JPS60104942U - Maximum or minimum value detection device - Google Patents

Maximum or minimum value detection device

Info

Publication number
JPS60104942U
JPS60104942U JP19507483U JP19507483U JPS60104942U JP S60104942 U JPS60104942 U JP S60104942U JP 19507483 U JP19507483 U JP 19507483U JP 19507483 U JP19507483 U JP 19507483U JP S60104942 U JPS60104942 U JP S60104942U
Authority
JP
Japan
Prior art keywords
minimum value
detection device
maximum
value detection
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19507483U
Other languages
Japanese (ja)
Inventor
内海　秀三
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP19507483U priority Critical patent/JPS60104942U/en
Publication of JPS60104942U publication Critical patent/JPS60104942U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の最大値検出装置を示すブロック図、第２
図はこの考案の一実施例を示すブ冶ツク図である。 図において３ｃ、３ｄ、３ｅは比較器、６は論理積ゲー
ト、７は切換器である。なお、図中同一符号は同一また
は相当部分を示す。Figure 1 is a block diagram showing a conventional maximum value detection device, Figure 2 is a block diagram showing a conventional maximum value detection device.
The figure is a block diagram showing an embodiment of this invention. In the figure, 3c, 3d, and 3e are comparators, 6 is an AND gate, and 7 is a switch. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力される３種類以上の複数ビットの２進数のうち最大
値、または最小値のみを検出して出力する装置において
、入力された前記複数ビットの２進数の大小を比較する
複数の比較器と、これら比較器の出力を入力し、その入
力の中の最大値または最小値だけを切換えて出力する切
換器とを備えることを特徴とする最大値または最小値検
出装置。A device that detects and outputs only the maximum value or the minimum value among three or more types of input multi-bit binary numbers, including a plurality of comparators that compare the magnitudes of the input multi-bit binary numbers; A maximum value or minimum value detection device comprising a switch which inputs the outputs of these comparators and switches and outputs only the maximum value or minimum value among the inputs.
JP19507483U 1983-12-19 1983-12-19 Maximum or minimum value detection device Pending JPS60104942U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19507483U JPS60104942U (en) 1983-12-19 1983-12-19 Maximum or minimum value detection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19507483U JPS60104942U (en) 1983-12-19 1983-12-19 Maximum or minimum value detection device

Publications (1)

Publication Number Publication Date
JPS60104942U true JPS60104942U (en) 1985-07-17

Family

ID=30752564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19507483U Pending JPS60104942U (en) 1983-12-19 1983-12-19 Maximum or minimum value detection device

Country Status (1)

Country Link
JP (1) JPS60104942U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642108U (en) * 1987-06-23 1989-01-09
JP2013037613A (en) * 2011-08-10 2013-02-21 Renesas Electronics Corp Arithmetic circuit and arithmetic unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642108U (en) * 1987-06-23 1989-01-09
JP2013037613A (en) * 2011-08-10 2013-02-21 Renesas Electronics Corp Arithmetic circuit and arithmetic unit
US8954483B2 (en) 2011-08-10 2015-02-10 Renesas Electronics Corporation Arithmetic circuit and arithmetic apparatus

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