JPS5863636U - switch input circuit - Google Patents

switch input circuit

Info

Publication number
JPS5863636U
JPS5863636U JP15735081U JP15735081U JPS5863636U JP S5863636 U JPS5863636 U JP S5863636U JP 15735081 U JP15735081 U JP 15735081U JP 15735081 U JP15735081 U JP 15735081U JP S5863636 U JPS5863636 U JP S5863636U
Authority
JP
Japan
Prior art keywords
rom
output
input circuit
group
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15735081U
Other languages
Japanese (ja)
Inventor
白水　清
Original Assignee
三菱重工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱重工業株式会社 filed Critical 三菱重工業株式会社
Priority to JP15735081U priority Critical patent/JPS5863636U/en
Publication of JPS5863636U publication Critical patent/JPS5863636U/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は公知のスイッチ入力回路を示すブロック線図、
第２図は本考案の一実施例を示すブロック線図、第３図
は第２図のスイッチとＲＯＭの出力との関係を示す図で
ある。 ＩＡ・・・Ａ群スイッチ、１Ｂ・・・Ｂ群スイッチ、２
Ａ・・・Ａ群の抵抗群、２Ｂ・・・Ｂ群の抵抗群、３Ａ
。 ３Ｂ・・・ＲＯＭ、４・・・バッファ、５Ａ・・・出力
Ａ０５．６・・・計算機、７・・・Ａ　　ＳＥＬ信号。FIG. 1 is a block diagram showing a known switch input circuit.
FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between the switch shown in FIG. 2 and the output of the ROM. IA...A group switch, 1B...B group switch, 2
A... resistance group of group A, 2B... resistance group of group B, 3A
. 3B...ROM, 4...Buffer, 5A...Output A05.6...Computer, 7...A SEL signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] それぞれ複数のスイッチを内蔵するＡ、８２群めスイッ
チと、Ａ群のスイッチ入力がそれぞれアドレス入力に接
続されたＲＯＭ　　Ａと、Ｂ群のスイッチ入力がそれぞ
れアドレス入力に接続されたＲＯＭ　　Ｂとを具え、上
記ＲＯＭ　　Ａ、ＲＯＭ　　Ｂの一方の出力線のうちの
１つを互いに他方のＲＯＭの出力禁止入力に接続し、上
記各群スイッチのうちの１つのスイッチがＯＮのときこ
れを識別する出力を上記各ＲＯＭが出力し、他のすべて
のスイッチ入力の出力することを禁止するようにしたこ
とを特徴とするスイッチ入力回路。It includes switches A and 82 groups each containing a plurality of switches, a ROM A in which the switch inputs of group A are connected to address inputs, and a ROM B in which switch inputs of group B are connected to address inputs. , connect one of the output lines of the ROM A and ROM B to the output inhibit input of the other ROM, and output an output that identifies when one of the switches in each group is ON. A switch input circuit characterized in that each of the above ROMs outputs an output and all other switch inputs are prohibited from outputting.
JP15735081U 1981-10-22 1981-10-22 switch input circuit Pending JPS5863636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15735081U JPS5863636U (en) 1981-10-22 1981-10-22 switch input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15735081U JPS5863636U (en) 1981-10-22 1981-10-22 switch input circuit

Publications (1)

Publication Number Publication Date
JPS5863636U true JPS5863636U (en) 1983-04-28

Family

ID=29949878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15735081U Pending JPS5863636U (en) 1981-10-22 1981-10-22 switch input circuit

Country Status (1)

Country Link
JP (1) JPS5863636U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184716U (en) * 1985-05-08 1986-11-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184716U (en) * 1985-05-08 1986-11-18

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