JPH01133646U - - Google Patents
Info
- Publication number
- JPH01133646U JPH01133646U JP2900888U JP2900888U JPH01133646U JP H01133646 U JPH01133646 U JP H01133646U JP 2900888 U JP2900888 U JP 2900888U JP 2900888 U JP2900888 U JP 2900888U JP H01133646 U JPH01133646 U JP H01133646U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- signal
- circuits
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図及び第２図は入出力制御装置のブロツク
図を示し、第１図は本考案の１実施例、第２図は
従来例、第３図は入出力制御装置の動作説明用の
タイムチヤートである。
１……ＣＰＵ、４ａ〜４ｈ……データラツチ回
路、５ａ〜５ｈ……入力ゲート回路、６……アド
レスデコーダ、９……オアゲート。
1 and 2 show block diagrams of the input/output control device. FIG. 1 is an embodiment of the present invention, FIG. 2 is a conventional example, and FIG. 3 is a timetable for explaining the operation of the input/output control device. It's a chat. 1... CPU, 4a to 4h... data latch circuit, 5a to 5h... input gate circuit, 6... address decoder, 9... OR gate.
Claims (1)
た複数のデータラツク回路及び複数の入力ゲート
回路等の入出力回路と、複数のデコード出力端子
がそれぞれ前記各入出力回路の制御用端子に接続
されゲート入力により作動して前記ＣＰＵより出
力された任意の入出力回路指定用のアドレス信号
から該当の前記入出力回路を選択し前記出力端子
より選択信号を出力するアドレスデコーダと、前
記ＣＰＵからのデータライト信号及びデータリー
ド信号が入力され出力信号が前記アドレスデコー
ダのゲート端子に入力されるオアゲートとを備え
てなる入出力制御装置。 A plurality of input/output circuits such as a plurality of data rack circuits and a plurality of input gate circuits are respectively connected to the CPU via a data bus, and a plurality of decode output terminals are respectively connected to control terminals of the respective input/output circuits. an address decoder which operates to select the corresponding input/output circuit from an address signal for designating an arbitrary input/output circuit outputted from the CPU and outputs a selection signal from the output terminal; and a data write signal and a data write signal from the CPU. An input/output control device comprising an OR gate to which a data read signal is input and an output signal is input to a gate terminal of the address decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2900888U JPH01133646U (en) | 1988-03-03 | 1988-03-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2900888U JPH01133646U (en) | 1988-03-03 | 1988-03-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01133646U true JPH01133646U (en) | 1989-09-12 |
Family
ID=31252837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2900888U Pending JPH01133646U (en) | 1988-03-03 | 1988-03-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01133646U (en) |
-
1988
- 1988-03-03 JP JP2900888U patent/JPH01133646U/ja active Pending
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