JPH0323894U

JPH0323894U -

Info

Publication number: JPH0323894U
Application number: JP11378589U
Authority: JP
Priority date: 1988-11-28
Filing date: 1989-09-28
Publication date: 1991-03-12

Description

[Brief explanation of the drawing]

第１図は本考案のＩＣメモリの一実施例の接続
図、第２図は一実施例の内部回路を示すブロツク
図、第３図は本考案のＩＣメモリの一実施例のブ
ロツク図、第４図は従来例のブロツク図、第５図
は書き込み動作タイミング図、第６図は読み出し
動作タイミング図である。１１′，２１……アドレス／データ時分割バス
、１２′，２２……アドレスラツチイネーブル信
号、１５′，２３……チツプイネーブル入力信号
、１４′，２４……書き込み要求信号、１３′，
２５……読み出し要求信号、１７，２６……アド
レスラツチ回路、１８，２７，２９，３２……ア
ドレスバス、１９，２８……メモリ装置、３０…
…バス切換回路、３１……バス切換信号。 FIG. 1 is a connection diagram of one embodiment of the IC memory of the present invention, FIG. 2 is a block diagram showing the internal circuit of one embodiment, and FIG. 3 is a block diagram of one embodiment of the IC memory of the present invention. FIG. 4 is a block diagram of a conventional example, FIG. 5 is a write operation timing diagram, and FIG. 6 is a read operation timing diagram. 11', 21... Address/data time division bus, 12', 22... Address latch enable signal, 15', 23... Chip enable input signal, 14', 24... Write request signal, 13',
25... Read request signal, 17, 26... Address latch circuit, 18, 27, 29, 32... Address bus, 19, 28... Memory device, 30...
...Bus switching circuit, 31...Bus switching signal.

Claims

[Claims for Utility Model Registration] (1) An address/data time division bus terminal to which address input and data input/output are performed, an address latch enable input terminal to which the address latch enable signal is input, and a data control terminal to which a control signal having at least one of read functions is input; an address latch circuit that holds an address input from the address/data time division bus terminal by a signal input of the address latch enable input terminal; and the address latch circuit. The output from the latch circuit is used as an address input, and the signal input from the data control terminal is used to input the address/
An IC memory comprising: a memory device that reads or writes data to a data time division bus terminal. (2) Address/data time division bus terminals for address input and data input/output, address input terminals for address input, address latch enable input terminals for inputting address latch enable signals, and data write or A data control terminal to which a control signal having at least one function of reading data is input, and an address input from the address/data time division bus terminal or the address input terminal is held at the signal input of the address latch enable input terminal. an address latch circuit that uses an output from the address latch circuit as an address input, and a memory device that reads or writes data to the address/data time division bus terminal using a signal input from the data control terminal; and selection of an address input method. a function selection terminal to which a signal is input, and switching an address input path to the address latch circuit to either the address/data time division bus terminal or the address input terminal based on the signal input from the function selection terminal. I characterized by comprising a switching circuit.
C memory.