JPH0221618B2 - - Google Patents
Info
- Publication number
- JPH0221618B2 JPH0221618B2 JP58132700A JP13270083A JPH0221618B2 JP H0221618 B2 JPH0221618 B2 JP H0221618B2 JP 58132700 A JP58132700 A JP 58132700A JP 13270083 A JP13270083 A JP 13270083A JP H0221618 B2 JPH0221618 B2 JP H0221618B2
- Authority
- JP
- Japan
- Prior art keywords
- storage device
- tracer
- initial state
- signal
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000700 radioactive tracer Substances 0.000 claims description 19
- 230000006870 function Effects 0.000 claims description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
【発明の詳細な説明】
技術分野
本発明は、記憶装置、特に情報処理装置におけ
る読み出し、書き込み動作の制御信号のトレーサ
を内蔵する記憶装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a storage device, and particularly to a storage device incorporating a tracer of control signals for read and write operations in an information processing device.
背景技術
従来、記憶装置に付加されるトレーサは、記憶
装置に内蔵されているため、記憶装置本体を初期
状態にセツトするイニシヤライズ信号によつて、
トレーサも同時にセツトされていた。したがつ
て、イニシヤライズ信号によつて初期状態にセツ
トするまでの記憶装置本体の動作状態の履歴を記
憶（以下トレースと呼ぶ）することができない欠
点があつた。BACKGROUND ART Conventionally, a tracer added to a storage device is built into the storage device, so that the tracer is added to the storage device by an initialization signal that sets the storage device itself to the initial state.
Tracers were also set at the same time. Therefore, there is a drawback that the history of the operating state of the storage device until it is set to the initial state by the initialization signal cannot be stored (hereinafter referred to as tracing).
発明の開示
本発明の目的は上述の欠点を解決し、イニシヤ
ライズ信号によつて初期状態にセツトするまでの
記憶装置本体の動作状態を、トレースすることが
出来るようにした装置を提供することにある。DISCLOSURE OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a device that can trace the operating state of a storage device until it is set to an initial state by an initialization signal. .
本発明は上述の目的を達成するために、演算処
理装置からの情報を書き込み、また情報を読み出
す機能を有し、かつ、読み出し、書き込みの動作
の制御信号及びインターフエース信号のトレーサ
を有する記憶装置において、イニシヤライズ信号
が、先にトレーサを初期状態にセツトした後、前
記イニシヤライズ信号が遅延レジスタを介して、
記憶装置本体を初期状態にセツトする手段を有す
るように構成されている。 In order to achieve the above-mentioned object, the present invention has a storage device having a function of writing information from an arithmetic processing unit and reading information, and having a tracer of control signals of read and write operations and an interface signal. , the initialize signal first sets the tracer to the initial state, and then the initialize signal passes through a delay register,
The storage device is configured to have means for setting the main body of the storage device to an initial state.
本発明によればトレーサがイニシヤライズ信号
により初期状態にセツトされるまでの時間を遅延
時間とする遅延レジスタを介して、トレーサを除
く記憶装置本体にイニシヤライズ信号が入力され
るため、記憶装置本体がイニシヤライズ信号によ
つて初期状態にセツトされるまでの動作状態をト
レースできるという効果がある。 According to the present invention, the initialization signal is input to the storage device main body except for the tracer via the delay register whose delay time is the time until the tracer is set to the initial state by the initialization signal, so that the storage device main body is initialized. This has the advantage that the operating state until it is set to the initial state can be traced by the signal.
発明を実施するための最良の形態
次に本発明の実施例について図面を参照して説
明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の実施例のブロツク図で、記憶
装置のトレース情報６はデータレジスタ１を介し
てトレーサメモリ２に送られる。トレーサメモリ
２への書き込みアドレス指定は演算レジスタ３と
アドレスレジスタ４によつて、下位番地から順番
に行なわれる。トレーサメモリ２への書き込み指
定はライトパルス１３がゲート１５を介してライ
トパルス１４として入力される。 FIG. 1 is a block diagram of an embodiment of the present invention, in which trace information 6 in a storage device is sent to a tracer memory 2 via a data register 1. Write addresses to the tracer memory 2 are specified by the arithmetic register 3 and the address register 4 in order from the lowest address. To designate writing to the tracer memory 2, a write pulse 13 is inputted as a write pulse 14 via a gate 15.
さて、イニシヤライズ信号１６がゲート１８を
介してトレーサに入力すると、停止条件回路５の
停止条件が解除され、ライトパルス１３がトレー
サメモリ２へ入力されるとともに、アドレスレジ
スタ４がリセツトされ、下位番地から順番に書き
込みが行われる。 Now, when the initialization signal 16 is input to the tracer via the gate 18, the stop condition of the stop condition circuit 5 is canceled, the write pulse 13 is input to the tracer memory 2, and the address register 4 is reset, starting from the lower address. Writing is performed in order.
一方、イニシヤライズ信号１６は遅延レジスタ
１７によつて、トレーサ全体が初期状態にセツト
されるために必要な時間だけ遅延され、その遅延
されたイニシヤライズ遅延信号２０が記憶装置本
体２１に入力される。 On the other hand, the initialization signal 16 is delayed by the delay register 17 by the time necessary to set the entire tracer to its initial state, and the delayed initialization signal 20 is input to the storage device body 21.
したがつて、本発明によれば、先にトレーサが
初期状態にセツトされた後に、記憶装置本体が初
期状態にセツトされることとなり、記憶装置本体
がイニシヤライズ信号によつて初期状態にセツト
されるまでの動作状態をトレースすることが出来
るという効果がある。 Therefore, according to the present invention, the tracer is first set to the initial state, and then the storage device main body is set to the initial state, and the storage device main body is set to the initial state by the initialization signal. This has the effect of being able to trace the operating state up to that point.
第１図は本発明の実施例においてトレーサ部分
を特に詳細に示したブロツク図である。
１…データレジスタ、２…トレーサメモリ、３
…演算回路、４…アドレスレジスタ、５…停止条
件回路、６，７…トレース情報、８…トレース読
み出しデータ情報、９…読み出し指定、１０…書
き込み指定アドレス情報、１１…停止信号、１２
…停止条件信号、１３，１４…ライトパルス、１
５，１８…ゲート、１６，１９…イニシヤライズ
信号、１７…遅延レジスタ、２０…イニシヤライ
ズ遅延信号、２１…記憶装置本体。
FIG. 1 is a block diagram showing the tracer portion in particular detail in an embodiment of the present invention. 1...Data register, 2...Tracer memory, 3
...Arithmetic circuit, 4...Address register, 5...Stop condition circuit, 6, 7...Trace information, 8...Trace read data information, 9...Read designation, 10...Write designation address information, 11...Stop signal, 12
...Stop condition signal, 13,14...Write pulse, 1
5, 18...Gate, 16, 19...Initialize signal, 17...Delay register, 20...Initialize delay signal, 21...Storage device main body.
Claims (1)
報を読み出す機能を有し、かつ読み出し、書き込
み動作の制御信号及びインターフエース信号の履
歴を記憶するメモリ（以下トレーサと呼ぶ）を有
する記憶装置において、イニシヤライズ信号が、
先にトレーサを初期状態にセツトした後、前記イ
ニシヤライズ信号が遅延レジスタを介して前記ト
レーサ以外の記憶装置本体を初期状態にセツトす
る手段を有することを特徴とする記憶装置。1 In a storage device that has the function of writing and reading information from an arithmetic processing unit, and also has a memory (hereinafter referred to as a tracer) that stores the history of control signals and interface signals for read and write operations, initialization is performed. The signal is
A storage device characterized by having means for first setting a tracer in an initial state, and then using the initialize signal to set the main body of the storage device other than the tracer in an initial state via a delay register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58132700A JPS6027049A (en) | 1983-07-22 | 1983-07-22 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58132700A JPS6027049A (en) | 1983-07-22 | 1983-07-22 | Memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6027049A JPS6027049A (en) | 1985-02-12 |
| JPH0221618B2 true JPH0221618B2 (en) | 1990-05-15 |
Family
ID=15087505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58132700A Granted JPS6027049A (en) | 1983-07-22 | 1983-07-22 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027049A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0417992A (en) * | 1990-05-12 | 1992-01-22 | Sumitomo Electric Ind Ltd | Power damper |
-
1983
- 1983-07-22 JP JP58132700A patent/JPS6027049A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0417992A (en) * | 1990-05-12 | 1992-01-22 | Sumitomo Electric Ind Ltd | Power damper |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6027049A (en) | 1985-02-12 |
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