JPH0320837B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to semiconductor memory devices, and relates to the time required for read-modify-write (writing new information known in advance immediately after reading). The present invention relates to a semiconductor memory device with a shortened term.

[Prior Art] Generally, in semiconductor storage devices, read and write operations are performed independently, and a minimum time interval called a cycle time is defined for each, but when new data is written to the same location after a read operation, It is known that an operation called read-modify-write allows reading and writing to be executed in a shorter time than independently executing them.

FIG. 1 is a block diagram showing the main parts of an example of a conventional semiconductor memory device. 1 is a memory cell group, 2 is a sense amplifier (flip type, input and output are common), 3 is a write drive circuit, 4 is a write data input terminal, 5 and 6 are electronic switches consisting of P channel MOS transistors, 7 is a read data register, 8 is a read data output terminal, 9,
10 is a first digit common line, 9' and 10' are second digit common lines, 11 is an electronic switch 5,
6 control terminal.

The operation of the semiconductor memory device shown in FIG. 1 will be explained. During reading operation, electronic switches 5 and 6
is in the on state, the output signal from a selected cell in the memory cell group 1 is amplified by the sense amplifier 2, and either the first digit common line 9 or 10 is activated. electronic switch 5, 6 second digit common line 9' or 1
0' to set the read data register 7. As a result, read data can be obtained from the output terminal 8.

On the other hand, during the write operation, the electronic switches 5 and 6
is turned off, and in accordance with the data applied to the write data input terminal 4, either the first digit common line 9 or 10 is energized by the write drive circuit 3, and the data is written to the memory cell group 1. Send a pulse.

That is, the conventional semiconductor memory device is characterized in that the electronic switches 5 and 6 are turned on during the read cycle period and turned off during the write cycle period. Therefore, in order to perform a write operation following a read operation, it is necessary to wait for the electronic switches 5 and 6 to change from on to off in response to a timing signal applied to the control terminal 11 from the outside. That will take time.

That is, conventional semiconductor memory devices have a drawback in that it is difficult to perform read/modify/write operations at high speed.

[Object of the Invention] An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor memory device that can operate at high speed with a simple circuit.

[Structure of the Invention] A semiconductor memory device of the present invention includes a pair of first digit common lines and a pair of second digit common lines connected via a pair of electronic switches, and a second digit common line of the pair. Detecting that either one of the read data register connected between the lines and the second digit common line is energized, and outputting a control signal to turn off the pair of electronic switches after a predetermined delay. The system includes an electronic switch control means for controlling the electronic switch.

[Description of Examples] Examples of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the main parts of the first embodiment of the present invention.

In the first embodiment, a pair of first digit common lines 9 and 10 and a pair of second digit common lines 9' and 10 are connected via a pair of electronic switches 5 and 6.
10', the read data register 7 connected between the pair of second digit common lines 9', 10', and either one of the second digit common lines 9', 10' is energized. The device includes an electronic switch control means consisting of a gate circuit 12 consisting of an OR circuit and a delay circuit 13, which detects and outputs a control signal 14 which turns off the pair of electronic switches 5 and 6 after a predetermined delay. Note that 15 is a reset input terminal to the gate circuit 12, which is normally kept at a low level.

Next, the read/modify/write operation of the first embodiment will be explained. First, the electronic switches 5 and 6 are turned on.
(Reset terminal 15, second digit line 9', 1
Since both 0' are at low level, the gate circuit 12
Since the output is at a low level and the control signal 14 is not sent out, the electronic switches 5 and 6 are in the on state. ) In this state, the gate circuit 12
When either one of the digit common lines 9' or 10' is energized, the output changes to high level and a detection signal 14' is sent to the delay circuit 13. and,
The delay circuit 13 activates the electronic switch 5, while the second digit common line 9' or 10' is activated.
In order to prevent the electronic switch 6 from being turned off, the electronic switch control signal 14 is output with a predetermined delay. The electronic switches 5 and 6 are turned off by this control signal 14, and a write operation is subsequently performed. Here, the electronic switches 5 and 6 receive the control signal 1
4 is at a high level, it is in an off state, and when it is at a low level, it is in an on state.

That is, according to the first embodiment, the electronic switches 5 and 6 change from on to off as a result of their own operation without controlling the electronic switches 5 and 6 from the outside. The time required to change to an operating state is shortened, and read/modify/write operations can be speeded up.

Note that when the second digit lines 9' and 10' are both low level and not in a reading operation, the reset terminal 15 of the gate circuit 12 is set to high level, turns off the electronic switches 5 and 6, and prohibits erroneous reading of data. used to do.

FIG. 3 is a block diagram showing the main parts of a second embodiment of the present invention.

7' is a two-terminal read data register, 16
is the reset circuit of the read data register 7'.
It consists of channel MOS transistors 20 and 21. 17 is its reset input terminal, 1
8 and 19 are N-channel MOS transistors,
The rest is the same as the first embodiment shown in FIG.

In the second embodiment shown in FIG. 3, when performing a read/modify/write operation, first a reset signal is applied to the reset input terminal 17 of the read data register 7', and the reset circuit 16 resets the read data register 7'. Leave it in the reset state.
Next, electronic switches 5 and 6 are turned on. When a read operation energizes the second digit common line, either 9' or 10', one of the read data registers 7' changes to the set state. Therefore, the gate circuit 12 outputs the detection signal 14' to the electronic switches 5 and 6 via the delay circuit 13, so that the electronic switches 5 and 6 are turned off.

Thereafter, even if the write drive circuit 3 operates to execute a write operation, the electronic switches 5 and 6 are turned off, so the read data register 7'
does not affect.

N-channel MOS transistors 18 and 1
Depending on whether the digit common line 9' or 10' is activated (high level in this case), either one of the digit common lines 9' or 10' is turned on, and if the transistor 18 is on, the read data is output. When the output terminal 8 is at a high level, and when the transistor 19 is on, it is at a low level.

Read data register 7' is connected to reset terminal 1
An energized reset signal is applied to the circuit 7, and the reset circuit 16 returns the circuit to the reset state.

In addition, in the explanation of FIG. 3, the gate circuit 12
is placed before the delay circuit 13, but this means that the delay circuit 13 comes first (in this case, two delay circuits are required), and then the gate circuit 12
Needless to say, you can leave it behind.

Furthermore, in the above description, an analog switch using a P-channel MOS transistor was used as the electronic switch, and a circuit including a gate circuit consisting of a delay circuit and an OR circuit was used as the electronic switch control means. Needless to say, it can be replaced with another circuit having the same function.

[Effects of the Invention] As explained in detail above, the semiconductor memory device of the present invention has a means consisting of a simple circuit that generates and controls the on/off state of an electronic switch during read/modify/write from its own read data. The electronic switch can be turned on and off in a shorter time compared to conventional control using external timing signals, so it has the advantage of being able to operate at high speed and with a simple circuit. have.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a main part of an example of a conventional semiconductor memory device, and FIGS. 2 and 3 are block diagrams showing main parts of a first and second embodiment of the present invention, respectively. 1...Memory cell group, 2...Sense amplifier, 3
...Write drive circuit, 4...Write data input terminal, 5, 6...Electronic switch, 7, 7'...Read data register, 8...Read data output terminal, 9, 10...First digit common line, 9',
10'...Second digit common line, 11...Control terminal, 12...Gate circuit, 13...Delay circuit, 14...Control signal, 15...Reset input terminal, 16...Reset circuit, 17... ...Reset input terminal, 18, 19, 20, 21...transistor.

Claims (1)

[Claims] 1 a pair of first digit common lines and a pair of second digit common lines connected via a pair of electronic switches; a read data register connected between the pair of second digit common lines; electronic switch control means for detecting that either one of the common lines is energized and outputting a control signal for turning off the pair of electronic switches after a predetermined delay. .