JPS6047294A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To improve the wiring efficiency by using a read/write field effect transistor (FET) in a static RAM cell as an ROM cell and constituting the ROM and the RAM in one cell to reduce an address decoder. CONSTITUTION:The static RAM cell 45 consists of an inverter comprising FET 29-32 and FETs 27, 28 constituting the ROM cell connected between its output and digit lines 41, 42 and decided to obtain a prescribed ROM output by the size. At read of the ROM cell, the lines 41, 42 are precharged by a signal phiP, signals phiRW and phiROM go to ''H'' and the level of the lines 41 and 42 is decided by the ratio of size of depletion FETs 23, 25 of pull-up circuits 43, 44, enhancement FETs 24, 26 and FETs 27, 30, 28 and 32. The FETs 27, 28 are used as the ROM cell by designing the size of the FETs 27, 28 depending whether the level of the lines 41, 42 is at ''H'' or the RAM cell data is outputted and one goes to ''H'' and the other goes to ''L''.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to semiconductor memory circuits kAEs.

[Conventional branch body]

In recent years, as semiconductor integrated circuits have become more highly integrated, microprocessors, etc. have become more multifunctional, and one chip has a high capacity ROM (Read Only Memory) and RAM.
(Random Access Memory) has been commercialized. One such microprocessor is a dynamic programming type microprocessor that uses internal AMe as a program memory and provides flexibility in programming. Even when this method is used, a ROM is usually used as part of the program memory for tests and an initial loader program for loading programs.

When such a microprocessor is actually installed, the address decoder of the ROM and RAM cannot be shared because the size of the ROM cell is very small compared to the size of the RAM cell. Also, it is not possible to share the read/write edge of J, tAM and the read line of It (JM). The ROM and RAM are each provided with an address decoder τ at a different location, and the output thereof is selected by a multiplexer.

Fig. 1 is a circuit diagram showing the bold part of a static LLAM made up of six conventional Jp E 'I's, Fig. 2 is a timing chart for its reading, and Fig. 3 is its timing for writing. It is a chart.

Next, the operation will be explained with reference to these categories.

During reading, precharge FETI,2 is turned on by precharge signal -1, and data h! '12113 is precharged. Next, read/write FET3.4
is turned on by the signal yJRW, and the data written in the FETs 5°5' and 6.6' forming the static RAM cell 14 is read out to the digit line 12, amplified by the sense amplifier 7, and read out to the output OUT. be done.

When entering 1°, the tigit line 12.13 is similarly precharged by F'ET1.2. Next, write FE
T8 and 9 are turned on by the write signal ~, and at the same time li'
ET3.

4 turns on. And positive phase and negative phase buffers 10°11
The input IN passed through the digit line 12.13 is written into the static RAM cell 14. In such a static I (AM), the read data is always the data in the RAM cell.

As described above, the conventional semiconductor memory circuit has the disadvantage that the address decoder is provided separately and a wiring area for it is also required, which increases the required area of the semiconductor chip.

[Purpose of the invention]

The object of the present invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a semiconductor memory circuit in which M cells can be configured on the same cell, the number of address decoders can be reduced, and wiring efficiency can be improved.

[Structure of the invention]

The semiconductor memory circuit of the present invention includes a pair of inverters whose respective inputs and outputs are cross-connected, and an RO connected between the outputs of the pair of inverters and a pair of digit lines.
A static RAM cell consisting of a pair of transistors that constitutes an M cell and whose dimensions are determined to obtain a constant ROM output, and data reading/writing of the static RAM cell connected to each of the pair of digit lines. and the precharge transistor for R6.
a pull-up circuit for M reading, a pair of sense amplifiers for detecting read data of the pair of digit lines, and outputs of the pair of sense amplifiers in response to reading of the static RAM cell or the ROM cell. and a control circuit that controls the output of the static RAM cell or the ROM cell to be obtained.

[Explanation of Examples]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram showing a main part of an embodiment of the present invention.

In this embodiment, each input and output are cross-connected.
A pair of inverters consisting of ET29, 30, 31.32, the output of this pair of inverters, and a pair of digit lines 4
≠≠=%F connected between 1.42 to form a ROM cell and determined to obtain a predetermined ROM output according to its dimensions
Static RAM cell 4 consisting of ET 27, 28
5, precharger transistors FgT21, 22 for reading data/input of the static RAM cell 45 connected to each of the pair of disks HJ41, 42, and PL3T23, 24, 25, 26 for reading the data cell. A pull-up circuit 43.44, a pair of sense amplifiers 7'33.34 for detecting the read data of the pair of digits a41 and 42, and this pair of sense amplifiers 33.3.
4 to the static RAM cell 45 or the ROM
Static RA to output OUT in response to cell reading
It is constructed by including an AND gate 39 for controlling the output of the M cell 44 or the ROM, and a control circuit 46 connected from the mismatch gate 40.

Next, the timing chart for reading the static RAM cell shown in FIG. 5, the timing chart for reading the ROM cell shown in FIG. The operation of this embodiment will be explained with reference to the chart.

When reading data from the static RAM cell 45, the precharge FET 21 is activated by the signal D as in the conventional example.
, 22 precharge digit lines 41,42.

Next, FgTs 27 and 28 are turned on, and the data in the static RAM cell 45 is read out to the dector lines 41 and 42.
It is amplified by sense amplifiers 33 and 34. The output of the sense amplifier 34 is the signal □. When the gate is at a low level, the AND gate 39 does not open and is masked, resulting in the output OUT.
As Ll, the output of the sense amplifier 33 is read out, and the data in the RAM 7' is read out.

When reading data from a ROM cell, first, the F1iiTs 21.22 precharge the Tigid line 41.42 in response to the signal -1. Next, the signal 'RW l' R6 becomes high level, causing the data a! 41.

The level of 42 is the pull-up circuit 43, 44'(i1'
It is determined by the size ratio of the configuration FETs 23, 25 and enhancement FETs 24, 26, and the static f (enhancement in AMM cell 5) ET27, 30, 28°32.Here, FFJT27
．． By designing the dimensions of 28 to either the case where the levels of the Tigit lines 41 and 42 are both high level, or the case where RAM cell data is output as usual and one is high level and the other is low level, This pair of FI4Ts 27 and 28 is used as a ROM cell. The level of the digit lines 41 and 42 is the sense amplifier 33.
．． 34 and its output is amplified by mismatch gate 40
is input, and corresponding to the dimensions of FET27 and 28, digit &! When the digit lines 41 and 42 are at a high level, a low level is output, and when the digit lines 41 and 42 are at a low level and a high level, a high level is output as the output OUT.

When writing a booter to a static RAM cell, go to the signal. When □ is always at a low level, li'ET24.26 is turned off, and the operation is similar to that of a conventional static RAM cell.

〔Effect of the invention〕

As explained above in detail, the semiconductor memory circuit of the present invention has a read/write F B in a static RAM cell.
Since jLOM and RAM are configured in the same cell using T as a ROM cell, it is possible to share the address decoder, which was previously required separately, and it has the effect of increasing wiring efficiency. There is.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the main parts of a conventional static R/AM, Fig. 2 is a timing chart during reading, and Fig. 3 is a circuit diagram showing the main parts of a conventional static R/AM.
4 is a circuit diagram showing a main part of an embodiment of the present invention. FIG. 5 is a timing chart for reading the static I(, AM) cell. FIG. FIG. 7 is a timing chart for reading the ROM cell, and FIG. 7 is a timing chart for writing the static RAM cell. 1 to 9 Enhancement FET, 5', 6
'−゛. ...Depression FET, 10.11...
・) Kutufa, 12.13...Dicts l-line, 14...Static RAM cell, 21,2
2, 24, 26, 27° 28. 32, 35, 36...
...Amplification) ment PET. 23.25,29,31...Depression FE
T, 37°38...Buffer, 39...
・And gate, 40...Inconsistency gate, 41
, 42... Digit line, 43.44...
...Pull-up circuit, 45...Static R
AM cell, 46...control circuit, UP, φRWP
~# “ROM... Signal, OUT...
Output, IN...Input. ,,7"=7'n・, Agent Patent attorney Susumu Uchihara () ゝ -1 ] ] 11−−−−−−−−−−−−−−1−H TO−−−
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Claims (1)

[Claims] A pair of inverters whose respective inputs and outputs are cross-connected are connected between the outputs of the pair of inverters and a pair of digit lines to form a ROM cell, and the ROM cell is configured to have a predetermined R depending on its dimensions.
A static RAM cell consisting of a pair of transistors determined to obtain an OM output, and the static RAM cell connected to each of the pair of digit lines.
A precharge transistor for reading/writing cell data, a pull-up circuit for reading the ROM cell, a pair of sense amplifiers for detecting read data on the pair of digit lines, and outputs of the pair of sense amplifiers are connected to the static RAM. The static RAM cell or the RO is connected to the output in response to reading of the static RAM cell or the ROM cell.
1. A semiconductor memory circuit comprising: a control circuit for controlling the output of an M cell to be served.