JPH0554651A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To reduce the number of data busses running in a chip to reduce the chip size and to improve the characteristic. CONSTITUTION:An input/output buffer circuit 6 is so formed that a data bus 9 is shared among write per bit data PBD, write data, and read data in time division. A latch circuit 10 is provided to latch write per bit data PBD at a pre-scribed timing, and it is transmitted to a write amplifying circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit having a function of writing data for each bit of an input / output multi-bit structure by distinguishing whether or not to write data in the same cycle. ..

[0002]

2. Description of the Related Art In a semiconductor memory circuit having an input / output multi-bit structure, a function of performing writing by discriminating whether or not to write data bit by bit in the same cycle is called a write per bit function. The write per bit function will be briefly described by taking a dynamic RAM as an example.

3 and 4 are a block diagram of a semiconductor memory circuit of this type and a timing diagram of each terminal signal when the write per bit function is used, respectively.

If the write signal WE is set to the low level active level when the row address strobe signal RAS is set to the low level active level, the write per bit function becomes effective. In this case, the row address strobe signal RAS
Whether or not the subsequent write operation of the bit is performed is discriminated depending on the level state of the data input / output terminal IOj (j = 1 to n) at the time of falling. Specifically, if the data input / output terminal IO1 is at a low level and IO2 to IO4 are at a high level when the row address strobe signal RAS falls,
In the write operation performed during the same RAS cycle, the data applied to the input / output terminal IO1 becomes invalid, and the memory cell corresponding to this holds the old data.

Further, the data applied to the input / output terminals IO2 to IO4 becomes valid, and the operation of writing these data to the memory cells corresponding thereto is performed.

Next, the operation of the semiconductor memory circuit having the write per bit function will be described. FIG. 5 (A),
(B) is a timing chart of signals of respective parts for explaining the operation. FIG. 5 (A) is a read cycle, FIG. 5 (B)
Indicates a write cycle.

When the row address strobe signal RAS falls, the write per bit data PBD is taken in from the data input / output terminal IOj and the internal 12 of the input / output buffer circuit 6a is taken.
It is latched and placed on the write per bit data bus 11.

Since the memory cell is refreshed for a certain period of time after the row address strobe signal RAS falls, writing and reading operations to the memory cell array 1 are prohibited by the internal signal Φ. When the internal signal Φ changes to a high level, writing and reading operations to the memory cell array 1 become possible.

Therefore, in the case of a read cycle, the internal signal Φ
Changes to a high level, the read control signal RC for performing the read operation becomes a high level, and the read data is transmitted from the memory cell array 1 to the data bus 9 via the read amplifier circuit 8. Therefore, the data bus 9 is in the active period from the fall of the row address strobe signal RAS to the change of the internal signal Φ to the high level.
Is not used.

In the write cycle, when the column address strobe signal CAS and the write signal WE change to low active levels after the row address strobe signal RAS falls, the write data is taken in from the data input / output terminal ICj. It is latched inside the circuit 6a and placed on the data bus 9. FIG. 5B shows that the column address strobe signal CAS and the write signal WE change to low level before the internal signal Φ which is the access prohibition signal to the memory cell is released after the row address stove signal RAS falls. It is an example.

When the column address strobe signal CAS and the write signal WE change to low level, the write data is fetched and latched and placed on the data bus 9. However, since the internal signal Φ is at low level, writing to the memory cell array is performed. No action is taken.

When the internal signal Φ changes to the high level, the write control signal WC for the write operation becomes the high level, and in the write per bit mode (when the write per bit flag PBF is at the high level). The write operation is performed by taking the logic with the write per bit data PBD. That is, when the write per-bit data PBD is "1", the corresponding channel of the write amplifier circuit 7 is activated to perform the write operation to the memory cell, and when the write per-bit data PBD is "0". , The write operation to the corresponding memory cell is not performed regardless of the level of the write control signal WL.

Therefore, although write data is on the data bus 9, the data is not used until the internal signal Φ changes to high level.

[0014]

The conventional semiconductor memory circuit described above has a structure in which the data bus 9 and the write per bit data bus 11 are connected from the input / output buffer circuit 6a to the write amplifier circuit 7, respectively. Due to the layout, these buses must run long distances. Therefore, the size of the input / output buffer circuit 6a that drives these buses becomes large, which affects the chip size. Further, if the number of buses themselves is large, not only does this affect the chip size, but there is also the drawback that the speed of signals that must be traversed by wiring such as silicide is delayed, and the characteristics of the product are deteriorated. This drawback becomes more prominent in the multi-bit configuration such as 16 bits and 32 bits.

[0015]

A semiconductor memory circuit according to the present invention is provided with a memory cell array having a plurality of memory cells for writing and storing data in these memory cells, and for inputting a plurality of bits of write data and write per bit data. Then, a plurality of data input / output terminals for outputting read data, a data bus for transmitting a plurality of bits of data, and at a predetermined timing, the respective data are written for writing into the input / output terminals and write per-bit data are taken in. An input / output buffer circuit for transmitting to the data bus and fetching read data of the data bus for transmitting to each of the data input / output terminals; a latch circuit for fetching and outputting write per bit data of the data bus at a predetermined timing; When the write per bit mode is provided with the write amplifier, the write power from the latch circuit is And a writing write amplifying circuit data of the data bus in a predetermined memory cell of activating said corresponding write amplifier said memory cell array are in accordance with the bit data.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, a memory cell array 1 is provided which has a plurality of memory cells and writes and stores data in and from these memory cells in a selected state.
An address buffer circuit 2, which brings a predetermined memory cell of the memory cell array 1 into a selected state according to the address signal AD.
Row address decoder 3, and column address decoder 4
A plurality of data input / output terminals IOj (j = 1 to n) for inputting a plurality of bits of write data and write per bit data PBD and outputting read data; and a data bus 9 for transmitting a plurality of bits of data. , The data for writing the input / output terminal IOj and the write per-bit data PBD are taken in at a predetermined timing, and the data bus 9
An input / output buffer circuit 6 for transmitting the read data from the data bus 9 to the respective data input / output terminals IOj;
A latch circuit 10 which takes in and outputs the write per bit data PBD of the data bus 9 at a predetermined timing, and a plurality of write amplifiers, and in the write per bit mode, a corresponding write amplifier according to the write per bit data PBD from the latch circuit 10. A write amplifier circuit 6 for activating the memory cell array 1 to write the data of the data bus 9 to a predetermined memory cell of the memory cell array 1, and a read amplifier circuit 8 for amplifying the data read from the memory cell array 1 and transmitting the amplified data to the data bus 9. The row address strobe signal RAS, the column address strobe signal CAS, the write signal WE, and the output control signal OE are input, and the internal signal Φ, the write control signal WC, the read control signal RC, the write per bit flag PBF, the latch signal LCH, etc. Is output to control the operation of each part. And it has a configuration and a 5.

Next, the operation of this embodiment will be described.
FIG. 2 is a timing chart of each control signal for explaining the operation of this embodiment.

As in the conventional example, when the write signal WE is a low active level when the row address strobe signal RAS changes from a high inactive level to a low active level, the write per bit mode is entered. Immediately after the row address strobe signal PBD becomes active level, the write per bit data PBD transmitted to the data bus 9 by the input / output buffer circuit 6 is latched by the latch circuit 10.
Latch to. After the latch circuit 10 latches the write per bit data PBD, the internal signal Φ and the write control signal WC become high level, and the write amplifier circuit 7 causes
The write data transmitted to the data bus 9 is written into the corresponding memory cell of the memory cell array 1 according to the write per bit data PBD. The input / output buffer circuit 6 is
When the write per bit data PBD is placed on the data bus 9, the output end of the buffer circuit for transmitting the write data is set to high impedance, and when the write data is placed, the write per bit data PBD is transmitted. The output end of the buffer circuit on the side is set to high impedance.

As described above, since the data bus 9 is used for the write per bit data PBD and the data for writing and the read data in a time division manner, compared to the case where these are transmitted by separate buses as in the conventional case. The number of buses can be halved, so that the chip size can be reduced and the characteristics can be improved.

[0022]

As described above, according to the present invention, the write per-bit data, the write data and the read data are transmitted by using the common data bus in a time division manner, so that the inside of the chip can be improved. Since the number of running data buses can be significantly reduced, there is an effect that the chip size can be reduced and the characteristics can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory circuit.

FIG. 4 is a timing diagram of each terminal signal for explaining a write per bit function of the semiconductor memory circuit shown in FIG.

FIG. 5 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory circuit shown in FIG.

[Explanation of symbols]

 1 memory cell array 2 address buffer circuit 3 row address decoder 4 column address decoder 5, 5a control signal 6, 6a input / output buffer circuit 7 write amplifier circuit 8 read amplifier circuit 9 data bus 10 latch circuit 11 write per bit data bus

Claims (2)

[Claims] 1. A memory cell array having a plurality of memory cells for writing and storing data in these memory cells, and a plurality of data input / output terminals for inputting a plurality of bits of write data and write per bit data and outputting read data. And a data bus for transmitting a plurality of bits of data, and at a predetermined timing, each of the data is written into the input / output terminal and write-per-bit data is fetched and transmitted to the data bus to read the data from the data bus. An input / output buffer circuit for transmitting to each of the data input / output terminals, a latch circuit for capturing and outputting write per bit data of the data bus at a predetermined timing, and a plurality of write amplifiers are provided, and in the write per bit mode, The corresponding write amplification according to the write per bit data from the latch circuit And a write amplifier circuit for activating a memory device to write the data of the data bus to a predetermined memory cell of the memory cell array. 2. When the row address strobe signal changes from the inactive level to the active level and the write signal is at the active level, the write per bit mode is entered, and the data immediately after the row address strobe signal becomes active level. The write per-bit data transmitted to the bus is latched by a latch circuit, and the latch circuit latches the write per-bit data, and then the write amplifier circuit transfers the write data transmitted to the data bus to the write per-bit data. 2. The semiconductor memory circuit according to claim 1, wherein data is written in a corresponding memory cell of the memory cell array according to bit data.