JP3226950B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More specifically, the present invention relates to a method for testing a memory cell. In recent years, the capacity of semiconductor memory devices has been increased, and the test time of the large-capacity cell takes a long time in proportion to the capacity, and the test cost is increasing. Therefore, it is necessary to shorten the test time and reduce the test cost.

[0002]

2. Description of the Related Art FIG. 7 shows an input buffer and a write amplifier in a conventional DRAM. Input buffers 11A-1
1D is provided for each bit data DQ1 to DQ4 of the input data. Each of the input buffers 11A to 11D includes an inverter 12, a PMOS transistor 13, a well-known latch 14 including two inverters, and inverters 15, 16.
Are connected in series. The latch signal generation circuit 17 is connected to the gate terminal of the PMOS transistor 13, and receives the data latch signal φL. Therefore, the input buffers 11A to 11D latch the bit data DQ1 to DQ4 when the data latch signal φL switches from L level to H level.

The latch signal generation circuit 17 includes an inverter 18
20 and a NAND circuit 21. Inverter 18 has column address strobe signal CAS
, And inverts the output level, and the inverter 19 inputs the write control signal WE to invert the level and outputs the inverted signal. The NAND circuit 21 receives the outputs of the two inverters 18 and 19 and outputs the output signal to the inverter 2.
The signal is output as a data latch signal φL through the signal 0. That is, the latch signal generation circuit 17 outputs the H level data latch signal φL only when both the column address strobe signal / CAS and the write control signal / WE are at the L level.
Is output to each of the input buffers 11A to 11D. When one of the column address strobe signal / CAS and the write control signal / WE is at an H level, the latch signal generation circuit 17 outputs an L level data latch signal φL.
Is output to each of the input buffers 11A to 11D.

A write amplifier 22 is provided in an input buffer 11A.
A, 22E to 22H are connected in parallel, and the input buffer 1
Write amplifiers 22B to 22D are connected to 1B to 11D via selection circuits 23A to 23C.

Each of the selection circuits 23A to 23C is configured by connecting an NMOS transistor 24 and a PMOS transistor 25 in parallel, and a test mode signal φTEST is applied to gate terminals of the transistors 24 and 25.
NMOS transistors 24 of selection circuits 23A to 23C
Is connected to the output of the input buffer 11A. The PMOS transistor 25 of the selection circuit 23A is connected to the input buffer 1
1B, the PMOS transistor 25 of the selection circuit 23B is connected to the output of the input buffer 11C,
The PMOS transistor 25 of C is connected to the output of the input buffer 11D.

Therefore, when test mode signal φTEST is low,
At the time of a normal write operation at the level, the selection circuit 23
The PMOS transistors 25 of A to 23C are turned on, and the bit data DQ2 to DQ4 latched in the input buffers 11B to 11D are applied to the write amplifiers 22B to 22D. In the test mode in which the test mode signal φTEST is at the H level, each of the N circuits of the selection circuits 23A to 23C is
The MOS transistor 24 turns on, and the input buffer 11A
Bit data DQ1 latched in the write amplifier 22
B to 22D.

Each of the write amplifiers 22A to 22H has a pair of bus line pairs DB1, DB1 to DB8, and a bar DB.
8 are connected. Each of the write amplifiers 22A to 22H is configured by connecting a series circuit of the inverters 26 and 27 and the NMOS transistor 29 and a series circuit of the inverter 28 and the NMOS transistor 30 in parallel. Bus line DB1 on the non-inverting side of each of write amplifiers 22A to 22H
To DB8 are connected to the respective NMOS transistors 29, and the inversion-side bus lines DB1 to DB8 are connected to the respective NMOS transistors 30.

Both NMOs of each of the write amplifiers 22A to 22D
Write activation signal φW is input to the gate terminals of S transistors 29 and 30. Each light amplifier 22A ~
22D is activated when H-level write activation signal φW is input, and its bus line pair DB1, bar DB1-DB
4. The amplified data is output to the bar DB4.

Further, both N of each of the write amplifiers 22E to 22H
The activation signal generation circuit 31 is connected to the gate terminals of the MOS transistors 29 and 30. The activation signal generation circuit 31 includes a NAND circuit 32 and an inverter 33. The NAND circuit 32 receives the write activation signal φ
W and a test mode signal φTEST are input, and the output signal is output to each of the write amplifiers 22E to 22H as a write activation signal φW1 via an inverter 33. That is, the activation signal generation circuit 31 outputs the H level write activation signal φW1 to each of the write amplifiers 22E to 22H only when both the write activation signal φW and the test mode signal φTEST are at H level. The activation signal generation circuit 31 outputs an L level write activation signal φW1 to each of the write amplifiers 22E to 22H when either the write activation signal φW or the test mode signal φTEST is at the L level. Therefore, each light amplifier 2
2E to 22H are activated when H-level write activation signal φW1 is input, and their bus line pairs DB5 and / DB
The amplified data is output to DB5 to DB8 and the bar DB8.

Then, each bus line pair DB1, bar DB
As shown in FIG. 3, bit line pairs BL1, BL1 to BL8, and bar BL8 are connected to 1 to DB8 and to DB8, respectively. Each bit line pair BL1, bar BL
1 to BL8 and bar BL8 are gate transistors T1 and T
2 and one end via the sense amplifier 34
1, WL2 and so on.

In the DRAM configured as described above, as shown in FIG. 8, when the test mode signal φTEST changes from the L level to the H level, the DRAM enters the test mode. H
Selection circuit 2 according to the level test mode signal φTEST.
The NMOS transistors 24 of 3A to 23C turn on,
The input buffer 11A is connected to the write amplifiers 22B to 22D.

After the row address strobe signal RAS, the column address strobe signal CA
When the write control signal WE becomes L level after S becomes L level, the data latch signal φL of the latch signal generation circuit 17 switches from L level to H level. Due to the change of the data latch signal φL to the H level, the bit data DQ1 input at that time is latched as valid data in the input buffer 11A, and the bit data DQ1 is output to all the write amplifiers 22A to 22H.

On the other hand, when, for example, word line WL1 is selected based on the row address of the address signal and a column address is applied and column selection signals φCL1 and φCL2 attain an H level, gate transistors T1 and T2 are turned on and each of the gate transistors T1 and T2 is turned on. Bus line pair DB1, bar DB1 to DB8, bar DB
8, each bit line pair BL1, bars BL1 to BL8, bar B
L8 is connected.

Thereafter, when write activation signal φW goes high, write activation signal φW1 also goes high. Then, the H-level write activation signals φW, φW1
Amplifiers 22A-22D, 22E-22
H is activated and its bus line pair DB1, bars DB1 to DBD
The bit data DQ1 latched in the input buffer 11A is amplified and output to B8 and DB8.

As a result, the word line WL1 and each bit line B
Bit data DQ1 is written to each of the eight memory cells 35 connected to L1 to BL8.

[0016]

In the above-mentioned conventional DRAM, the number of memory cells 3 which is twice the number of input buffers in one cycle is increased.
5 can be written collectively. However, since only the same data can be collectively written into these memory cells 35, only a simple data pattern can be written into the memory cell array.

Therefore, when performing a test with a complicated data pattern, the test mode signal φTEST is held at the L level, the PMOS transistors 25 of the selection circuits 23A to 23C are turned on, and the write amplifiers 22B to 22D are turned on. The input buffers 11B to 11D are connected. After this,
Based on the change of the column address strobe signal / CAS to the L level and the change of the data latch signal φL to the H level due to the change of the write control signal / WE to the L level, it is then input to each of the input buffers 11A to 11D. The respective bit data DQ1 to DQ4 are latched as valid data, and the respective bit data DQ1 to DQ4 are output to the write amplifiers 22A to 22D.

When the write activation signal φW changes to the H level, the write amplifiers 22A to 22D are activated, and the bus line pairs DB1, / DB1 to DB4, / D
B4 amplifies and outputs the bit data DQ1 to DQ4 latched in the input buffers 11A to 11D, and stores the bit data DQ1 in the four memory cells 35 connected to the word line WL1 and the bit lines BL1 to BL4, respectively. ~
Write DQ4.

However, in this case, only the bit data DQ1 to DQ4 for the number of input buffers (four) can be written, and there is a problem that the test time is not shortened.

The present invention has been made in order to solve the above-mentioned problems, and a complicated data pattern can be collectively written in one cycle to memory cells twice as many as the number of input buffers. The purpose is to reduce the time.

[0021]

FIG. 1 is a diagram illustrating the principle of the present invention. According to a first aspect of the present invention, in the semiconductor memory device, an input data terminal and a common input data terminal are provided.
Connected first and second data latch circuits 3 and 4,
First and second data buses 7 for transmitting output data of the first and second data latch circuits 3 and 4, respectively ;
The first and second data buses 7 are connected to each other.
The first and second data latch circuits 3 and 4 receive test data Di1 and Di2 from the input data terminals at different timings in one test write cycle. Latch and said
The first and second write amplifiers 5, 6 are connected to the one test
In the write cycle, the test data Di1, Di
2 is to be written in the memory cell in parallel .

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, different timings are provided between the input data terminal and the first and second data latch circuits 3 and 4, respectively. The gist of the present invention is to further include first and second gates that are on / off controlled by a signal .

[0023]

The bit data Di1 and Di2 are latched at different timings in the test mode by the first and second latch circuits 3 and 4 of the input buffers 1 and 2, respectively, and the first and second latch circuits 3 and 3 are latched. 4 are output to the corresponding first and second write amplifiers 5 and 6, respectively. Then, in the test mode, the connection circuit 9 connects each bus line pair DB1 and bar DB.
1 to DB4 and bar DB4, each bit line pair BL1,
Bars BL1 to BL4 and bar BL4 are connected. Therefore, in one cycle, data is collectively written to twice as many memory cells as the number of input buffers, and the data to be written can be formed into a complicated data pattern composed of arbitrary bit data, thereby shortening the test time.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the present invention is embodied in a DRAM will be described below with reference to FIGS.

For convenience of description, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof is partially omitted. As shown in FIG. 2, the memory cell array 40 is composed of a large number of memory cells.
1, a column address decoder 42 and a sense buffer group 43 are connected, and an output buffer group 44 is connected to the sense buffer group 43. Also, the memory cell array 4
0 is a write amplifier group 4 in parallel with the sense buffer group 43.
5, and an input buffer group 46 is connected to the write amplifier group 45.

The row address buffer RA0~RAn-1 is connected to the row address decoder 41, b c address buffer RA0~RAn-1 external address signal AD to the row address decoder 41 consists of n bits from a control device (not shown) To be supplied.

The row control circuit 47 has a row address strobe signal / RAS as an address activation signal.
Row address buffers RA0-RA
Controls n-1.

Column address buffers CA0 to CAn-1 are connected to the column address decoder 42, and the column address buffers CA0 to CAn-1 apply an external address signal AD consisting of a plurality of bits input from the control device to the column address decoder 42. To be supplied.

The column control circuit 48 has a column address strobe signal / C as an address activation signal.
Column address buffer CA0 based on AS level
.. CAn-1 and the write amplifier group 45.

The output control circuit 49 controls the output buffer group 44 based on the level of the output control signal OE from the control device. Light control circuit 50
Controls the write amplifier group 45 based on the level of the write control signal WE from the control device.

FIG. 4 shows the details of the input buffer group 46 and the write amplifier group 45. The input buffer group 46 includes a plurality (four in the present embodiment) of input buffers 46A to 46 provided for the bit data DQ1 to DQ4 of the input data.
D. Each of the input buffers 46A to 46D includes first and second latch circuits 51 and 52.

The first latch circuit 51 includes an inverter 12,
A PMOS transistor 13, a latch 14 composed of two inverters, and inverters 15 and 16 are connected in series.
2, a PMOS transistor 53, a latch 54 composed of two inverters, and inverters 55 and 56 are connected in series.

The latch signal generation circuit 17 is connected to the gate terminal of the PMOS transistor 13 in each of the first latch circuits 51 of the input buffers 46A to 46D, and receives the data latch signal φLA. Therefore, both the column address strobe signal CAS and the write control signal WE become L level, and the H level data latch signal φLA is input from the latch signal generation circuit 17 to each of the first latch circuits 51 of the input buffers 46A to 46D. Then, the first latch circuits 51 of the input buffers 46A to 46D store the respective bit data DQ1 to DQ4 at that time.
Are latched as bit data DQ1A to DQ4A.

A latch signal generation circuit 57 is connected to the gate terminal of the PMOS transistor 53 in each of the second latch circuits 52 of the input buffers 46A to 46D, and receives the data latch signal φLB. The latch signal generation circuit 57 includes inverters 58 and 59 and a NAND circuit 60.
It is composed of Inverter 58 receives row address strobe signal RAS, inverts its level, and outputs the inverted signal. NAND circuit 60 receives the output of inverter 58 and test mode signal φTEST, and outputs the output signal as data latch signal φLB via inverter 59. That is, the latch signal generation circuit 57 outputs the data latch signal φLB at the H level to each second latch circuit 52 only when the row address strobe signal / RAS is at the L level and the test mode signal φTEST is at the H level. When the row address strobe signal / RAS is at H level or the test mode signal φTEST is at L level, the latch signal generation circuit 57 outputs an L level data latch signal φLB to each second latch circuit 52.

When the data latch signal φLB switches from the L level to the H level, each second latch circuit 52 latches the bit data DQ1 to DQ4 at that time as bit data DQ1B to DQ4B.

The write amplifier group 45 includes a plurality of (four in this embodiment) first write amplifiers 45A to 45D and a plurality of (four in this embodiment) second write amplifiers 45E.
To 45H. Each first write amplifier 4
5A to 45D are connected to the first latch circuits 51 of the input buffers 46A to 46D, respectively.
E to 45H are connected to the second latch circuits 52 of the input buffers 46A to 46D.

Each of the write amplifiers 45A to 45H has a pair of bus line pairs DB1, DB1 to DB8, and bar DB.
8 are connected. Each of the write amplifiers 45A to 45H is configured by connecting a series circuit of the inverters 26 and 27 and the NMOS transistor 29 and a series circuit of the inverter 28 and the NMOS transistor 30 in parallel. Bus line DB1 on the non-inverting side of each of write amplifiers 45A to 45H
To DB8 are connected to the respective NMOS transistors 29, and the inversion-side bus lines DB1 to DB8 are connected to the respective NMOS transistors 30.

Both NMOs of each write amplifier 45A to 45D
Write activation signal φW is input to the gate terminals of S transistors 29 and 30. Each light amplifier 45A ~
45D is activated when the H-level write activation signal φW is input, and the bit data DQ1A to 45D latched in the first latch circuits 51 of the input buffers 46A to 46D.
DQ4A is amplified and its bus line pair DB1, bar DB1
The amplified data is output to DB4 and DB4.

Further, both N of each of the write amplifiers 45E to 45H
The activation signal generation circuit 31 is connected to the gate terminals of the MOS transistors 29 and 30, and the write activation signal φ
W1 has been input. Each light amplifier 45E to 45H
Is the write activation signal φW and the test mode signal φTES
When both T become H level and the H level write activation signal φW1 is input from the activation signal generation circuit 31, the signal is activated. Then, each of the write amplifiers 45E to 45H amplifies the bit data DQ1B to DQ4B latched by each of the second latch circuits 52 of the input buffers 46A to 46D, and its bus line pair DB5, DB5 to DB8, and D
The amplified data is output to B8.

The bus line pairs DB1 and bar DB
As shown in FIG. 3, bit line pairs BL1, BL1 to BL8, and bar BL8 are connected to 1 to DB8 and to DB8, respectively. Each bit line pair BL1, bar BL
1 to BL8 and / BL8 are memory cells 3 whose one ends are connected to word lines WL1 and WL2 and the like via gate transistors T1 and T2 as connection circuits and a sense amplifier 34.
5 is connected.

Next, the operation of the DRAM configured as described above will be described with reference to FIG. First, the test mode signal φ
When TEST changes from L level to H level, the test mode is set. After test mode signal φTEST changes to H level, row address strobe signal RAS
Changes to L level, data latch signal φLB of latch signal generation circuit 57 switches from L level to H level.

When the data latch signal φLB changes to the H level, the bit data DQ1 to DQ4 input at that time are latched as valid data DQ1B to DQ4B in the second latch circuits 52 of the input buffers 46A to 46D. The data DQ1B to DQ4B are output to the write amplifiers 45E to 45H.

Subsequently, after the column address strobe signal / CAS goes low, the write control signal / W
When E becomes L level, the data latch signal φLA of the latch signal generation circuit 17 switches from L level to H level.

When the data latch signal φLA changes to the H level, the first latch circuits 51 of the input buffers 46A to 46D latch the bit data DQ1 to DQ4 input at that time as valid data DQ1A to DQ4A. The data DQ1A to DQ4A are output to the write amplifiers 45A to 45D.

On the other hand, after, for example, the word line WL1 is selected based on the row address of the address signal, when a column address is applied and the column selection signals φCL1 and φCL2 go to the H level, the gate transistors T1 and T2 are turned on. Each bit line pair BL1, bar BL1 to BL8, bar BL8 is connected to each bus line pair DB1, bar DB1 to DB8, bar DB8.

Thereafter, when write activation signal φW attains an H level, write activation signal φW1 also changes to an H level. Then, the write amplifiers 45A to 45D are activated based on the H-level write activation signal φW, and the data DQ1A to DQ4 latched by the first latch circuits 51 are activated.
A is amplified and its bus line pair DB1 and bars DB1-D
The amplified data is output to B4 and bar DB4.
The write amplifiers 45E to 45H are activated based on the H-level write activation signal φW1, and the data DQ1B to DQ4B latched by each second latch circuit 52 are amplified, and the bus line pair DB5, DB5 to DB8,
The amplified data is output to the bar DB8.

As a result, the word line WL1 and each bit line B
Bit data DQ1A to DQ4A, DQ1B to DQ are stored in eight memory cells 35 connected to L1 to BL8, respectively.
Q4B is written.

As described above, in the present embodiment, each of the input buffers 46A to 46D controls the bit data DQ1 to DQ input at that time at different timings in the test mode.
And first latch circuits 51 and 52 for latching the first and second write amplifiers 45A to 45D corresponding to the first latch circuits 51, respectively. Each of the second write amplifiers 45E to 45H is provided corresponding to the circuit 52. Then, in the test mode, each bus line pair DB is operated by the gate transistors T1 and T2.
The bit line pairs BL1, BL1 to BL8, and bar BL8 are connected to 1, bars DB1 to DB8, and bar DB8. Therefore, in one cycle, data can be written to eight memory cells twice as large as the four input buffers 46A to 46D, and the data to be written can be a complicated data pattern composed of arbitrary bit data. . Therefore, even in the case of a complicated data pattern, data can be collectively written to twice as many memory cells as the number of input buffers in one cycle, and the test time can be reduced.

In this embodiment, when the row address strobe signal / RAS changes to the L level in the test mode, the bit data DQ1 to DQ4 at that time are stored in the second latch circuits 52 of the input buffers 46A to 46D.
Are latched as valid data DQ1B to DQ4B, and when the write control signal / WE changes to the L level, the first latch circuits 51 of the input buffers 46A to 46D store the respective bit data DQ1 to DQ4 at that time as valid data DQ1A. ~ DQ4A to latch
In the cycle, a data pattern composed of arbitrary bit data is collectively written to eight memory cells twice as large as the four input buffers 46A to 46D, but the present invention is not limited to this. It may be implemented as shown. That is, after the test mode signal φTEST changes to the H level to enter the test mode, the column address strobe signal / CAS and the write control signal / WE
Becomes L level, the bit data DQ1 to DQ4 input at that time are input to the input buffers 46A to 46D.
Are latched as valid data in each of the first latch circuits 51, and the latched data is written into each of the write amplifiers 45A to 45A.
Output to 5D.

On the other hand, each latched bit data DQ1-
A data pattern consisting of 4 bits for each combination of DQ4 is stored in a storage device (not shown). Then, the data patterns corresponding to the respective combinations of the bit data DQ1 to DQ4 latched by the respective first latch circuits 51 are read from the storage device, and the read data patterns are read into the respective second latches of the input buffers 46A to 46D. The data is latched by the circuit 52 as valid data and output to the write amplifiers 45E to 45H.

By simultaneously activating each of the write amplifiers 45A to 45H, a data pattern consisting of arbitrary bit data can be transferred to eight memory cells twice as large as the four input buffers 46A to 46D in one cycle. You may write in a lump.

[0052]

As described above in detail, according to the present invention, a complicated data pattern can be collectively written to memory cells twice as many as the number of input buffers in one cycle.
There is an excellent effect that the test time can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a dynamic RAM according to one embodiment;

FIG. 3 is an electric circuit diagram showing a memory cell array in one embodiment.

FIG. 4 is a circuit diagram showing an input buffer and a write amplifier according to one embodiment.

FIG. 5 is a timing chart showing the operation of one embodiment.

FIG. 6 is a timing chart showing the operation of another embodiment.

FIG. 7 is a circuit diagram showing a conventional input buffer and write amplifier.

FIG. 8 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 1, 2 input buffer 3 1st latch circuit 4 2nd latch circuit 5 1st write amplifier 6 2nd write amplifier 7 data bus 8 memory cell array 9 connection circuit BL1, bar BL1-BL4, bar BL4 bit line pair DB1, bar DB1 to DB4, bar DB4 bus line pair Di1, Di2 bit data

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-30199 (JP, A) JP-A-4-324200 (JP, A) JP-A-61-204900 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/40-11/419

Claims (2)

(57) [Claims] An input data terminal, first and second data latch circuits commonly connected to the input data terminal, and a first for transmitting output data of the first and second data latch circuits, respectively. And a second data bus, and a first data bus connected to the first and second data buses, respectively.
And a 1 and a second write amplifier, said first and second data latch circuit 1 at different timings in the test write cycle, latches the test data from the input data terminal, said first and second The light amplifier of the one test writing
The test data in parallel in the
A semiconductor memory device for writing data in a cell . 2. The semiconductor device according to claim 1, further comprising first and second gates provided between the input data terminal and the first and second data latch circuits, the first and second gates being on / off controlled by different timing signals. 2. The semiconductor memory device according to claim 1, wherein: