JPH073757B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device having a high speed and highly reliable test mode.

[Conventional technology]

In recent years, the use of dynamic RAM has expanded, and it has come to be used in large quantities in the field of image processing, so that what is called a dual port RAM for image processing has appeared. This RAM has a RAM section and a serial access memory (hereinafter referred to as SAM) section inside, and the RAM section and the SAM section can operate asynchronously. If you use this dual port RAM, the CPU will
Since the SAM unit can input image data while accessing the unit, the CPU utilization efficiency can be improved. Further, the RAM section and the SAM section can transfer data mutually.

Figure 2 shows the 1986 IE Conference International Conference on Consumer Electronics Digest of Technical Paper (IE
EE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONIC
S DIGEST OF TECHNICAL PARERS) This shows the RAM / SAM port section of the conventional dual port RAM described on page 159. In the figure, 2a and 2b are word lines, 3a and 3b are memory cells, 4a and 4b are bit lines of mutually opposite phase signals, 5a and 5b are data buses, 6a and 6b are data gate lines, 7 is a data register, 8 Is a serial selector, 9a and 9b are serial buses, 10
Is a column decoder, Q ₁ and Q ₂ are data gates, Q ₃ and Q ₄ are data transfer transistors, Q ₅ and Q ₆ are serial gate transistors, and Q ₇ is an address transfer transistor.

Next, the operation will be described. First, when data is transferred from the RAM port to the SAM port, the data amplified by the sense amplifier 1 is amplified on the bit lines 4a and 4b. Then, the transistors Q ₃ and Q ₄ are turned on, and the data is latched in the data register 7. When latched data is the transistor Q ₅ 8 serial selector is selected, Q ₆ are turned on data is read serial bus 9a, to 9b. RAM
Bit line 4a when the operation of only the port portion, data 4b are the column decoder 10 is the select transistors Q _1, Q ₂
Is turned on, and the data is read onto the data buses 5a and 5b. Serial bus 9a for transfer from the SAM port to the RAM port and 9b data is written in the data register 7 is then turned on the transistor Q _3, Q ₄ is, bit lines 4a, data 4b is transferred, further sense It is amplified by the amplifier 1 and written in the memory cell.

[Problems to be solved by the invention]

Since the conventional dual-port RAM is configured as above, at the test stage, only the RAM port test, R
It is necessary to perform a transfer test from AM to SAM and a transfer test from SAM to RAM, and the test method is complicated and takes a long time.

The present invention has been made to solve the above problems, and by adding a few circuits, RAM port SAM
Recognize the transfer result of the port, so that you can test all RAM / SAM ports lined up in the column direction at once,
The purpose is to obtain a dual-port RAM with a high-speed and highly reliable test mode function.

[Means for solving problems]

The dual-port RAM according to the present invention is provided with a coincidence detection circuit for performing coincidence detection in addition to connecting the sense amplifier output of the RAM port and the data register of the SAM port with a data transfer gate, and further in a row. The configuration is such that the coincidence detection sense lines are connected commonly to the aligned columns.

[Work]

The dual port RAM according to the present invention is provided with a coincidence detection circuit in the RAM / SAM port section so that the data read by the same word line of the RAM section and amplified by the sense amplifier and the data latched in the data register of the SAM section. By detecting the match with, it is possible to test the same line at a time, and it is also possible to check the RAMSAM transfer function.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, reference numeral 12 is a coincidence detection circuit for detecting coincidence of data in the RAM port section and the SAM port section. Reference numeral 13 is a sense line for outputting coincidence detection result data, and 14 is a signal line for coincidence detection circuit reset. Here, the transistors Q ₈ , Q ₉ , Q
₁₀ is a 4-channel transistor, and the others are N-channel transistors. Other parts are the same as in the conventional example of FIG.

Next, the operation will be described. First, it is assumed that the nodes N ₂ and N ₄ are precharged to “H” before the data of the RAM port is read. Also Purichiyaji a signal line 14 to the node N ₁ turns on the transistor Q ₁₁ in the "H" to "H". Then, the signal line 13 is precharged to "H". At this time, the transistor Q ₁₀ is off because the node N ₁ is “H”. After that, the signal line 14 is set to the “L” level. Both transistors Q ₈ and Q ₉ are off.

When the sense amplifier 1 is activated and the data of the RAM port is amplified, the RAM data of the nodes N ₂ and N ₄ and the SAM of the nodes N ₃ and N ₅
Matches the data. For example, when the nodes N ₂ and N ₃ are both “H” and the nodes N ₄ and N ₅ are both “L”, the transistor Q ₈ is turned on, and the node N ₁ remains “H”. The level of the sense line 13 also remains "H". Similarly, when the nodes N ₂ and N ₃ are both “L” and the nodes N ₄ and N ₅ are both “H”, the transistor Q ₉ is turned on and the node N ₁ remains “H”.

However, if the nodes N ₂ and N ₅ are “H” and N ₃ and N ₄ are “L”, the transistor Q ₈ is turned on and the node N ₁ is “L”. "H" level is discharged through the transistor Q _10. Conversely, node N ₂ ,
Even when N ₅ is “L” and the nodes N ₃ and N ₄ are “H”, the same discharge occurs. In this way, the level of the sense line 13 is discharged when even one of the many coincidence detection groups does not coincide.

The coincidence detection is performed as described above. The coincidence detection circuits 12 are arranged in a line like the data register 7, and the sense lines 13 and the signal lines 14 are commonly connected to all the coincidence detection circuits. By doing so, it is possible to detect the coincidence between the data of all the RAM port parts of the same row when one word line is selected and the data register of the corresponding SAM port part 1: 1 at a time. it can.
This makes it possible to easily check the transfer function of RAMSAM. Also, in the test of the RAM unit alone, the same row can be tested at once by storing the test data in the data register 7.

Although the dual port RAM has been described in the above embodiments, the coincidence detection circuit and the data register may be provided only for the test function with a simple RAM.

〔The invention's effect〕

As described above, according to the present invention, all the RAM / SAM ports arranged in a line in the column direction can be tested at one time, so various tests can be performed easily and in a short time. Have.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 7 ... Data register, 12 ... Match detection circuit, 13 ... Match detection output.

Claims (1)

[Claims] 1. A semiconductor having a sense amplifier connected to a bit line for reading and writing data from a memory cell, a gate for bidirectionally transferring the data of the sense amplifier, and a data register separated from the sense amplifier by the gate. A semiconductor memory device, comprising: a match detection circuit for detecting a match between an output of a data register and an output of a sense amplifier.