JP2905394B2 - Test method for dual port RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a dual-port RAM having two ports for independently accessing each memory area.

[0002]

2. Description of the Related Art In recent years, techniques for processing data at high speed have been developed.
With increasing emphasis, dual-port RAMs have been proposed as part of this technology. For example, when performing graphic processing with a personal computer, in a single-port RAM conventionally used, a write operation and a read operation of a large number of data for screen display are performed separately.

On the other hand, a dual port RAM is provided with two ports, and a large amount of data is written from one port for screen display and a large number of data is read from the other port. Time is saved and high-speed display is realized. FIG. 4 is a circuit diagram showing one memory cell of the dual port RAM.

The memory cell 30 is provided with two inverters 32 and 33 whose inputs and outputs are connected to each other. The memory cell 30 includes a bit line ABIT0 and a bit bar line ABIT0N of the A port, and a bit line BBIT0 and a bit bar line BBI of the B port.
T0N extends, and a connection point between the input of the inverter 32 and the output of the inverter 33 and each bit line ABIT0, BBIT
Pass transistors 34 and 35 are arranged between BIT0 and BIT0. A connection point between the input of the inverter 33 and the output of the inverter 32 is connected to each bit bar line ABIT0N and BBIT0.
The pass transistors 36 and 37 are arranged between the pass transistors 0N and 0N. The memory cell 30 has a word line AWORD0 of the A port and a word line BWORD of the B port.
0 extends, the gates of the pass transistors 34 and 36 are connected to the word line AWORD0, and the gates of the pass transistors 35 and 37 are connected to the word line BWORD0.

When writing data to the memory cell 30 configured as described above from the A port, the word line A of the A port is used.
WORD0 rises to logic '1' and bit line ABIT
0 and bit bar lines ABIT0N are logical
By setting them to 1 ',' 0 'or logic' 0 ',' 1 ', respectively, logic' 1 'or logic' 0 'is written in this memory cell 30. Also, this memory cell 30
When reading out the stored contents from the A port, the word line AWORD0 of the A port is raised to logic "1", and the contents of the memory cell 30 appearing on the bit line ABIT0 and the bit bar line ABIT0N are detected by a sense amplifier (not shown). Is done. The same applies to the B port.

Here, only one memory cell 30 is shown, but a plurality of such memory cells 30 are arranged to form one memory area with one address, and the memory thus configured A plurality of areas are further arranged in the row direction and the column direction, and a plurality of memory areas arranged in the same column direction have a common A-port bit line ABIT0, bit bar line ABIT0N, B-port bit line BBIT0, bit bar line BBIT0N. Extending.

[0007]

As described above, a dual-port RAM has two ports.
Each memory area is accessed independently from each of these two ports. The bit line of one port and the bit line of the other port are arranged in parallel with each other along each memory region, and a short circuit between these bit lines is sufficiently considered in a manufacturing process. For this reason, it is necessary to test whether or not these bit lines are short-circuited after manufacturing. However, a conventional test such as marching of a single-port RAM is applied to a dual-port RAM, and each of the two ports is individually tested. Even if the memory area is tested for defects, the presence or absence of a short circuit between the bit lines is not detected, and a test for the presence or absence of a short circuit between the bit lines must be added in addition to the test for the presence or absence of a memory area defect.
It took a long time to test.

In view of the above circumstances, the present invention performs a test for the presence or absence of a short circuit between the bit line of the first port (A port) and the bit line of the second port (B port) in a memory area such as so-called marching. It is an object of the present invention to provide a dual port RAM test method that can be performed simultaneously with a test for the presence or absence of a defect.

[0009]

According to the present invention, there is provided a method of testing a dual-port RAM, comprising one or a plurality of memory cells, each of which is two-dimensionally arranged in a row direction and a column direction. A plurality of memory areas, and a first memory area for accessing the plurality of memory areas independently of each other.
A dual port RAM including a first port and a second port, the first port and the second port having a second port and a second port. A first step of initializing each of the memory areas of the plurality of memory areas from one and the other of the first and second ports, respectively. Simultaneously writing data other than the predetermined data into the area and reading from the second memory area arranged in a different row and different column from the row and column in which the first memory area is arranged. 2 steps (3) The first port from the one or the other port
A third step of reading data stored in a third memory area arranged at an intersection of a column in which the memory area is arranged and a row in which the second memory area is arranged; The second step and the third step are alternately repeated while sequentially changing the first memory area. Based on the data read in the third step, the bit line of the first port and the second It is determined whether or not the bit line of the port is short-circuited.

[0010]

According to the present invention, in the above-described test method, in the second step, for example, data is written to a certain memory area from the first port, and at the same time, another row and column memory is written from the second port. The data in the area is read, whereby the word line of the second port in another row is raised to logic "1". Therefore, when the bit line of the first port and the bit line of the second port are short-circuited, the data is read from the same column as the memory area where data is written from the first port and from the second port. Will be written from the first port to the memory area located at the intersection of the same row as the memory area from which is read.

Therefore, in the third step,
By reading data from the memory area located at this intersection, a short circuit between the bit line of the first port and the bit line of the second port can be easily detected based on the read data. Since the test method of the dual port RAM of the present invention is such a method, it can be easily incorporated in a conventionally performed marching test, for example.
Therefore, at the same time as the test for the presence / absence of a defect in the memory area, the test for the presence / absence of a short circuit between bit lines can be performed.
The test time is short-circuited without setting a new test item.

[0012]

Embodiments of the present invention will be described below. FIG. 1 is a conceptual diagram of a test circuit to which a test method of a dual port RAM according to one embodiment of the present invention is applied. In this embodiment, the test circuit and the dual port RAM are used.
Are mounted in one LSI.

The dual port RAM 11 shown in FIG. 1 has an A port and a B port. Multiplexers 13a,..., 13e are arranged at the input on the A port side of the dual port RAM 11. On the other hand, B
An inverter 12 and multiplexers 14a,..., 14e are arranged at the port side input. A signal for testing the dual port RAM 11 is input to one input terminal "1" of each of the multiplexers 13a,..., 13e, 14a,.

Further, the multiplexers 13a,.
e, 14a,..., 14e have the other input terminal “0”
A signal for the user to use the dual port RAM 11 is input. Here, the multiplexers 13a,.
13e, 14a,..., 14e control signals ME
When an “H” level signal is input as MTEST,
Multiplexers 13a, ..., 13e, 14a, ..., 14
The signal input to the input terminal “1” of e is input to the A port and the B port of the dual port RAM 11. On the other hand, multiplexers 13a, ..., 13e, 14a, ...,
When an “L” level signal is input to the control terminal of the multiplexer 14e, the multiplexers 13a,..., 13e, 14a,.
The signal input to the input terminal “0” of 14 e is input to the A port and the B port of the dual port RAM 11.
FIG. 1 shows only one-bit multiplexers 13a to 13e, 14a to 14e, 15a, and 15b and one-bit inverter 12 for each signal.
Actually, these multiplexers 13a to 13e, 1
4a to 14e, 15a, 15b and the inverter 12 are provided for the bit width of each signal.

The multiplexers 15a and 15a are connected to the output sides of the A port and the B port of the dual port RAM 11, respectively.
5b are arranged, and the output data ADAT of the A port
Output data BDATO of the O or B port is output to the output pad. Here, when testing the dual port RAM 11, first, the multiplexer 13a,
, 13e, 14a,..., 14e, and 15b are input with an "H" level signal. Then, the address signal ADRT is input to the address terminal AADR of the A port via the multiplexer 13a. At the same time, the address signal ADRT is inverted by the inverter 12, and is also input to the address terminal BADR of the B port via the multiplexer 14a. Therefore, the address of the memory area accessed from the port A and the address of the memory area accessed from the port B are addresses whose logics are inverted from each other.

A data signal DATIT is commonly input to the data terminal ADATA of the A port and the data terminal BDATI of the B port via the multiplexers 13b and 14b. Therefore, the same data is written in the memory area accessed from the A port and the memory area accessed from the B port. Further, the external clock signal CKNT is also commonly input to the clock terminal ACKN of the A port and the clock terminal BCKN of the B port via the multiplexers 13c and 14c.

Also, chip select signals ACSP and BCST for selecting the A port and the B port are input to the chip select terminal ACS of the A port and the chip select terminal BCS of the B port via the multiplexers 13d and 14d, respectively. Is done. Similarly, a read / write signal ARWN for reading / writing port A and port B
T and BRWNT are also read / write terminal ARW of port A via multiplexers 13e and 14e, respectively.
It is input to the read / write terminal BRWN of the N and B ports.

The description will be continued with reference to FIGS. 2 and 3 together with FIG. FIG. 2 is a flowchart showing steps of a method for testing a dual port RAM according to one embodiment of the present invention. FIG. 3 is a circuit diagram showing four memory cells of the dual port RAM 11 shown in FIG. Here, the memory cells 30, 40, 50,
Reference numeral 60 has the same configuration as the memory cell 30 shown in FIG.

Here, for example, the bit line ABIT0 of the A port and the bit line BBI of the B port shown on the left side of FIG.
It is assumed that T0 is short-circuited. In addition, memory cell 3
It is assumed that the addresses where 0, 40, 50, and 60 are specified are '00', '01', '10', and '11', respectively. According to the flow shown in FIG.
When the test 1 is started, first, in an initialization step 21, the four memory cells 30, 40, 50, and 60 are
Logic '0' is written as initialization data.

Next, in the write / read step 22, "00" is designated as the address signal ADRT, and logic "1" is written from the A port to the memory cell 30. At the same time, the contents of the memory cell are read from the B port. Here, the address of the memory cell designated from the B port is the address '11' inverted by the inverter 12, and therefore, the memory cell 60 is designated. To read the contents of the memory cell 60, the word line BWORD1 of the B port is used.
Is raised to logic one. Then, when the bit line ABIT0 on the A port side and the bit line BBIT0 on the B port are short-circuited, the column of the memory cells 30 and the memory cells 60
Logic “1” is applied to the memory cell 50 arranged at the intersection with the row
Is written. Thus, the memory cell 6
The reading of the content of 0 is a dummy read, so to speak, and the purpose is to raise the word line BWORD1 to logic '1'.

Next, in a read / determination step 23, the data stored in the memory cell 50 is read. In this case, the data may be read from the A port or the B port. Here, it is assumed that data is read from the A port. Then, the logical A 'is output from the output terminal ADAT0 of the A port of the dual port RAM11.
1 'is output and the input terminal' of the multiplexer 15a is output.
Input to 0 '. Here, since the control terminal of the multiplexer 15a receives the "L" level signal SELAB for selecting the output signal ADATO of the port A, this logical "1" signal is input to the input terminal "1" of the multiplexer 15b. Is input to The logic "1" signal input to the input terminal "1" of the multiplexer 15b is supplied to the control terminal of the multiplexer 15b by the "H" level signal MEM.
Since TEST is input, the multiplexer 15b
Selects the signal of logic "1" and outputs it from the output pad. The logic of the signal output from the output pad is determined, and since the logic is "1", the bit line ABIT0 of the A port and the bit line BBI of the B port are determined.
A short circuit with T0 is found. To subsequently test whether there is a short circuit between the other bit line of the A port and the other bit line of the B port, the address signal ADRT is changed, and the write / read step 22 and the read / judgment step 23 are executed. .

In this manner, while sequentially changing the address signal ADRT, the write / read step 22 is performed.
And the read / determination step 23 are alternately and repeatedly performed.

[0023]

As described above, the method for testing a dual port RAM of the present invention performs writing to the first memory area and reading to the second memory area simultaneously,
Because of the method of reading the third memory area, it is easy to determine whether there is a short circuit between the bit line of the first port and the bit line of the second port. Therefore, the dual port R of the present invention
The AM test method includes a new test for short-circuiting between the bit line of the first port and the bit line of the second port of the dual port RAM in order to easily incorporate the conventional testing of a marching pattern, for example. Test time is also reduced without adding

Further, since a test circuit for applying the test method of the present invention can be a small and simple circuit as shown in FIG. 1, when a dual-port RAM is mounted in an ASIC, The test circuit can be easily incorporated in the device.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a test circuit to which a test method for a dual port RAM according to an embodiment of the present invention is applied.

FIG. 2 is a flowchart illustrating steps of a method for testing a dual port RAM according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing four memory cells of the dual port RAM shown in FIG.

FIG. 4 is a circuit diagram showing one memory cell of a dual port RAM.

[Explanation of symbols]

Reference Signs List 11 dual port RAM 12, 32, 33 inverter 13a, 13b, 13c, 13d, 13e multiplexer 14a, 14b, 14c, 14d, 14e multiplexer 15a, 15b multiplexer 21 initialization step 22 write / read step 23 read / judgment step 30, 40, 50, 60 memory cells 34, 35, 36, 37 pass transistors ABIT0, ABIT0N, ABIT1, ABIT1N
A port bit lines BBIT0, BBIT0N, BBIT1, BBIT1N
B port bit line AWORD0, AWORD1 A port word line BWORD0, BWORD B port word line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G11C 29/00 G01R 31/28 G11C 11/41 G11C 11/413 G11C 11/401

Claims (1)

(57) [Claims] 1. A plurality of memory areas each having one or a plurality of memory cells, each of which is two-dimensionally arranged in a row direction and a column direction, and a plurality of memory areas which independently access the plurality of memory areas. A method of testing a dual port RAM, comprising: testing a short circuit between a bit line of a first port and a bit line of a second port of a dual port RAM having first and second ports; A first step of initializing each of the areas with predetermined data; and a step of, from one and the other of the first and second ports, respectively, a first memory area of the plurality of memory areas. Writing of data other than the predetermined data, and second memory arranged in a different row and different column from the row and column in which the first memory area is arranged. A second step of simultaneously reading data from the memory area; and arranging, from the one or the other port, an intersection between a column in which the first memory area is arranged and a row in which the second memory area is arranged. A third step of reading out data stored in the third memory area, wherein the second step and the third step are alternately repeated while sequentially changing the first memory area.
Determining whether the bit line of the first port and the bit line of the second port are short-circuited based on the data read in the step (b). .