CN100364015C - Testing method of multiport storage - Google Patents
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- CN100364015C CN100364015C CNB2003101153542A CN200310115354A CN100364015C CN 100364015 C CN100364015 C CN 100364015C CN B2003101153542 A CNB2003101153542 A CN B2003101153542A CN 200310115354 A CN200310115354 A CN 200310115354A CN 100364015 C CN100364015 C CN 100364015C
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Abstract
The present invention relates to a testing method of a multiport memory, which comprises the following steps: (1) firstly, peripheral interconnection lines at all ports are tested in sequence; if faults exist in the peripheral interconnection lines, the faults are diagnosed; if faults do not exist in the peripheral interconnection lines, the following steps are carried out; (2) the memory array of the multiport memory is tested by one port of the multiport memory; if faults exist in the internal storage unit of the memory, an address generating the faults is reported; if the faults are not discovered, the following steps are carried out; (3) the address decoders and input/output controllers of the rest of the ports are tested in sequence; if faults exist in the address decoders and input/output controllers, the faults are diagnosed; if faults are not discovered, the test is over. The testing method of the present invention completely tests usual faults of data wires, address wires, control wires, arbitrators, the address decoders and the input/output controllers, and accurately positions the faults.
Description
Technical field
The present invention relates to the measuring technology of the electronics or the communications field, specifically refer to a kind of method of testing of multiport memory.
Background technology
Multiport memory has a plurality of independently access ports, and each port has independently control, address, data pin, allows from each end unit arbitrarily the read-write memory independently.And common be the dual-ported memory (being also referred to as mailbox) that possesses two ports, as shown in Figure 1.Dual-ported memory (mailbox) is generally by forming with the lower part: address decoder, the i/o controller of storage array, flag moderator and both sides, carry out the BUSY signal wire and the INT signal wire of bus arbitration in addition.
The fault of control line mainly comprises fixed logic fault, stuck-open fault and bridge joint short trouble.Because it is less that control line compares, and the fault of control line is very obvious.The fault of control line just can be found when data line and address wire are carried out basic test, so can generally separately control line not tested.
The fault of data line, address wire and control line also all is the fault of peripheral interconnection line, generally all is to set up stuck-at fault model.So the fault of data line and address wire mainly also is fixed logic fault, stuck-open fault and bridge joint short trouble (Short fault).The bridge joint short trouble comprises two kinds of 0-dominance short trouble and 1-dominance short troubles again.
The reason that the moderator fault produces may be varied, but unification shows as and can't correctly control the read-write operation authority.The moderator fault also is very tangible, and can detect the fault in the moderator in the content measurement afterwards, so generally also can not do special test to the fault of moderator.
The fault of storage array mainly is summed up as six class faults: fixed logic fault, stuck-open fault, state exchange fault, data keep fault, state coupling fault and multiple Write fault.
The fault of address decoder mainly shows as not to be chosen arbitrary storage unit or chooses selected cell to choose other unit simultaneously.Fault in the code translator can equivalence be the fault in the memory cell array.
The fault of i/o controller mainly contains: one or more fixed logic faults in input, the output lead; One or more stuck-open faults in impact damper or the latch; State coupling fault in impact damper or the latch between any two.The fault of read-write in the logical circuit also can equivalence be the fault in the memory cell array.
Because to the complete test of the storage display fault of cover data line, address wire, control line and moderator fully; And the fault of address decoder, i/o controller is equal to the fault of memory array again, so the method that the method for test multiport memory is just tested multi-port memory array.
And main multiport memory is exactly mailbox, can promote the use of very naturally in the test of multiport memory for the method for testing of mailbox.
Now general method of testing and process are as follows:
1) initialization mailbox;
2) the mailbox left-sided system obtains flag, and wide each the unit identical data of mailbox that writes successively of word on request discharges flag;
3) the mailbox right-sided system obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number with the data negate, writes mailbox then, discharges flag;
4) the mailbox left-sided system obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number discharges flag.
Last mistake of statistics number if wrong number is 0, then shows and does not find fault, if wrong number is not 0, then there is fault in report.
Method of testing and process for multiport memory also are similar (are the example explanation with the K port store):
1) initialization K port store;
2) the 1st port one side system of K port store obtains flag, and wide each the unit identical data of mailbox that writes successively of word on request discharges flag;
3) the 2nd port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number with the data negate, writes mailbox then, discharges flag;
……
K+1) K port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number with the data negate, writes mailbox then, discharges flag;
K+2) the 1st port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number discharges flag.
Last mistake of statistics number if wrong number is 0, then shows and does not find fault, if wrong number is not 0, then there is fault in report.
The shortcoming of prior art: this test is fairly simple, can detect partial fixing logic fault, partial fixing open fault, partial data maintenance fault.Can only cover seldom state exchange fault, state coupling fault and multiple Write fault.This method of testing test is very incomplete, and can not be to diagnosing malfunction and location.
Summary of the invention
The present invention proposes a kind of method of testing of multiport memory, to solve the problem that method of testing in the prior art can not complete test when the test multiport memory and can not be diagnosed and locate.
For addressing the above problem, the invention provides following technical scheme:
A kind of method of testing of multiport memory comprises the following steps:
(1), at first successively test the peripheral interconnection line of each port,, then carry out fault diagnosis if peripheral interconnection line has fault; If peripheral interconnection line is not found fault, then carry out the following step;
(2), the storage array of multiport memory is tested by a port of multiport memory, if there is fault in the memory inside storage unit, the report address of breaking down then; If do not find fault, then carry out the following step;
(3), successively the address decoder and the i/o controller of remaining port are tested, if address decoder and i/o controller have fault, then carry out fault diagnosis; If do not find fault, then end of test (EOT).
Wherein, the test of described peripheral interconnection line comprises the following steps:
(11) in two different addresses, with the stuck-open fault and the fixed logic fault of one group of complete " 1 " data and one group of complete " 0 " Data Detection data line;
(12) fix an address, test data adopts " walking 1 matrix " and " walking 0 matrix " respectively, detects the short trouble of data line;
(13) test address and test data are " walking 1 matrix ", and increase by one group of complete " 0 " address and complete " 0 " data, test one time; Test address and test data are " walking 0 matrix ", and increase by one group of complete " 1 " address and complete " 1 " data, test one time again, detect address wire stuck-open fault, fixed logic fault and bridge joint short trouble.
Described step is tested the storage array of multiport memory in (2), is to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, and specifically comprises the steps:
(21) the address ascending order is write " 01...0101 ";
(22) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(23) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(24) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(25) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately.
Above-mentioned read-write process also can be to carry out according to the address descending; Simultaneously, the order that writes data also can be to write " 10...1010 " earlier, after write " 01...0101 ".
Address decoder and i/o controller to remaining port in the described step (3) are tested, and specifically comprise:
(31) if data line more than or equal to address wire, then all address spaces are tested as a monoblock;
(32) if data line is less than address wire, then the address space piecemeal to be tested according to the number of data line, the size of each piece is exactly the maximum data that data line can be represented.
In the said method, within each address block, each data corresponding address is unique, and the data of each address correspondence also are unique simultaneously.
Describedly address space is divided into a plurality of address blocks tests, comprising: write data 0 in first address 0, address 1 writes data 1 ..., until last address of first writes maximum data; In the data that second block address writes is to write on the basis of data in first block address to roll once, promptly write successively data 1,2 ..., maximum data, 0; In the data that the 3rd block address writes is to write on the basis of data in second block address to roll once ..., the rest may be inferred, write all address blocks after, read successively from low to high or from high to low by the address and to compare.
Described address space is tested as a monoblock, comprise: with number of addresses as writing a data high position, one or more high positions according to the figure place of data line intercepting number of addresses append to the low level that writes data again, with the said write data be written to the corresponding address location of described number of addresses in, read verification then.
This method of testing of the present invention can detect fixed logic fault, stuck-open fault, state exchange fault, six class most common failures such as data maintenance fault, state coupling fault and multiple Write fault fully, and has covered the fault of data line, address wire, control line, moderator, address decoder and i/o controller fully.This method of testing test is very complete, and localization of fault is accurate.
Description of drawings
Fig. 1 is the general structural drawing of dual-ported memory.
The process flow diagram that Fig. 2 A, Fig. 2 B detect memory array for the present invention.
Embodiment
The invention provides a kind of method that multiport memory is carried out complete test, at first discuss the method for testing of dual-ported memory, be generalized to then in the multiport memory test.
The method of testing and the step of dual-ported memory are as follows:
(1) tests the peripheral interconnection line (comprising data line, address wire, control line) at two ends at first successively, the read-write control is obtained in the left side, use " three-step approach " test left side peripheral interconnection line, the left side discharges the read-write control, the read-write control is obtained on the right side, uses " three-step approach " test right side peripheral interconnection line.
So-called " three-step approach " is a kind of method of testing at peripheral interconnection line that the present invention proposes, and this method of testing is fault location accurately, and it is dissimilar to distinguish two kinds of bridge joint short trouble.The method of testing of " three-step approach " and step such as following table:
| Testing procedure | Operation | The address | Data | Note |
| The first step | Write | A | 0...000 | A, B compare verification when being any two different address read, and test data is one group complete " 0 " and one group complete " 1 ". |
| Write | B | 1...111 | ||
| Read | A | 0...000 | ||
| Read | B | 1...111 | ||
| The second step a | Write | A | 0...001 | A is any fixed address, compares verification when reading.Test data is " walking 1 matrix " (the diagonal of a matrix data is 1, and the data of all the other positions are 0, and so similar 1 walking forward or backward is name walking 1 matrix). |
| Read | A | 0...001 | ||
| Write | A | 0...010 | ||
| Read | A | 0...010 | ||
| Write | A | 1...000 | ||
| Read | A | 1...000 | ||
| The second step b | Write | A | 1...110 | A is any fixed address, compares verification when reading.Test data is " walking 0 matrix " (the diagonal of a matrix data is 0, and the data of all the other positions are 1, and so similar 0 walking forward or backward is name walking 0 matrix). |
| Read | A | 1...110 | ||
| Write | A | 1...101 | ||
| Read | A | 1...101 | ||
| Write | A | 0...111 | ||
| Read | A | 0...111 | ||
| The 3rd step a | Write | 0...001 | 0...001 | Test address and test data are " walking 1 matrix ", increase by one group of complete " 0 " address and complete " 0 " data at last again.Compare verification when reading,, carry out fault diagnosis earlier, positioning and fixing logical zero fault and 1-dominance short trouble if finish to find fault at the 3rd step a. |
| Write | 0...010 | 0...010 | ||
| Write | 1...000 | 1...000 | ||
| Write | 0...000 | 0...000 | ||
| Read | 0...001 | 0...001 | ||
| Read | 0...010 | 0...010 |
| Read | 1...000 | 1...000 | ||
| Read | 0...000 | 0...000 | ||
| The 3rd step b | Write | 1...110 | 1...110 | Test address and test data are " walking 0 matrix ", increase by one group of complete " 1 " address and complete " 1 " data at last again.Compare verification when reading,, carry out fault diagnosis earlier, positioning and fixing logical one fault and 0-dominance short trouble if finish to find fault at the 3rd step b. |
| Write | 1...101 | 1...101 | ||
| Write | 0...111 | 0...111 | ||
| Write | 1...111 | 1...111 | ||
| Read | 1...110 | 1...110 | ||
| Read | 1...101 | 1...101 | ||
| Read | 0...111 | 0...111 | ||
| Read | 1...111 | 1...111 |
First step test is used for the test data line and whether has open fault and fixed logic fault, and second pacing tries out the test data line whether to have short trouble, and the 3rd pacing tries out the test address line whether to have open circuit or short trouble.Finish to carry out the data line fault diagnosis in second pacing examination, finish to carry out the address alignment fault diagnosis in the 3rd pacing examination.
The fault diagnosis of first step test is fairly simple, does not read entirely 0 if write complete 0, just illustrates that there is the fault of S-A-1 in data line, and numerical value is that 1 data line is exactly the fault wire position that S-A-1 takes place.Opposite situation is not read entirely 1 if write complete 1, just illustrates that there is the fault of S-A-0 in data line, and the data line of value bit 0 is exactly the linear position data that the S-A-0 fault takes place.Why utilizing the open fault of two different address test data lines, is for the detection to the data line open fault of the data latching effects that prevents from may exist on the data bus.
Second pacing examination need be judged the linear position data of short trouble and the short trouble of what type, be that of second pacing examination illustrates that (walking that please notes " 0 " and " 1 " in walking 0 and walking 1 algorithm both can be gone to low level from a high position below, also can go to a high position from low level), tentation data line b
3b
2b
1b
0, test vector r
0r
1... r
7
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Expectation value | b 2Open circuit S-A-0 | b 2And b 1Open circuit S-A-0 | b 2And b 1Short circuit 0-dominance | b 2And b 1Open circuit S-A-1 | b 2And b 1Short circuit 1-dominance | b 3And b 0Open circuit S-A-0 b 2And b 1Short circuit o-dominance | |
| b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | |
| r 0 | 1000 | 1000 | 1000 | 1000 | 1110 | 1000 | 0000 |
| r 1 | 0100 | 0000 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 2 | 0010 | 0010 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 3 | 0001 | 0001 | 0001 | 0001 | 0111 | 0001 | 0000 |
| r 4 | 0111 | 0011 | 0001 | 0111 | 0111 | 0111 | 0110 |
| r 5 | 1011 | 1011 | 1001 | 1001 | 1111 | 1111 | 0000 |
| r 6 | 1101 | 1001 | 1001 | 1001 | 1111 | 1111 | 0000 |
| r 7 | 1110 | 1010 | 1000 | 1110 | 1110 | 1110 | 0110 |
Note that when the test data line must fix an address and carry out, so no matter what fault is address wire exist, and do not influence the test result of data line.After the data line end of test (EOT), just go to do the address wire test.
Diagnostic process to the open fault of data line and short trouble is as follows:
BEGIN
Each row V of the actual test response matrix V of FOR
i
IF V
iRespective column T with the Expected Response matrix T
iInconsistent
There is fault in report;
IF V
iEach component all be fixed as 1
Report that 1 open fault has taken place to be fixed as i bar data line;
ELSE IF V
iEach component all be fixed as 0
Report that 0 open fault has taken place to be fixed as i bar data line;
There are a plurality of row in ELSE IF, and its vector equates that its value is the result of the logical OR computing of the Expected Response of these several row
1-dominance short trouble takes place in many data lines of report respective column
There are a plurality of row in ELSE IF, and its vector equates that its value is the Expected Response of these several row
The result of logic and operation
0-dominance short trouble takes place in many data lines of report respective column
ELSE
The report fault type can't be judged, reports simultaneously which data lines is fault occur on
END IF
END IF
END FOR
There is not fault in IF
Fault is not found in the test of report data line;
END。
After guaranteeing that data line does not have fault, can carry out the 3rd pacing examination, address wire is tested, be that of the 3rd pacing examination illustrates below, suppose that address wire is a
3a
2a
1a
0, test data is different, and numerical value equates with the address.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Address a 3a 2a 1a 0 | Expectation value | The a2 S-A-0 that opens a way | A2 and a1 open circuit S-A-0 | A2 and a1 short circuit 0-dominance | A2 and a1 open circuit S-A-1 | A2 and a1 short circuit 1-dominance | A3 and a0 open circuit S-A-0 a2 and a1 short circuit 0-dominance |
| 0001 | 0001 | 0001 | 0001 | 0001 | 0001 | 0001 | 0000 |
| 0010 | 0010 | 0010 | 0000 | 0000 | 0000 | 0100 | 0000 |
| 0100 | 0100 | 0000 | 0000 | 0000 | 0000 | 0100 | 0000 |
| 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 0000 |
| 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 |
| 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 1111 |
| 1101 | 1101 | 1101 | 1111 | 1011 | 1111 | 1111 | 1011 |
| 1011 | 1011 | 1111 | 1111 | 1011 | 1111 | 1111 | 1011 |
| 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 1111 |
| 1111 | 1111 | 1111 | 1111 | 1111 | 1111 | 1111 | 1111 |
Diagnosis principle and data line fault diagnosis to address wire open fault and short trouble are similar, and roughly flow process is as follows:
BEGIN
Analyze the test response of walking 1 earlier
IF reads data and desired data is in full accord
Report address wire walking 1 test of heuristics is not found fault;
ELSE
FOR analyzes the value of reading back and inconsistent each address of expectation value
The data that the non-all zeros address of IF reads back are complete 0
Note, may be fixed logic 0 fault, abort situation is this address
The address wire of corresponding numeral " 1 "
The data that ELSE IF exists a plurality of addresses to read back are equal, and non-complete 0
Noting, is 1 dominance short trouble, the phase of corresponding these several addresses
The address wire short circuit of different address bit
ELSE
The report fault type can't be judged, reports simultaneously which takes place fault
On the address.
END FOR
Analyze the test response of walking 0 more earlier
IF reads data and desired data is in full accord
Report address wire walking 0 test of heuristics is not found fault;
ELSE
FOR analyzes the value of reading back and inconsistent each address of expectation value
The data bit complete 1 that the non-all ones address of IF reads back
Note, may be fixed logic 1 fault, abort situation is for being somebody's turn to do
The address wire of the corresponding digital " 0 " in address
The data that ELSE IF exists a plurality of addresses to read back are equal, and non-complete 1
Noting, is 0 dominance short trouble, corresponding these several addresses
The address wire short circuit of different address bit
ELSE
The report fault type can't be judged, reports simultaneously which takes place fault
On the address.
END FOR
At last diagnostic result is carried out analysis-by-synthesis
There is the address wire of fault in FOR
This address wire of IF is judged as 0-dominance short trouble or 1-dominance short circuit event
Barrier
Conclude that then this address wire is 0-dominance short trouble or the short circuit of 1-dominance
Fault
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic 1 event
Barrier
Conclude that then this address wire is fixed logic 0 fault or fixed logic 1 fault
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic simultaneously
1 fault
Conclude that then this address wire is the fixed logic fault
ELSE
This address wire exist can't the failure judgement type fault.
END FOR
END
Suppose that the address wire number is d, the data line number is n, then need carry out the inferior operation that reads or writes of 4* (n+d+1) to storage unit altogether.Three-step approach all is 100% to the fault coverage of fixed logic fault (Stuck-at fault), stuck-open fault (Stuck-open fault) and bridge joint short trouble (Short fault), and can carry out fault diagnosis accurately, distinguish dissimilar short troubles.
(2), then carry out fault diagnosis if there is fault in peripheral interconnection line; If do not find fault, then the storage array of dual-ported memory to be tested by a side system of dual-ported memory, testing algorithm can adopt " nine step checkerboard pattern methods ".(note when storage array is tested, also just the address decoder and the i/o controller of this side of dual-ported memory carried out testing completely)
So-called " nine step checkerboard pattern methods ", it is exactly the form that when detecting data cell, adopts checkerboard pattern, when detecting address decoding, adopt the method for testing of nine steps, concrete execution flow process is shown in Fig. 2 A, Fig. 2 B, the characteristics of this method of testing are: the form of the similar checkerboard pattern of test data, just data " 01...0101 " and " 10...1010 " staggered form; Test is divided into 5 steps, 9 times read-write operations, 1., the address ascending order writes " 01...0101 ", 2., the address ascending order reads " 01...0101 ", verification writes " 10...1010 " immediately, 3., the address ascending order reads " 10...1010 ", verification writes " 01...0101 " immediately, 4., the address descending is read " 01...0101 ", 5., the address descending reads " 10...1010 " verification writes " 10...1010 " immediately,, verification writes " 01...0101 " immediately.Test data in the above step " 01...0101 " and " 10...1010 " can exchange, and do not influence the test effect; In like manner, also may carry out according to the step of address ascending order again, also do not influence the test effect earlier according to the address descending.
Nine step checkerboard pattern methods all are complete to the test of fixed logic fault, stuck-open fault, state exchange fault, state coupling fault and multiple Write fault.This method of testing need be carried out 5 times write operations and 4 times read operations to storer, comes to read-write operation 9 times, and the test data that adopts is chessboard alternating graph mode, so be referred to as nine step checkerboard pattern methods in the present invention.
(3) if find in the 2nd pacing examination that there is fault in the dual-ported memory internal storage unit, then reports the address of breaking down; If do not find fault, then the address decoder and the i/o controller of opposite side to be tested, testing algorithm can adopt " unique address/data method ".
" unique address/data method " that the present invention proposes can partly effectively be tested address decoder and i/o controller.Because a side of dual-ported memory has been carried out the test of nine step checkerboard pattern methods, so except storage array having been carried out test fully, also address decoder and the i/o controller to this side carried out test fully.But the address decoder and the i/o controller of an other side are not also tested.If at this moment the test of carrying out opposite side with nine step checkerboard pattern methods again just obviously has some unnecessary.Because need the just address decoder of test and the fault of i/o controller now.So to the test of address decoder and i/o controller, just suitable adopt a kind of method of testing more fast--" unique address/data method ".
The step of this method of testing is as follows:
If data line is less than the situation of address wire, then according to the number of data line with the address space piecemeal, the size of each piece is exactly the maximum data that data line can be represented, guarantee then within each piece, each data corresponding address is unique (obviously the data of each address correspondence also is unique in each piece), guarantee as far as possible that simultaneously between piece and the piece, test data is removed beyond the high position of increase, the data of corresponding identical address low level are also different.
Concrete method of operating is exactly to write data 0 first address 0, and address 1 writes data 1 ..., until last address of first writes maximum data.The data scrolling that writes in second block address once, promptly write successively data 1,2 ..., maximum data, 0.Roll again once in the data that the 3rd block address writes ..., the rest may be inferred.Read successively from low to high by the address at last and compare.
Giving one example illustrates, the tentation data line has 4, and address wire is more than 4 situation.Then unique address/data method is carried out read-write operation one time, data that write and read such as following table:
| Piece number | The address | Data | ||
| The decimal system | Scale-of-two | Scale-of-two | Sexadecimal | |
| Block1 | 0 | 0000 | 0000 | 0 |
| 1 | 0001 | 0001 | 1 | |
| 2 | 0010 | 0010 | 2 | |
| …… | …… | …… | …… | |
| 15 | 1111 | 1111 | F | |
| Block2 | 16 | 10000 | 0001 | 1 |
| 17 | 10001 | 0010 | 2 | |
| …… | …… | …… | …… | |
| 30 | 11110 | 1111 | F | |
| 31 | 11111 | 0000 | 0 | |
| Block3 | 32 | 100000 | 0010 | 2 |
| 33 | 100001 | 0011 | 3 | |
| …… | …… | …… | …… | |
| 45 | 101101 | 1111 | F | |
| 46 | 101110 | 0000 | 0 | |
| 47 | 101111 | 0001 | 1 | |
| Block4 | 48 | 110000 | 0010 | 3 |
| 49 | 110001 | 0011 | 4 | |
| …… | …… | …… | …… | |
| 61 | 111101 | 1111 | 0 | |
| 62 | 111110 | 0000 | 1 | |
| 63 | 111111 | 0001 | 2 | |
| …… | …… | …… | …… | …… |
From above example as can be seen, within each piece, each data corresponding address is unique (data of each address correspondence also is unique in each piece certainly), removes simultaneously beyond the high position of increase, and the data corresponding address low level of different masses also is mutually different.First address " 0000 " corresponding data " 0 " for example; The address high position " 1 " of increase is removed in second address, and the data that address low level " 0000 " is corresponding are " 1 "; The address high position " 10 " of increase is removed in the 3rd address, and the data that address low level " 0000 " is corresponding are " 2 "; The address high position " 11 " of increase is removed in the 4th address, and the data that address low level " 0000 " is corresponding are " 3 " ....After handling like this, when appearring in the high address line, stuck-at fault also can be detected.Simultaneously be not difficult to find out that also Block 2 and Block 4 remove after the address high position " 1 " of increase, the data block of corresponding address piece is also inequality.
If address wire is less than the situation of data line, then only need write one time by the address, read through.The numeral that each address writes obtains like this: as a data high position, a high position that intercepts the address again appends to the low level of number of addresses as the data that write with number of addresses.Suppose that the address is 3, data line is 4.The high position of address 001 is 0 so, and the low level that appends to number of addresses obtains 0010, and then the data that write of address 001 are 0010, shown in seeing the following form:
| Address (three) | Data (four) |
| 000 | 0000 |
| 001 | 0010 |
| 010 | 0100 |
| 011 | 0110 |
| 100 | 1001 |
| 101 | 1011 |
| 110 | 1101 |
| 111 | 1111 |
The address is 3 for another example, and data are 5 situation, and then the data that write of address 010 are 01001, and the data that address 101 writes are 10101.If address wire is far smaller than data line, then need to intercept repeatedly, be 3 such as the address, data are 8, and then to write data be 01001001 in address 010, and the data that address 101 writes are 10110110.
Unique address/data method can compare completely test to the fault of address decoder and i/o controller, and it only need carry out a write operation and a read operation, is a kind of quite effectively method of testing.
(4) if the 3rd step was found fault, report that then there are fault in the address decoder of this side or i/o controller; Otherwise all test events are finished, and the report dual-ported memory is normal.
If the various piece of K port store is compared test completely, then testing procedure is as follows:
(1) test the peripheral interconnection line of each port at first successively, specific operation process and dual-ported memory test class are seemingly.
(2), then carry out fault diagnosis if peripheral interconnection line has fault; If do not find fault.Then by a side system of K port store the storage array of K port store is tested, testing algorithm can adopt nine step checkerboard pattern methods.Attention has also just been carried out test completely to the address decoder of this side of K port store and i/o controller when storage array is tested.
(3) there is fault if K port store internal storage unit is found in the 2nd pacing examination, then reports the address of breaking down; If do not find fault, then successively the address decoder and the i/o controller of remaining port partly to be tested, testing algorithm adopts unique address/data method.
(4) if fault is found in the 3rd pacing examination, report that then there are fault in the address decoder of all the other multiports or i/o controller; Otherwise all test events are finished, and the report multiport memory is all normal.
Claims (10)
1. the method for testing of a multiport memory is characterized in that, this method comprises the following steps:
(1), successively test the peripheral interconnection line of each port,, then carry out fault diagnosis if peripheral interconnection line has fault; If peripheral interconnection line is not found fault, then carry out the following step;
(2), the storage array of multiport memory is tested by a port of multiport memory, if there is fault in the memory inside storage unit, the report address of breaking down then; If do not find fault, then carry out the following step;
(3), successively the address decoder and the i/o controller of remaining port are tested, if address decoder and i/o controller have fault, then carry out fault diagnosis; If do not find fault, then end of test (EOT).
2. the method for testing of multiport memory as claimed in claim 1 is characterized in that: to the test of peripheral interconnection line, comprise the following steps: in the described step (1)
(11) in two different addresses, with the stuck-open fault and the fixed logic fault of one group of complete " 1 " data and one group of complete " 0 " Data Detection data line;
(12) fix an address, test data adopts " walking 1 matrix " and " walking 0 matrix " respectively, detects the short trouble of data line;
(13) test address and test data are " walking 1 matrix ", and increase by one group of complete " 0 " address and complete " 0 " data, test one time; Test address and test data are " walking 0 matrix ", and increase by one group of complete " 1 " address and complete " 1 " data, test one time again, detect address wire stuck-open fault, fixed logic fault and bridge joint short trouble.
3. the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21), the address ascending order is write " 01...0101 ";
(22), the address ascending order reads " 01...0101 ", verification writes " 10...1010 " immediately;
(23), the address ascending order reads " 10...1010 ", verification writes " 01...0101 " immediately;
(24), the address descending reads " 01...0101 ", verification writes " 10...1010 " immediately;
(25), the address descending reads " 10...1010 ", verification writes " 01...0101 " immediately.
4. the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21) the address descending is write " 01...0101 ";
(22) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(23) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(24) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(25) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately.
5. the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise step:
(21) the address ascending order is write " 10...1010 ";
(22) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(23) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(24) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(25) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately.
6. the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21) the address descending is write " 10...1010 ";
(22) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(23) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(24) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(25) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately.
7. the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: address decoder and i/o controller to remaining port in the described step (3) are tested, and specifically comprise:
(31) if data line more than or equal to address wire, then all address spaces are tested as a monoblock;
(32) if data line is less than address wire, then the address space piecemeal to be tested according to the number of data line, the size of each piece is exactly the maximum data that data line can be represented.
8. the method for testing of multiport memory as claimed in claim 7, it is characterized in that: within each address block, each data corresponding address is unique, the data in each address correspondence also are unique simultaneously.
9. the method for testing of multiport memory as claimed in claim 7, it is characterized in that: described the address space piecemeal is tested, comprising: write data 0 in first address 0, address 1 writes data 1, ..., until last address of first writes maximum data; In the data that second block address writes is to write on the basis of data in first block address to roll once, promptly write successively data 1,2 ..., maximum data, 0; In the data that the 3rd block address writes is to write on the basis of data in second block address to roll once ..., the rest may be inferred, write all address blocks after, read successively from low to high or from high to low by the address and to compare.
10. the method for testing of multiport memory as claimed in claim 7, it is characterized in that: described address space is tested as a monoblock, comprise: with number of addresses as writing a data high position, one or more high positions according to the figure place of data line intercepting number of addresses append to the low level that writes data again, with the said write data be written to the corresponding address location of described number of addresses in, read verification then.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100695437B1 (en) * | 2006-04-13 | 2007-03-16 | 주식회사 하이닉스반도체 | Multi port memory device |
| CN101303898B (en) * | 2007-05-09 | 2011-08-10 | 智原科技股份有限公司 | Circuit and method for self repairing multiport memory |
| CN101783745B (en) * | 2009-01-21 | 2012-03-14 | 环旭电子股份有限公司 | System and method for testing a plurality of network ports |
| CN103000226B (en) * | 2011-09-08 | 2016-03-23 | 施耐德电器工业公司 | The method of testing of defect is detected by RAM chip address pin |
| CN102543213B (en) * | 2011-12-31 | 2014-07-30 | 大连现代高技术集团有限公司 | Data error-detecting method for EEPROM chip |
| CN105589770B (en) * | 2015-07-20 | 2019-09-06 | 新华三信息技术有限公司 | A kind of method and apparatus of fault detection |
| CN107451017B (en) * | 2016-05-31 | 2021-05-07 | 中车株洲电力机车研究所有限公司 | Reliability test method and system for double-port memory |
| CN110082672B (en) * | 2018-01-25 | 2020-09-11 | 大唐移动通信设备有限公司 | Method and device for testing logic model in chip |
| CN108447524A (en) * | 2018-03-21 | 2018-08-24 | 清能德创电气技术（北京）有限公司 | A method of for detecting external memory interface failure |
| CN110111833B (en) * | 2019-04-03 | 2021-07-13 | 中国科学院微电子研究所 | Memory verification circuit and verification method |
| CN110954804B (en) * | 2019-12-19 | 2021-11-02 | 上海御渡半导体科技有限公司 | Device and method for accurately diagnosing cBit array faults in batch |
| CN112053739B (en) * | 2020-09-04 | 2023-04-11 | 上海思尔芯技术股份有限公司 | Memory detection method and device |
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