JPS6230662B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a storage circuit that is composed of a memory and a backup memory and that shares a readout circuit.
In particular, the present invention relates to a memory backup method that slows down the read time of the backup memory when an error occurs during memory read.

(b) Prior art and problems Memory that uses dynamic memory elements, etc., has temporary defects (called soft errors) that can be used normally by rewriting, so it is difficult to use backup memory for backup purposes. If a soft error occurs in the backup memory, the data recorded in the backup memory is read and rewritten. There are disadvantages that are not economical.

(c) Object of the invention In order to eliminate the above-mentioned drawbacks, the object of the invention is to provide an economical backup memory in which a memory with a slow read speed can be used and a common bus can be used as the address bus and the read bus. The purpose of the present invention is to provide a flexible memory backup method.

(d) Structure of the Invention The structure of the present invention is such that a memory and a backup memory for backing up the memory are provided, and an address bus, a write bus, and a read bus are common to both memories. When a memory error occurs in the memory, data is read from the backup memory to the common read bus at a slow read speed.

(e) Embodiment of the Invention FIG. 1 is a block diagram of a circuit showing an embodiment of the invention.

When writing data, write data is input from write bus A, and the data is written and stored in memory 1 and backup memory 2 by simultaneously specifying the address via address bus E according to the address in address register 3. .

Normally, the data stored in the memory 1 is read out by setting the backup enable signal line C to "1" so that the chip select CS terminal of the memory 1 becomes "0" by the NOT circuit 5.
It is now being read out. On the other hand, in the backup memory 2, the chip select CS terminal is always set to "0", the backup enable signal line C is normally set to "1", and the tristate gate 4 controls the readout of the backup memory 2 from the readout bus. It becomes a high impedance and blocks B.

If an error is detected by a separate means (not shown) during normal reading of memory 1, the backup enable signal line C becomes "0", the chip select CS terminal of memory 1 becomes "1", and memory 1 reading is aborted. On the other hand, as mentioned above, the chip select CS terminal of the backup memory 2 is always "0", and when the backup enable signal line becomes "0", the tristate gate 4 becomes conductive and the backup memory 2 is read out. Read out onto bus B.

OR circuit 6, AND circuit 7 and frequency divider circuit 8 in Figure 1
forms a clock circuit, and the common clock for memory 1 and backup memory 2 is supplied from clock line D through this clock circuit. When the backup enable signal line C is “1”, it passes through the OR circuit 6 and the AND circuit 7.
to go into. Therefore, the AND circuit 7 passes the clock input from the clock line D as is. However, when the backup enable signal line C becomes “0”
The AND circuit 7 passes the clock based on the output of the frequency divider circuit 8. FIG. 2 is a time chart illustrating the relationship between the output waveform of the frequency dividing circuit 8 and the outputs of the clock and AND circuit 7. The frequency divider circuit 8 sends out an output that is inverted every time the clock waveform falls, and therefore, the output of the AND circuit 7 is a waveform with a period twice that of the clock. Therefore, the data in the backup memory 2 is read out in twice the time taken to read out the memory 1. In other words, the read time of the backup memory 2 is twice as long as the read time of the memory 1.

(f) Effects of the Invention By implementing the present invention as explained above, it is possible to use a memory with a slow read speed as the backup memory, and it is also possible to use a common bus as the address bus and the read bus. Therefore,
The effect is great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 2 is a time chart explaining the operation of FIG. 1 is memory, 2 is backup memory, 3 is address register, 4 is tri-state gate, 8
is a frequency divider circuit.

Claims (1)

[Claims] 1. A memory and a backup memory for backing up the memory are provided, and an address bus, a write bus, and a read bus are common to both memories, and a memory error occurs in the memory. In this case, the memory backup method is characterized in that data is read from the backup memory to the common read bus at a slow read speed.