JPS6084632A - Disk controller - Google Patents

Abstract

PURPOSE:To perform rewriting processing in a short time without using a common data transfer path by rewriting the data of a buffer memory corresponding to data in a sector where an error is detected in a substitutive sector. CONSTITUTION:Data read out of a main storage device 1 is sent out to an optical disk device 6 through a bus 2, DMA control circuit 3, buffer memory 4, and optical disk control circuit 5. The optical disk controller 5 checks on whether an error occurs to data written right after writing operation. If the error is detected, the sector number of the error detection is held and readout error chekcing operation is carried on. The data corresponding to the error-detected sector is rewritten in a substitutive sector #n+m from a sector #n+1 after a check on a readout error of the written data is made. In this case, the start and end addresses of data of the error-detected sector in the buffer memory are set in counters 8 and 9 and the data between them are sent out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a disk control device used in a data processing/system including a main storage device, a common data transfer path, and a disk device, and which controls the disk device.

<Prior art> In a conventional optical disk control device, the re-biting process that occurs when an error is detected immediately after 1 writing is performed by reading out the take used for 4jJ writing again from the main storage device via the common data transfer path and sending it to the optical disk device. A method called 舊#;include has been used. Therefore, the phase-in operation is delayed due to the readout from the main memory, and other input/outputs connected to the common data transfer path cannot use the common data transfer path. flill Q4j! There was a drawback that data transfer at position 4 and ξ was impaired.

<Object of the Invention> The object of the present invention is to provide a disk control device that can efficiently perform a write operation in a short processing time without using a common data transfer path in the reloading process of an optical disk device. It is in.

<Summary of the Invention> According to the present invention, a data processing/processing system including a main storage device, a common data transfer path, a disk control device, and a tisf device.
In the system, the main storage device and the disk control device row are connected to the common data transfer path, and the disk control device has a buffer memory with a capacity larger than the maximum transfer unit of the disk device, a direct memory access circuit, and a buffer. The first one controls data transfer to and from memory.
an address counter circuit, a second address color/recircuit that performs data transfer between the disk open side circuit and the buffer memory, and the first and...
2 times to control the address counter circuit + 1''''6
Immediately after executing the permission operation of the tisf device, an error check operation is executed to detect the presence or absence of an error in the input data, and if an error is detected, the data is not transferred again from the main storage device. , the data in the buffer memory corresponding to the data in the sector in which the error has been detected is re-introduced into the alternative sector of the tisf device i''i.

<Example> Next, an example of the present invention will be described with reference to the drawings. Figure 1 is a fruit of this invention/Ii! FIG. 2 shows a track format written on an optical disk medium used in i'611, and FIG. 2 shows an optical disk control device in an embodiment of the present invention. In the 21st step, main memory 1
a direct memory access (hereinafter referred to as DMA) control circuit 3 that can be directly accessed via a common data transfer path 2 (hereinafter referred to as bus); an optical disk control circuit 5 that controls the optical disk device 6; A buffer memory 4 having a capacity larger than the transfer unit, and I) I'v'lA.
An address counter circuit 7 (hereinafter referred to as a first counter) that controls data transfer between the control circuit 3 and the buffer memory 4; and an address counter circuit 8 that controls data transfer between the optical disk control circuit 5 and the buffer memory 4. (hereinafter abbreviated as the second counter), the tenth counter 7 and the second counter
A counter control circuit 9 for controlling the colors/returns 8 is provided.

The DMA control path 3 is connected via a bus 2 to the main memory 1 and to a buffer memory 4 . Further, the optical disk control circuit 5 is connected to the buffer memory 4 and the optical disk device 6, and controls the transmission and reception of data between them. Further, the optical disk control circuit 5 is connected to the DIV[A control circuit 3 via a signal line 10, and is configured to transmit and receive various control signals. DMA control circuit 3. Buffer memory 4, disk control circuit 5. 1st. The second counter 7.8 and the counter control circuit 9 constitute an optical disk control device 11.

The data read from main memory 1 is transferred to bus 2゜DMA.
G11ll It circuit 3. Buffer memory 4. It is sent to the optical disk device 6 through the optical disk control circuit 5,
Sector f in Figure 1? The data is written in the primitive sectors 1 to sector+n, but is once stored in the buffer memory 4 which functions as a first-in, first-out (FIFO) memory. This buffer memory 4 has a DMA control circuit 1 (a first counter 7 controls the transfer between the circuit 3 and the buffer memory 4, and a first counter 7 controls the transfer between the optical disk control circuit 5 and the buffer memory 4). This is done by the counter 8 of 2.

The original disk control device 5 [Checks whether there are any errors in the data that has entered immediately after the end of the prowling operation/C outputs the data that was inserted into the optical disk device 6, and then outputs the data from the optical disk device 6. The i control circuit 5 executes an error check operation. Here, if an error is detected, the sector signal of error detection is held and the M-shape output error check operation is continued. After the read error check operation of the introduced data is completed, the data corresponding to the sector where the error occurred is transferred to sectors +11+1.
sector ≠ n When reinterpretation is executed to a free sector in the 10m alternative sector, the address corresponding to ν■1VC of the data in the error sector of the buffer memory 4 is set to the second address.
The first counter 8 is set to the address corresponding to the end of the data, and the address corresponding to the end of the data is set to the first counter 9, and the data in between is sent to the optical display device 6, thereby executing reloading.

This invention is light! ′, :fFff, and can also be used to control magnetic tasks :lj for general magnetic tisf devices.

<Effects> As described above, the optical tisf control device of the present invention enables reprogramming operation in a short processing time without blocking the common data transfer path during the reprogramming process of the optical tisf device. It is possible to carry out n].

[Brief explanation of drawings]

Figure 1 shows an optical tisf medium used in an embodiment of this invention.
Figure 2 does not show the track format of this release.
This is block 1/1 showing the installation of an optical disk 11, which is an example of JIJ. 1: Main memory, 2: 4J data transfer path (bus),
3: Direct memory access (DMA) control circuit 1111° 4: Buffer memory, 5: Optical Tisp control l111 circuit, 6: Optical Tisp kwL, 7: Address counter circuit for m1, 8: Second address counter circuit , 9
: Counter control circuit 113, Jl: Optical disk ili control device. Patent applicant: Takashi Kusano, representative of NEC Corporation

Claims (1)

[Claims] (1) In a take processing system including a main storage device and a disk control device connected to a common data transfer path, and a disk device controlled by the disk control device, the disk control device a buffer memory with a capacity larger than the maximum transfer unit of a disk device, a direct memory access circuit and a first address counter circuit for controlling data transfer between the buffer memory, a transfer control circuit and data between the buffer memory; It includes a second address counter circuit for controlling transfer and a circuit for controlling these first and second address counter circuits. Take error dlj]
i, and if an error is detected, the take in the buffer memory corresponding to the take in the sector in which the error was detected is repopulated to an alternative sector of the disk device for a length of qh. Disk control device.