JPS6292039A - Data processor - Google Patents

Abstract

PURPOSE:To investigate accurately the cause of a fault by detecting all memory areas of a state memory device if they are used, inhibiting the writing actions and reading out the contents stored in the state memory device to store them in another memory device. CONSTITUTION:The contents of a write address register 3 as well are replaced as the internal state information of a data processor 1 is written to a state history memory device 2 by a state information signal 10. Then the contents of the register 3 as well are sent to a tracer control circuit 7 by a carry signal 14 when they are changed to 00 from an FF. When a holding signal 15 is set at logic 1, the operation of the processor 1 is discontinued and therefore no writing action is carried out to the device 2. In this case, the contents of a read address register 5 are set at 00 and the contents of the address 00 to be stored in the device 2 is read out to the circuit 7. Then the contents of the register 5 is set at 01 by an address replacement signal 17. While the contents read out of the storage 2 is written to a main memory device 8 by an output signal 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that has a state history storage device that sequentially stores the internal state of the device and is used to find the cause of a failure.

[)Renovation]

In a data processing device having a state history storage device that stores the internal state of the device, the present invention detects when the entire storage area of the state storage device is used, prohibits writing, and stores the retained contents. By providing a means to read and store the information in another storage device, the internal state of the data processing device can be retained for a long period of time, allowing accurate investigation of the cause of the failure.

[Prior Art] Conventionally, when a data processing device detects an abnormality during operation and stops its operation, the appropriate internal state of the device until the abnormality is detected is stored as a history, and the contents are examined. This makes the use of tracers an effective means of identifying the cause of failures.

[Problems that inventions can solve]

In a conventional data processing device, the internal state of 8
Input is limited to the storage area of the state history storage device, so
After the storage area is all used, the portion that has already been written will be overwritten. Therefore, the ζ data processing device detects an error during operation and starts the error ilD processing.
5 After a while, a problem occurred ([, 1, talike 1 luck (r,
',, +', :i, (iλNeri's error process J
') When 9 is new and 7 is 1 blue report and 3 is A, there is a drawback that it is difficult to find the cause of the problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device having a state history storage device that can retain the internal state of the data processing device for a long period of time and accurately track down the cause of a failure by eliminating the above-mentioned drawbacks.

[Failure to solve the problem]

The present invention provides, in a data processing device having a state history storage device for sequentially storing the internal state of the device, means for detecting that all the storage area in the state history storage device is used and outputting a detection signal; a second storage device; and means for inhibiting writing from the data device to the state history storage device based on a detection signal from the means, and transferring the retained contents to the first storage device. I have things
4 and 4''.

[Operation] 4. In the invention, the means for outputting a detection signal detects that the storage area of the state history storage device is all used, and the means for outputting the detection signal and transferring the state history by means of the second detection signal. Writing to the storage device is prohibited, and the retained contents are read and stored in another storage device. Therefore,
Records of the internal state of the data processing device will not be lost, making it possible to accurately identify the cause of the failure.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes a state history storage device 2 that sequentially stores the internal state of the data processing device 1, and a write address register 3 that serves as a means for detecting that all of the 4 Iq areas of the seventh record have been used and outputting a detection signal. and the adder 4 and the carry signal 14 of the detection signal, prohibit writing of the internal state by the address register 3 from the data processing device 1 to the device 2 that records the status 1. Then, the contents held in the state history storage device 2 are transferred to the main storage device 8, which is a second storage device, and the contents are read out. It includes an inverter 6 and a tracer control circuit 7.

A feature of the present invention is that in FIG.
, an adder 4.6, a read register 5 and a tracer control circuit 7.

Next, the operation of this embodiment will be explained. Data processing device 1 transmits internal state information to state history storage device 2 through state information signal 10, and sends trace timing signal 11 to state history storage device 2 and write address register 3. State history record 1.1 The device 2 writes the contents of the state 1 voice information signal 10 to the address indicated by the input signal 3 according to the trace timing signal 11. On the other hand, the value updated by the adder 4 is set in the write completion trace register 3 by the trace timing signal 11. When the storage area of the state history storage device 2 runs out, the carry signal 14 from the most significant bit of the adder 4 is
- sent to the tracer control circuit 7, tracer control circuit ゛i
A hold signal 15 to the data processing device I is outputted from Iη. Furthermore, the contents of the address indicated by the read address register 5 of the state history storage device 2 are read out as the read signal 19. The read address register 5 is set with the result updated by the adder 6 in response to the address update signal 17 from the tracer control circuit 7. A carry from the most significant digit of the adder 6 is sent to the tracer control circuit 7 by a carry signal 21. The tracer control circuit 7 sends the contents of the read signal 19 read from the state history storage device 2 to the main storage device 8 as an output signal 20.

Now, assuming that the state history storage device 2 has a capacity of 256 words, a more detailed explanation will be given with reference to the timing chart shown in FIG. As the internal state information of the data processing device 1 is written to the state history storage device 2 by the state information signal 10 by the trace timing signal 11 from the data processing device 1, the contents of the write address register 3 are also updated. When the contents of the write address register 3 change from (FF) (hexadecimal number) to (00) (hexadecimal number), it is transmitted to the tracer control circuit 7 by the carry signal 14, and thereby the hold signal 15 becomes logic "1". As a result, the operation of the data processing device 1 is stopped, and therefore no writing is done to the state history storage device 2. On the other hand, the read address register 5 at this time is (00
) (hexadecimal), the contents of address (00) in the state history storage device 2 are read out to the tracer control circuit 7,
The address update signal 17 causes the contents of the read address register 5 to become (01) (hexadecimal). The contents read from the state history storage device 2 are written to the main storage device 8 by means of an output signal 20. In this way, one word is read out and written to the main memory 8, and when the contents of the read address register 5 change from (F F) (hexadecimal number) to (00) (hexadecimal number), a carry signal is sent. 21, the hold signal 15 becomes logic "0", the operation of the data processing device 1 is resumed, and writing to the state history storage device 2 is also performed.

In FIG. 1, 12 is a write address register output signal, 13.18 is an adder output signal, and 16 is a read address register output signal. FIG. 2 also shows the input point of the clock.

Further, in the above embodiment, the second storage device is the main storage device, but it goes without saying that it may be provided separately.

〔Effect of the invention〕

As explained above, the present invention detects that all of the storage area in the state history storage device has been used, prohibits writing to it, reads the retained contents, and stores them in the second storage device. This has the effect of allowing the internal state of the processing device to be preserved for a long period of time, allowing accurate investigation of the cause of the failure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a timing chart showing the operation. ■...Data processing device, 2...State history storage device,
3... Interpretation address register, 4.6... Adder, 5... Read address register, 7... Tracer control circuit, 8... Main storage device, 10... Status information signal, 11...Trace timing signal, 12...Write address register output signal, 13.18...Adder output signal, 14.21...Carry signal, 15...
Hold signal, 16... Read address register output signal, 17... Address update signal, 19... Continuation signal, 20... Output signal.

Claims (1)

[Claims] (1) In a data processing device having a state history storage device that sequentially stores the internal state of the device, means for detecting that all the storage area in the state history storage device is used and outputting a detection signal; a storage device; and means for inhibiting writing from the data device to the state history storage device based on a detection signal from the means, and transferring the stored contents to the second storage device. data processing equipment.