JPH05282857A - Memory card device - Google Patents

Abstract

PURPOSE:To furnish a memory card device which makes it possible to monitor the internal state of a card from outside the card sufficiently without impairing prescriptions of standardization. CONSTITUTION:An address/data switching signal, designating whether data supplied to a bus line is an address or data, represents an address AD input and thereby a read/write switching signal designating writing or reading the data is set in a state of reading the data. In a memory card device 11 outputting card status information at this time, a bus clock is given from outside according to the state of output of the card status information, and thereby a flag byte representing the internal state of a card is outputted instead of the card status information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and in particular, the internal condition thereof impairs standardization regulations. For things that can be monitored without.

[0002]

As is well known, EEPROMs are currently
It has attracted attention as a data recording medium that replaces magnetic disks, and it does not require a backup battery for holding data and can reduce the cost of the chip itself. SRAM (static random access memory) ) Or D (dynamic) RAM has a unique advantage that it does not have, and therefore, development for use as a memory card has been actively conducted.

In this memory card, for example, an optical image of a photographed subject is converted into an electric image signal by using a solid-state image pickup device, the image signal is converted into digital image data, and recorded in a semiconductor memory. A memory card that is suitable for use in still cameras, etc., and has an EEPROM built into a card-shaped case that can be attached to and detached from the camera body, so that it can be handled equivalent to a film in a normal camera. It is designed to be able to.

By the way, the EEPROM is an SRAM or a D
Unlike RAM, there are limits to the number of times data can be written, the data retention period, and the like. That is, normally, the number of times of writing data in the EEPROM is 10 ⁴ It is guaranteed up to 10 times and the data retention period is guaranteed up to 10 years. For this reason, in the EEPROM whose guaranteed number of times or guaranteed period has passed, the memory cell itself is apt to have a defect, and a defective storage region in which data cannot be normally written and held occurs.

Therefore, in the past, such EEPRO has been used.
In order to relieve the loss of data due to the request to write data to the defective storage area of M, the address specified for writing data from outside the memory card is
If the defective storage area of the EEPROM, the data is stored in another normal storage area inside the memory card, and the address of the data storage area and the external designated address are associated with each other by the link table. ing.

As described above, EEPRO is used as a semiconductor memory.
A memory card using M tends to have a complicated system, unlike a memory card using SRAM or DRAM, and due to the complexity, there is a strong demand for monitoring the internal state of the card from outside the memory card. Become. The current memory card using the EEPROM is standardized only to have a mode of outputting card status information such as a detection bit of the card and how many byte addresses are input to the outside. However, there is a problem that the internal status of the card cannot be sufficiently grasped only by the above card status information.

[0007]

As described above, the conventional memory card using the EEPROM as the semiconductor memory has a problem that the internal condition of the card cannot be sufficiently monitored from the outside of the card.

Therefore, the present invention has been made in consideration of the above circumstances, and it is an object of the present invention to provide a very good memory card device capable of sufficiently monitoring the internal condition from the outside of the card without impairing the standardization standard. To aim.

[0009]

In the memory card device according to the present invention, an address / data switching signal designating whether the data supplied to the bus line is an address or data indicates an address input, and whether the data is written or read. When the read / write switching signal designating "1" is set to the data read state, it is intended for outputting the card status information. Then, by applying a bus clock from the outside in the output state of the card status information, a flag byte representing the internal status of the card is output instead of the card status information.

[0010]

According to the above configuration, the bus byte is externally applied in the output state of the card status information so that the flag byte representing the internal status of the card is output instead of the card status information. The internal condition can be sufficiently monitored from the outside of the card without impairing the standardization regulations.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a memory card of an electronic still camera will be described in detail below with reference to the drawings. In FIG. 1, reference numeral 11 is a memory card main body, and a connector 12 installed at one end thereof.
Via an electronic still camera body (not shown). The connector 12 is supplied with digital data DA to be written in the memory card body 11 and address data AD indicating the writing location from the electronic still camera body side. The digital data DA and the address data AD are transferred to the bus lines D0 to D0.
Data input / output control circuit 1 having a built-in CPU via D7
3 is being supplied.

Also, from the electronic still camera body, to the connector 12, a card enable signal CE which becomes H (high) level when the memory card body 11 is selected.
When the data supplied to the bus lines D0 to D7 is the address data AD, it is at the L (low) level, and when it is the digital data DA, it is at the H level and the address / data switching signal A / D and the data write request to the EEPROM When it is L level, when data read request is H
A level read / write switching signal R / W and a bus clock BCK synchronized with the address data AD are supplied.

These card enable signal CE, address / data switching signal A / D, read / write switching signal R
/ W and the bus clock BCK are also supplied to the data input / output control circuit 13. Further, from the electronic still camera body, a command for requesting data erase to the EEPROM is also supplied to the data input / output control circuit 13 via the connector 12. Then, the data input / output control circuit 13 generates a ready / busy switching signal RDY / BSY which becomes H level when the input of the digital data DA from the electronic still camera body is permitted and becomes L level when the input is rejected. Is becoming

Here, the schematic operation will be described. The digital data DA supplied to the connector 12 is described.
Under the control of the data input / output control circuit 13, is temporarily stored in the buffer memory 14 and recorded. At this time, the fetch timing of the digital data DA of the buffer memory 14 is controlled by the address data output from the address generation circuit 15. The address generation circuit 15 also counts the clock CK selected by the selector 16 to generate address data for the buffer memory 14. The selector 16 includes the bus clock BCK and the data input / output control circuit 1
The clock YCK output from the circuit 3 is supplied.

When the digital data DA is taken into the buffer memory 14, the selector 16 outputs the select signal SEL output from the data input / output control circuit 13.
The bus clock BCK is selected by and is derived to the address generation circuit 15 as the clock CK. For this reason,
The digital data DA sent from the electronic still camera body to the connector 12 is written in the buffer memory 14 according to the address data generated based on the bus clock BCK.

After that, when the writing of the digital data DA into the buffer memory 14 is completed, the data input / output control circuit 13 controls the select signal SEL to output the clock YCK generated by itself to the address generation circuit 15. The selector 16 is switched as follows. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 15 based on the clock YCK.
The digital data DA is read from 4.

At this time, the data input / output control circuit 13 is
The chip enable signal CEN and the write enable signal WE are output to the EEPROM 17 formed of a plurality of chips, the address data AD is output, and the digital data DA read from the buffer memory 14 is output.
Control is performed so that the data is written in the EEPROM 17, for example, in 512-byte page units. Then, in a state where the digital data DA is written in the EEPROM 17, the data input / output control circuit 13 outputs the out enable data OE and the address data AD that previously specifies the writing of data to the EEPROM 17, and the EEPROM 17
The write verify is executed to read the written digital data DA from, and determine whether the digital data DA matches the digital data DA recorded in the buffer memory 14.

If the digital data DA read from the EERPOM 17 and the digital data DA recorded in the buffer memory 14 do not match, the data input / output control circuit 13 again outputs the data from the buffer memory 14 to E.
The digital data DA is transferred to and written in the EPROM 17, and this operation is repeated until the digital data DA read from the EERPOM 17 and the digital data DA recorded in the buffer memory 14 completely match. DA EEPROM 17
Is written to.

In addition, from the electronic still camera body to the EEPR
When an instruction to erase (erase) the data recorded in the OM 17 is generated, the data input / output control circuit 13 drives the erasing circuit 18 based on the erasing instruction. The erasing circuit 18 outputs an erasing signal to the address line and the data line of the EEPROM 17 under the control of the data input / output control circuit 13, thereby the EEPROM
17 is electrically chip-erased or page-erased. The erase circuit 18 may be incorporated in the EEPROM 17. In this case, by issuing an erase command from the data input / output control circuit 13 to the EEPROM 7, the erase circuit in the EEPROM 17 receives this command and the erase operation is performed.

Next, the operation of reading the digital data DA from the EEPROM 17 to the outside of the memory card body 11 will be described. First, a read request and a recorded address of data to be read are specified from the electronic still camera body side via the connector 12. Then, the data input / output control circuit 13 sends the chip enable signal CEN and the out enable data O to the EEPROM 17.
E and address data AD are output, and the EEPROM 17
The digital data DA is read in page units from, and the selector 16 is switched so that the clock YCK generated by itself is derived to the address generation circuit 15 and written in the buffer memory 14.

Thereafter, the data input / output control circuit 13 switches the selector 16 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 15, and the bus clock BCK. Based on the address data generated by the address generation circuit 15, the data is read from the buffer memory 14 and led out to the electronic still camera body through the connector 12, and the digital data DA is read there.

Here, the standardized mode for reading the card status information will be described. That is, the digital data DA for the EEPROM 17 described above
Seen from the outside of the memory card body 11, that is, the signals input and output through the connector 12, when writing and reading the digital data DA to and from the memory card body 11. First, the card enable signal CE is set to H level to select the memory card main body 11, and both the address / data switching signal A / D and the read / write switching signal R / W are set to L level (write state by address input), The address data AD is supplied to the bus lines D0 to D7 to set the address. After that, by setting the address / data switching signal A / D to the H level (data input), writing and reading of the digital data DA to / from the memory card body 11 are performed.

Therefore, in the normal write and read operations, both the address / data switching signal A / D and the read / write switching signal R / W are at the L level when the address is set. Therefore, as shown in FIG. 3, the address / data switching signal A /
When the D / L level and the read / write switching signal R / W are set to the H level, the data input / output control circuit 13 is designed to send the card status information as digital data DA to the bus lines D0 to D7. ing. The bus clock BCK is not used in the standardized output mode of the card status information.

Here, in the output state of the card status information as described above, when the bus clock BCK is supplied as shown in FIG. 2, the data input / output control circuit 13 is provided.
Stops sending card status information to the bus lines D0 to D7 in synchronization with the first bus clock BCK,
It operates so as to send flag bytes 1, 2, ... To the bus lines D0 to D7 in synchronization with the second and subsequent bus clocks BCK. For example, "10000000" indicates that an error has occurred, "11000000" indicates that the card has reached the end of its life, "10100000" indicates that a defect has occurred, and "10010000" indicates the flag bytes 1, 2, ... Indicates that hot-line removal has occurred (the memory card body 11 was pulled out during data transfer with the electronic still camera body), and "10001000" indicates that some error occurred inside the card and calls a service person. "10000100" indicates that the addressing is different, and "10000010" indicates write protection.
Indicates that it is hanging.

In this case, when the bus clock BCK is supplied in the output state of the card status information, the data input / output control circuit 13 outputs the ready / busy switching signal RDY / BSY to L in synchronization with the first bus clock BCK. When the level is set, the external input is rejected, and flag bytes 1, 2, ... Are set in an output register (not shown) in the card. When the flag bytes 1, 2, ... Are set in the output register, the data input / output control circuit 13 sets the ready / busy switching signal RDY / BSY to the H level to set the bus clock for the second and subsequent times. In synchronization with BCK, flag bytes 1, 2, ...
Send to 7.

Therefore, according to the configuration of the above embodiment, when the bus clock BCK is supplied in the output state of the card status information, the flag bytes 1, 2, ... Since the data is output, the internal status of the memory card body 11 can be sufficiently monitored from the outside of the card by the flag bytes 1, 2, ... without impairing the standardization for outputting the card status information. Become. The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0027]

As described in detail above, according to the present invention,
It is possible to provide an extremely good memory card device capable of sufficiently monitoring the internal condition from the outside of the card without impairing the standardization standard.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a timing chart shown for explaining an output operation of card status information.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Data input / output control circuit, 14 ... Buffer memory, 15 ... Address generation circuit, 16 ... Selector, 17 ... EEPROM,
18 ... Erase circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical display location G11C 16/06 (72) Inventor Koji Maruyama 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Corporation Video Media Technology Laboratory (72) Inventor Tomoyuki Maekawa 8 Shinsita-cho, Isogo-ku, Yokohama-shi, Kanagawa Ltd. Video Media Technology Laboratory (72) Inventor Satoshi Sato 3-9 Shinbashi, Minato-ku, Tokyo Toshiba Abu E Co., Ltd.

Claims (1)

[Claims] 1. An address / data switching signal designating whether the data supplied to the bus line is an address or data represents an address input, and a read / write switching signal designating data writing or reading is in a data read state. When set, in a memory card device that outputs card status information, by applying a bus clock from the outside in the output state of the card status information,
A memory card device characterized in that a flag byte representing the internal status of the card is output instead of the card status information.