JPH05151068A - Memory card device - Google Patents

Abstract

PURPOSE:To obtain the memory card device that writes data at a speed nearly equal to the speed of data writing in page units even when used for a data series which frequently requests data writing in byte units. CONSTITUTION:This memory card device is equipped with a memory 13 which has address spaces corresponding to the pages of an EEPROM 12, a recording means 17 which records data in byte units, written in the same page of the EEPROM 12, in the memory according to addresses in byte units given to the data, a decision means 14 which decides a page change in the recording state of the recording means 17 according the addresses, and a write control means 18 which writes in a lump the contents of the memory 13 in the EEPROM 12 in page units, at a time according to the decision result of the decision means 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (electrically erasable and programmable read only memory) as a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized, and the built-in semiconductor memory is required to have a large storage capacity for recording a plurality of digital image data. For example, SR
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and has a high data writing speed and a high data reading speed, but holds the written data. Since it is necessary to store a backup battery for storing in the memory card, the storage capacity is reduced by the amount of the battery storage space and SR
There is a problem that the cost of AM itself is high and causes an economic disadvantage.

Therefore, in recent years, in order to solve the problems of the SRAM, the EEPROM has been attracting attention as a semiconductor memory used for a memory card. This EEP
The ROM has been attracting attention as a recording medium that replaces the magnetic disk, and it does not require a backup battery for holding data and can reduce the cost of the chip itself, which is a unique advantage that SRAM does not have. Therefore, development for use as a memory card has been actively carried out.

Here, when an EEPROM is used instead of an SRAM as a semiconductor memory used in a memory card, a particular problem is that the EEPROM writes data in byte units at random addresses like an ordinary SRAM. In this case, the writing speed is very slow for structural reasons. Therefore, in order to solve this problem, a page writing function has been added to the current EEPROM.

This page writing function is performed by the EEPROM.
Storage area is divided into page units consisting of several tens to hundreds of consecutive bytes, and by specifying the page, it is possible to write data collectively in page units. is there. That is, EE
Since it takes time to write data to the memory cell in the PROM, the time required to write data to the memory cell is equal to the time required to write 1 byte of data and 1 page worth of data. This is because it is equivalent to the time required to write the data all at once, and the writing speed is increased as much data can be written in the same time.

However, the conventional memory card using the EEPROM having the page writing function as the semiconductor memory is used for a data series in which a lot of continuous data writing is required, and one page is written in one writing operation. Since it is possible to write as many minutes of data as possible, the time required for writing can be shortened, but when used for a data series that requires a lot of byte-wise data writing by random access, the data writing speed remains as before. Is slow and time consuming.

[0009]

As described above, in the conventional memory card using the EEPROM having the function of writing the data in the page unit composed of a plurality of bytes,
When it is used for a data series that requires a lot of writing in byte units, the advantage that data can be written in batches in page units cannot be utilized, and there is a problem that the data writing speed is slow and time consuming as before.

Therefore, the present invention has been made in consideration of the above circumstances, and even when it is used for a data series in which a lot of data writing in byte units is required, it is performed at a speed substantially equal to the data writing speed in page units. An object is to provide an extremely good memory card device capable of writing data.

[0011]

In a memory card device according to the present invention, a storage area is divided into page units made up of a plurality of consecutive bytes, and data can be written in batches in page units by designating a page. It is intended for those having an EEPROM having a page writing function that can be performed. Then, a memory having an address space corresponding to the page of the EEPROM, a recording unit for recording the data of the byte unit written in the same page of the EEPROM in the memory based on the address of the byte unit added to the data, A discriminating means for discriminating page switching based on an address in the recording state by the recording means, and the content of the memory EEPR based on the discrimination result of the discriminating means
The OM is provided with a write control means for writing data in a page unit at a time.

[0012]

According to the above-mentioned structure, of the input data, the data to be written in the same page of the EEPROM is stored in the address space corresponding to the page of the EEPROM on the basis of the address of the byte unit added to the data. When a page change is detected, the data is stored in the EEPROM in batches on a page-by-page basis. Data can be written at a speed almost equal to the data writing speed in.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of the memory card device described in this embodiment, and FIG. 2 shows the operation timing of each part thereof. First, in FIG.
Reference numeral 11 is an input terminal to which input data is supplied. As shown in FIG. 2 (c), this input data indicates data D0 to D7 continuous for a maximum of 4 bytes and a start address 3 for recording the data D0 to D7 in an EEPROM 12 described later in byte units. Byte address data A0
~ A9 are mixed.

That is, in the example shown in FIG. 2C,
The address L specified by the 3-byte address data A0, A1, A2 is used as a start address, data D0 is recorded at this start address L, and data D is stored at address L + 1.
1 is recorded, data D2 is recorded at address L + 2, and data D3 is recorded at address L + 3. Similarly, the address data A3, A4, A
The data D4 is recorded at the address M designated by 5, and the address N designated by the address data A6, A7, A8.
The data D5 is recorded at the address N, the data D6 is recorded at the address N + 1, and the data D7 is recorded at the address N + 2.

The input data supplied to the input terminal 11 are supplied to the buffer memory 13 and the address discrimination circuit 14, respectively. Of these, the buffer memory 13 is
It has a storage capacity corresponding to one page of the EEPROM 12. Further, the address discrimination circuit 14 has the input terminal 1
A / D (address / data) discrimination signal A supplied to 5
/ D (see FIG. 2A) and the address data from the input data based on the bus clock BCK (see FIG. 2B) supplied to the input terminal 16 which is a byte-by-byte synchronous clock of the input data. Extracted and preset (PR) in the BMAC (buffer memory address counter) circuit 17
The data is sent as data and is output to the EEPROM timing generation circuit 18.

In the BMAC circuit 17, when writing data to the buffer memory 13, the bus clock BCK selected by the selector 19 by the select signal S output from the EEPROM timing generation circuit 18 is supplied to the clock input terminal CK. As a result, the bus clock BCK is sequentially counted from the preset address value, and the count value is sequentially output to the buffer memory 13 as an address. Then, the buffer memory 13
Records the input data supplied at the time when the address is sent from the BMAC circuit 17 as data.

That is, in the case of the data string shown in FIG. 2C, the address data A0, A in the A / D discrimination circuit 14 is used.
When 1 and A2 are extracted, on the buffer memory 13,
As shown in FIG. 3A, the data D0, D1, D2 and D3 are sequentially recorded on the EEPROM 12 at the positions corresponding to the addresses L, L + 1, L + 2 and L + 3, respectively.

The EEPROM timing generation circuit 18 receives the A / D signal input from the A / D discrimination circuit 14.
4-byte data D0, D based on the discrimination signal A / D
When it detects that D1, D2 and D3 have ended, BMAC
A clear (CL) signal is sent to the circuit 17 to clear the count value. Thereafter, the address determination circuit 14 determines whether the next input address data A3, A4, A5 is on the same page as the previous address data A0, A1, A2. Since the data A3, A4 and A5 are preset in the BMAC circuit 17, the data D4 is recorded in the buffer memory 13 at the position corresponding to the address M in the EEPROM 12.

After that, the EEPROM timing generation circuit 18 receives the A / D signal input from the A / D discrimination circuit 14.
When the end of the data D4 is detected based on the discrimination signal A / D, a clear (CL) signal is sent to the BMAC circuit 17 to clear the count value. Then, the address discrimination circuit 14 receives the address data A inputted next.
6, A7, A8 is the first address data A3, A4, A5
If it is the same page, the address data A6, A7, A8 is preset in the BMAC circuit 17, so that the address N, N + 1, N + 2
The data D5, D6, and D7 are sequentially recorded at the positions corresponding to, respectively.

Next, the EEPROM timing generation circuit 1
Detecting that the data D5, D6, and D7 have ended based on the A / D discrimination signal A / D input through the A / D discrimination circuit 14, 8 outputs a clear (CL) signal to the BMAC circuit 17. To clear the count value.
Then, the address determination circuit 14 determines whether the next input address data A9, A10, A11 is on the same page as the previous address data A6, A7, A8. In this case, since it is not the same page, that is, the page switching is detected, the A / D determination circuit 14 sends the information to the EEPROM timing generation circuit 18.

Then, the EEPROM timing generation circuit 18 generates an address designating a page to be written to the EEPROM 12 and a write enable signal WE at that time, whereby the buffer memory 1 is generated.
The contents of the address space for one page of 3 are EEPROM
12 pages are collectively written. In this case, EE
The PROM timing generation circuit 18 supplies the write clock WCK synchronized with the write timing of the EEPROM 12 supplied to the input terminal 20 by the select signal S to the B clock.
The selector 19 is controlled so as to be supplied to the clock input terminal CK of the MAC circuit 17, and the buffer memory 13 reads out the data with the address generated based on the write clock WCK.

Further, during this page write operation, the EEPROM timing generation circuit 18 sets the ready / busy signal RDY / BSY to the busy state BSY and outputs it to the output terminal 21 in order to prevent the data input to the input terminal 11. is doing. Furthermore, when writing data to the EEPROM 12, it is necessary to erase (erase) the data writing area in advance.
If the page to be written in the EPROM 12 has not been erased yet, the data of the page is once read out to the buffer memory 13 and erased in the buffer memory 13 and then erased by writing the page, and then the above-mentioned write operation is performed. EE to do
The PROM timing control circuit 18 controls. In addition, E
When there is only 1 byte of data in the address space of 1 page of the buffer memory 13, the EPROM timing control circuit 18 stops the page writing to the EEPROM 12 and deals with the data writing in byte units. ..

As described above, when the page writing to the EEPROM 12 is completed, the address data A9, A10, A11 of the page different from the above page is stored in the buffer memory 13 as shown in FIG. 3B. The address specified by is the start address P, and the addresses P and P +
Data D8, D9, D10 are recorded in 1 and P + 2, respectively, and the same operation is performed thereafter.

Therefore, according to the configuration of the above embodiment, even if the data to be written is input in byte units, the data to be written in the same page is stored in the buffer memory 13 having the address space for one page, and the page is stored. When the switch of is detected, E
Since the data is written in the EPROM 12, it is possible to execute the data writing at a speed substantially equal to the data writing speed in the page unit even when it is used for the data series in which the data writing in the byte unit is often requested. Become. Further, the buffer memory 13 may have an address space for two pages. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0025]

As described in detail above, according to the present invention,
To provide an extremely good memory card device capable of executing data writing at a speed substantially equal to the data writing speed in page units even when used for a data series in which data writing in byte units is often requested. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a timing chart showing the operation timing of each unit of the embodiment.

FIG. 3 is a diagram showing a data recording state of the buffer memory of the embodiment.

[Explanation of symbols]

11 ... Input terminal, 12 ... EEPROM, 13 ... Buffer memory, 14 ... Address discrimination circuit, 15, 16 ... Input terminal, 17 ... BMAC circuit, 18 ... EEPROM timing generation circuit, 19 ... Selector, 20 ... Input terminal, 21 ...
Output terminal.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical display location G11C 16/06 (72) Inventor Koji Maruyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock company Toshiba Corporation Video Media Technology Laboratory (72) Inventor Satoshi Sato 3-3-9 Shimbashi, Minato-ku, Tokyo Toshiba Abu E. Co., Ltd.

Claims (1)

[Claims] 1. A memory card provided with an EEPROM having a page writing function in which a memory area is divided into page units each including a plurality of consecutive bytes, and data can be collectively written in page units by designating a page. In the apparatus, a memory having an address space corresponding to a page of the EEPROM and a record of byte data to be written in the same page of the EEPROM in the memory based on a byte address attached to the data Means, a discriminating means for discriminating page switching based on the address in the recording state by the recording means, and a writing for collectively writing the contents of the memory into the EEPROM on a page basis based on the discrimination result of the discriminating means. A memory card device characterized by comprising a control means. Place