JPH0546459A - Memory card device - Google Patents

Abstract

PURPOSE:To improve a device so that it can be used for SRAM card write by using an EEPROM to shorten the write processing time of information data as much as possible. CONSTITUTION:The EEPROM is used as a card memory, and the memory space of this EEPROM is divided into first and second storage areas; and when information data from a system is written in the first storage area and its management data is written in the second storage area, an erase instruction of specific management data written in the second storage area from the system is discriminated to erase corresponding management data from the second storage area, and information data managed by this management data is erased from the first storage area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and more particularly to a digital image of an optical image of a photographed subject. The present invention relates to a device suitable for use in an electronic still camera device or the like that converts data and records it in a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized. The built-in semiconductor memory is required to have a large storage capacity for recording a plurality of pieces of digital image data.
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and that the data writing speed and the data reading speed are fast. On the other hand, since a backup battery for holding the written data needs to be housed in the memory card, the storage capacity is reduced as much as the battery housing space is installed, and S
There is a problem that the cost of the RAM itself is high and causes an economical disadvantage.

Therefore, at present, an EEPROM is attracting attention as a semiconductor memory that solves the problems of the SRAM. This EEPROM is promising as a recording medium that replaces the magnetic disk. In particular, it has a unique advantage that the SRAM does not have, such as a backup battery for holding data is not required and the cost of the chip itself can be reduced. For this reason, development for use as a memory card has been actively conducted. FIG. 8 shows a memory card using SRAM (SRAM card) and a memory card using EEPROM (EEPRO).
(M card) is shown in comparison with the length.

First, regarding the backup battery and the cost of the comparison items 1 and 2, as described above, the SRAM
The card requires a backup battery, has a problem that it is difficult to increase the capacity and the cost is high. On the other hand, the EEPROM card has an advantage that a backup battery is unnecessary, the capacity can be easily increased, and the cost can be reduced.

Regarding the write speed and read speed of comparison items 3 and 4, random access common to SRAM and EEPROM is performed for writing and reading data to or from a byte or bit arbitrarily designated by an address. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode, SRAM
Both writing speed and reading speed are fast,
The writing speed and the reading speed of the EEPROM are both slow. Also, in page mode,
Since the EEPROM simultaneously writes and reads a large amount of data for one page, the data write speed and data read speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM, which is the SRAM.
Is a mode that does not exist in. That is, the EEPROM
When writing new data to a storage area where data has already been written, new data cannot be written unless the previously written data is erased once. Therefore, when writing data,
This erase mode is executed. This erase mode includes, in addition to page erasing in page units described above, block erasing in block units of several Kbytes, and chip erasing mode in which all of them are collectively erased.

Further, the write verify of the comparison item 6 is also a mode peculiar to the EEPROM and is not present in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the contents written in the ROM and check whether the contents have been written correctly. This is write verification.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM and written, and then,
The contents written in the EEPROM are read out and compared with the contents in the buffer memory to determine whether they match. Then, when it is determined as a result of the write verify that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM has unique advantages not found in the SRAM, such as no backup battery, easy capacity increase, low cost, and data writing / reading in page units. .. On the other hand, the data writing speed and the data reading speed in the random access mode are slow, and there is a disadvantage that a mode such as erase mode and write verify which is not in the SRAM is required.

Therefore, as the semiconductor memory used for the memory card, the EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, the problem of needing erase mode and write verify, etc. can be solved, and it can be handled in the same manner as a memory card with built-in SRAM. As described above, that is, it is important to make various improvements in detail so that it can be used in an SRAM card-like manner. Now, let us pay attention to the erase mode when the EEPROM is used as the semiconductor memory in the memory card used in the electronic still camera device.

The memory space of the SRAM card used in the conventional electronic still camera device is divided into a header data storage area A and an information (image) data storage area B as shown in FIG. Header data is management data that mainly manages information data. As shown in FIG. 10, the information data storage area B includes a plurality of information data D1 to Dn.
Is stored. In the header data storage area A, as shown in FIG. 11, start addresses SA1 to SAn and end addresses EA1 to EAn designating the storage positions of the respective information data D1 to Dn are stored. That is, by referring to the address of the header data storage area A, the information data of the information data storage area B can be accessed.

Here, to erase the information data Dm,
Consider a case where a deletion command is input from the system. Conventional S
In the erasing routine in the case of the RAM card, as shown in FIG. 12, the start address SAm of the data Dm is set to "0" in the header data storage area A (step a), and the end address EAm thereof is set to "0". Yes (step b). That is, the data Dm in the information data storage area B is not erased because of the characteristic of the SRAM that overwriting is possible.

Therefore, the EEPROM card is replaced by the SRA.
If it is used similarly to the M card, the data Dm will remain in the information data storage area B of the EEPROM. However, since the EEPROM cannot be written unless it is erased once, the writing routine of the EEPROM card first erases the storage area of the data Dm from the information data storage area B as shown in FIG. 13 (step c ), After writing the new data Dm 'to that position (step d), the start address SAm' and end address EAm 'of the new data Dm' are written to the header data storage area A (step e, f).

As described above, in the EEPROM card, it is necessary to perform erase processing without fail when writing information data. However, when processing image data as information data as in an electronic still camera device, 1/8
Even if compressed to, the capacity is 96 [kByte], and if this block is erased, it will take about 0.3 [msec]. That is, this erasing processing time is extremely high in the writing processing time. Therefore, SR
When an EEPROM, which requires a longer writing process than AM, is used as the card memory, the writing process time to the card is further extended.

[0018]

As described above, SRA
Considering the use of the EEPROM for the memory card instead of the M, it is an important problem in practical use to improve the EEPROM card so that it can be used as an SRAM card. There is a strong demand for shortening.

Therefore, the present invention has been made in consideration of the above circumstances, and it is extremely preferable that an EEPROM is used to shorten the information data write processing time as much as possible and to improve it so that it can be used in an SRAM card-like manner. It is an object of the present invention to provide a simple memory card device.

[0020]

In a memory card device according to the present invention, a memory space is divided into a first storage area and a second storage area, and information data from a system is written in the first storage area. The EEPROM in which the management data is written in the second storage area and the erase command of the specific management data written in the second storage area from the system are determined, and the corresponding management data is stored in the second storage area. A control means is provided for erasing from the area and erasing the information data managed by the management data from the first storage area.

[0021]

According to the above configuration, the management data is erased and the information data managed by the management data is automatically erased. Therefore, the information data is erased in the writing process. This eliminates the need for the information data, thereby shortening the time required to write information data to the EEPROM, and the SRAM card-like use is possible.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 11 is a memory card main body, which is connected to an electronic still camera main body (not shown) via a connector 12 installed at one end thereof. The connector 12 is supplied with digital data DA to be written to the memory card body 11, address data AD indicating the writing location, and a bus clock BCK synchronized with the address data AD from the electronic still camera body side. Further, although not shown, processing mode designating data designating processing of writing, reading, and erasing of the card is also supplied.

Here, the digital data DA output from the electronic still camera main body side is memory card attribute information, various information peculiar to each image data, and memory management information such as date information and information on the number of shootable images. Header data H
D and image data PD (including sound) corresponding to the subject
And are included. Of these, the header data HD has a small total data amount of about 16 Kbytes, and has a property that it is often necessary to rewrite in byte units such as date information and information about the number of shootable images. ing. Further, the image data PD has a very large amount of data for one image, and has the property of being entirely sequential.

The digital data DA supplied to the connector 12 is once taken into the buffer memory 13 and recorded. At this time, the timing of fetching the digital data DA of the buffer memory 13 is as follows.
It is controlled by the address data output from 4. The address generation circuit 14 counts the clock CK selected by the selector 15 and generates address data for the buffer memory 13.

The selector 15 outputs from the data processing control circuit 16 either one of the bus clock BCK supplied from the electronic still camera main body side through the connector 12 and the read clock YCK supplied from the data processing control circuit 16. The selected signal SEL is selectively output. That is, the bus clock BCK is selected when the digital data DA of the buffer memory 13 is taken in, and the read clock YCK is derived to the address generation circuit 14 as the clock CK when reading it.

The data processing control circuit 16 switches to the designated processing mode based on the processing mode designation data supplied through the connector 12. The address data AD is supplied to the data processing control circuit 16,
It is determined whether the header address data HAD or the image address data PAD. The buffer memory 13 has a storage capacity (16 Kbytes or more) capable of storing all the header data HD. The digital data DA taken into the buffer memory 13 is read from the buffer memory 13 and written into the EEPROM 17 under the control of the data processing control circuit 16 which will be described later.

This EEPROM 17 has a large storage capacity of 4 Mbits or more, cannot write or erase data in byte units, and can perform batch erasing or erasing in block units of several Kbytes, and several hundreds. Data can be written and read in page units of bytes.

The memory space area of the EEPROM 17 is a header data HD storage area A as shown in FIG.
And the image data PD storage area B. The spatial configuration is in cluster units. In FIG. 2, clusters 0 and 1 are the header data HD storage area A, and clusters 2 to N are the image data PD storage area B. The cluster structure consists of erase block units as shown in FIG.
It is composed of M (fixed value of 1 or more) blocks.

Data is handled in packet units and is composed of L (arbitrary value of 1 or more) clusters as shown in FIG. In FIG. 2, packets 0 and 1 are header data composed of clusters 0 and 1, respectively, packet 2 is image data composed of clusters 2, 3, 4, and 5, packet 3 is
Is image data consisting of clusters 6, 8 and 9, packet 4
Is image data including clusters 7, 10, and 11.

A part of the header data storage area A is shown in FIG. This area has a directory information area and a MAT (memory allocation table) area. The start cluster number of each packet is managed in the directory information area, and the MAT of each cluster is managed in the MAT area. A cluster number to be connected next is written in the MAT area. At this time, a value such as FF _H is used for ending the cluster chain, and a value such as 00 _H is used for not using the cluster.

Taking the packet 3 of FIG. 2 as an example, the start cluster number is 6, the MAT of the cluster 6 is 8, the MAT of the cluster 8 is 9, and the MAT of the cluster 9 is F.
It becomes F _H. This causes packet 3 to be cluster 6,
It can be seen that it is configured in the order of 8 and 9.

In the above structure, the operation control in the card is performed by the data processing control circuit 16. First, the processing mode designation data sent from the electronic still camera body side designates the writing process, and the header data HD
Also, the operation of writing the image data PD in the EEPROM 17 will be described.

When the data processing control circuit 16 determines that the input address data AD is the header address data HAD, the out enable data OE is activated to the EEPROM 17 (for example, H level).
And the header data HD of the EEPROM 17
All the header data HD stored in the EEPROM 17 is generated by generating the address data AD that specifies all the storage areas.
Operates so as to be read page by page.

Next, the data processing control circuit 16 sets the write enable data WE to the active state (for example, H level) for the buffer memory 13 and controls the select signal SEL to generate the read clock YCK generated by itself. However, the selector 15 is switched so as to be led to the address generation circuit 14. Therefore, all the header data HD read from the EEPROM 17 is written in the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK.

After that, in a state where all the header data HD are written in the buffer memory 13, the data processing control circuit 16 determines, based on the header address data HAD.
The address generation circuit 14 generates the set address data SA that specifies the bytes of the header data HD to be rewritten.
And the address set data AS for setting the set address data SA in the address generation circuit 14 to the address generation circuit 14.

Then, the address generation circuit 14 generates address data from the set address data SA set based on the address set data AS, and outputs it to the buffer memory 13. At this time, the data processing control circuit 16 activates the write enable data WE to the buffer memory 13, so that the contents of the byte designated by the input address data of the buffer memory 13 are transferred via the connector 12. It is rewritten to the new header data HD that has been input.

When the rewriting of the header data HD in bytes is completed in the buffer memory 13, the data processing control circuit 16 generates the clock YCK generated by itself.
Selector 1 so that the
5 and controls the out enable data OE to the buffer memory 13 in the active state. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 14 based on the clock YCK.
The header data HD is sequentially read from 3.

At this time, the data processing control circuit 16 causes the E
The write enable data WE is activated for the EPROM 17, and the address data AD designating the entire header data HD storage area of the EEPROM 17 is generated. Therefore, all the header data HD after the rewriting stored in the buffer memory 13 is
The data is transferred to the ROM 17 and written in the header data HD storage area in page units.

After that, with all the header data HD written in the EEPROM 17, the data processing control circuit 16 activates the out enable data OE to the EEPROM 17 and specifies all the header data HD storage areas. Address data AD is output, the written header data HD is read, and write verification is executed to determine whether the header data HD matches the header data HD recorded in the buffer memory 13.

If the header data HD read from the EEPROM 17 and the header data HD recorded in the buffer memory 13 do not match, the header data HD is read from the buffer memory 13 to the EEPROM 17 again.
Is transferred and written, and this operation is
This is repeated until the header data HD read from M17 and the header data HD recorded in the buffer memory 13 completely match, and the header data HD is written there.

In the data processing control circuit 16, the input address data AD is the image address data PA.
When it is determined that the data is D, the image address data PAD is output to the EEPROM 18 and the write enable data WE is activated. next,
The data processing control circuit 16 controls the select signal SEL to switch the selector 15 so that the clock YCK generated by itself is derived to the address generation circuit 14.

Therefore, the image data PD is sequentially read from the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK, and written in the EEPROM 17 page by page.

After that, the image data P is stored in the EEPROM 17.
With D written, the data processing control circuit 16
Out enable data O for the EEPROM 17
When E is set to the active state, the image address data PAD is output, the written image data PD is read out, and it is determined whether or not it matches the image data PD recorded in the buffer memory 13. Perform verification.

If the image data PD read from the EEPROM 17 and the image data PD recorded in the buffer memory 13 do not match, the image data PD is transferred from the buffer memory 13 to the EEPROM 17 again to perform the writing operation. Perform this operation, EEPRO
This is repeated until the image data PD read from M17 and the image data PD recorded in the buffer memory 13 completely match, and the image data PD is written there.

Next, in the case of reading the header data HD and the image data PD from the EEPROM 17 to the outside of the memory card body 11 when the processing mode designation data sent from the electronic still camera body side designates the reading process. The operation will be described.

First, the address at which the data to be read from the electronic still camera body side is recorded via the connector 12 is designated. Then, the specified address is supplied to the data processing control circuit 16, and it is determined whether the address data HAD for the header or the address data PAD for the image.

Thereafter, the data processing control circuit 16 activates the out enable data OE and the write enable data WE to the EEPROM 17 and the buffer memory 13 based on the determination result, and
The clock YCK generated by itself is the address generation circuit 1
4 switches the selector 15 so that the EEP
The header data HD and the image data PD are read from the ROM 17 in page units and written in the buffer memory 13.

Then, the data processing control circuit 16 switches the selector 15 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 14, and the bus clock BCK.
The address data generated by the address generation circuit 14 based on CK is read out from the buffer memory 13 and led out to the electronic still camera main body via the connector 12, where the header data HD and the image data PD are stored.
Is read.

By the way, when the image data read by the above-mentioned reading process is reproduced on, for example, a television receiver, and the image is unnecessary, if the unnecessary image data is erased, it is stored in the area. Rewriting is possible. Therefore, an erase processing mode is added to the electronic still camera. An arbitrary packet M is sent from the electronic still camera body side to a card in which data has already been written.
The operation of erasing will be described.

On the electronic still camera body side, EEP
Assuming that the ROM card is handled without being distinguished from the SRAM card, erase processing mode designating data is supplied from the electronic still camera body side, and address data AD and digital data for erasing the header data of the packet M are supplied. DA is supplied. Specifically, as shown in FIG. 6, the start cluster is changed (for example, 00 _H ) through the data processing control circuit 16 (step g), and the MAT of the cluster forming the packet M is not used (for example, 00 _H). ) (Step h). Considering the case of packet 3 shown in FIG. 2, the start cluster of packet 3 is 00 _H and the MAT of clusters 6, 8, and 9 is 0.
It is only rewritten to 0 _H.

Therefore, when the erase processing mode is designated, the data processing control circuit 16 executes the processing shown in FIG. 7 following the above processing. That is, the MA of the cluster
It is determined whether or not T has been rewritten as unused (step i). If it has not been rewritten (N), the processing is terminated as it is, and if it has been rewritten (Y), the cluster is deleted. The constituent blocks are erased in block units (step j). Then, it is determined whether or not the last block in the cluster has been erased (step k). If not erased (N), the process returns to step j, and if erased (Y)
, It is determined whether or not the MATs of the other clusters have been rewritten as unused (step l). If they have been rewritten (Y), the process returns to step j, and if they have not been rewritten, (N) processing is performed. To finish.

Therefore, according to the configuration of the above embodiment, when there is a rewriting request for the header data HD having a property that the data amount is small and the data is rewritten in byte units, all the headers are read from the EEPROM 17. The data HD is read to the buffer memory 13, and the header data HD is rewritten byte by byte in the buffer memory 13 by random access.
Since all the header data HD of No. 3 is written to the EEPROM 17 in page units, the EEPR having a large storage capacity in which writing and reading of data in byte units cannot be performed.
Even using the OM 17, it is possible to easily write and read data in byte units.

Moreover, since the data transfer between the electronic still camera main body and the memory card main body 11 is always performed via the buffer memory 13, the data writing speed and the data reading speed are improved, and it is used for SRAM card-like. Will be able to. Also,
The write verify unique to the EEPROM 17 is also provided in the buffer memory 1 provided inside the memory card body 11.
3 is used, the memory card main body 11 can be used just like an SRAM card.

Further, in the erase processing mode, when the header data is rewritten to unused by the erase processing on the electronic still camera body side, the information data is automatically erased on the card side. Since it is not necessary to erase the information data when writing, the writing processing time can be significantly shortened,
On the electronic still camera body side, the EEPROM card is SRA
It can be used without distinguishing it from the M card. The present invention is not limited to the above embodiment,
In addition, various modifications can be made without departing from the scope of the invention.

[0056]

As described in detail above, according to the present invention,
It is possible to provide an extremely good memory card device which has been improved so that it can be used in an SRAM card-like manner by shortening the information data write processing time as much as possible by using the EEPROM.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration for an electronic still camera as an embodiment of a memory card device according to the present invention.

FIG. 2 is a configuration diagram showing a memory space configuration of an EEPROM used in the embodiment.

FIG. 3 is a configuration diagram showing a cluster structure in a memory of the EEPROM.

FIG. 4 is a configuration diagram showing a packet structure stored in the EEPROM.

FIG. 5 is a configuration diagram showing a part of a header data storage area in the memory space configuration.

FIG. 6 is a flowchart showing an erasing routine on the electronic still camera body side for the EEPROM of the embodiment.

FIG. 7 is a flowchart showing a card-side erasing routine for the EEPROM of the embodiment.

FIG. 8 is a diagram showing the lengths of an SRAM and an EEPROM in comparison.

FIG. 9 is a configuration diagram showing a space area of a card memory.

FIG. 10 is a configuration diagram showing a configuration of an information data storage area in the space area.

FIG. 11 is a configuration diagram showing a part of a header data storage area in the space area.

FIG. 12 is a flowchart showing an erasing routine on the electronic still camera body side with respect to the card memory.

FIG. 13 is a flowchart showing a conventional write routine on the card side when an EEPROM is used as the card memory.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Buffer memory, 14 ... Address generation circuit, 15 ... Selector, 16 ... Data processing control circuit, 17 ... EEPROM,
A ... Header data storage area, B ... Information data storage area.

Claims (2)

[Claims] 1. An EEPROM in which a memory space is divided into a first storage area and a second storage area, information data from a system is written in the first storage area, and management data thereof is written in the second storage area. , The second from the system
Of the specific management data written in the first storage area is determined, the corresponding management data is deleted from the second storage area, and the information data managed by the management data is deleted from the first storage area. A memory card device comprising a control means for erasing from a region. 2. The memory card device according to claim 1, wherein the control unit erases the information data in block units at the time of writing.