JPH0546490A - Memory card device - Google Patents

Abstract

PURPOSE:To unnecessitate securing an address table area by providing an error flag write means, a data write substitute means, an address write means, and a data read means. CONSTITUTION:The memory card is provided with an EEPROM 17, error detection means, error flag write means, and data write means. It also provided with an address write means writing a substitute destination address to be replaced by the data substitute means on a page with an error and a data read means 16 discriminating an error generated page while referring to an error flag area, discriminating a substitute destination address by reading a byte data on the page, and reading data from the substitute page based on the discriminated address. Especially, the address write means writes the substitute destination address on a plurality of bytes in the error generated page, and the data read means 16 reads data from a plurality of bytes on the error generated page, discriminating the substitute destination address by adopting the decision by majority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and more particularly to a digital image of an optical image of a photographed subject. The present invention relates to a device suitable for use in an electronic still camera device or the like that converts data and records it in a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized. The built-in semiconductor memory is required to have a large storage capacity for recording a plurality of pieces of digital image data.
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and that the data writing speed and the data reading speed are fast. On the other hand, since a backup battery for holding the written data needs to be housed in the memory card, the storage capacity is reduced as much as the battery housing space is installed, and S
There is a problem that the cost of the RAM itself is high and causes an economical disadvantage.

Therefore, at present, an EEPROM is attracting attention as a semiconductor memory that solves the problems of the SRAM. This EEPROM is promising as a recording medium that replaces the magnetic disk. In particular, it has a unique advantage that the SRAM does not have, such as a backup battery for holding data is not required and the cost of the chip itself can be reduced. For this reason, development for use as a memory card has been actively conducted. FIG. 4 shows a memory card using SRAM (SRAM card) and a memory card using EEPROM (EEPRO).
(M card) is shown in comparison with the length.

First, regarding the backup battery and the cost of the comparison items 1 and 2, as described above, the SRAM
The card requires a backup battery, has a problem that it is difficult to increase the capacity and the cost is high. On the other hand, the EEPROM card has an advantage that a backup battery is unnecessary, the capacity can be easily increased, and the cost can be reduced.

Regarding the write speed and read speed of comparison items 3 and 4, random access common to SRAM and EEPROM is performed for writing and reading data to or from a byte or bit arbitrarily designated by an address. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode, SRAM
Both writing speed and reading speed are fast,
The writing speed and the reading speed of the EEPROM are both slow. Also, in page mode,
Since the EEPROM simultaneously writes and reads a large amount of data for one page, the data write speed and data read speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM, which is the SRAM.
Is a mode that does not exist in. That is, the EEPROM
When writing new data to a storage area where data has already been written, new data cannot be written unless the previously written data is erased once. Therefore, when writing data,
This erase mode is executed. This erase mode includes, in addition to page erasing in page units described above, block erasing in block units of several Kbytes, and chip erasing mode in which all of them are collectively erased.

Further, the write verify of the comparison item 6 is also a mode peculiar to the EEPROM and is not present in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the contents written in the ROM and check whether the contents have been written correctly. This is write verification.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM and written, and then,
The contents written in the EEPROM are read out and compared with the contents in the buffer memory to determine whether they match. Then, when it is determined as a result of the write verify that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM has unique advantages not found in the SRAM, such as no backup battery, easy capacity increase, low cost, and data writing / reading in page units. .. On the other hand, the data writing speed and the data reading speed in the random access mode are slow, and there is a disadvantage that a mode such as erase mode and write verify which is not in the SRAM is required.

Therefore, as the semiconductor memory used for the memory card, the EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, the problem of needing erase mode and write verify, etc. can be solved, and it can be handled in the same manner as a memory card with built-in SRAM. As described above, that is, it is important to make various improvements in detail so that it can be used in an SRAM card-like manner. The points to be improved are as follows.

That is, in particular, when recording information data such as computer data and image data, a header data storage area for recording data attributes is essential in addition to the information data storage area. The number of times of rewriting of the header data storage area is frequent, and reliability is particularly required. Therefore, it is necessary to perform error detection, correction, etc. by the chip itself or software. In any case, the error can be detected by polling at the time of writing, but at the time of reading later, it is necessary to deal with the judgment as to whether or not there is an error and the processing for the error, for example, replacement.

An example in which a byte readable / writable EEPROM is used in the header data storage area will be described with reference to FIG. The error shall occur randomly in bytes.

FIG. 5 shows the structure of the header data storage area. The whole is 8K bytes (8192 bytes),
32 bytes are divided into one page and divided into 256 pages. An error flag (1 bit) indicating whether or not there is an error is written in each page, and in order to replace the page with another page when an error occurs, the address of the replacement destination is written there. become.

In this case, since 1 byte is required for each page as an address, 2 bytes are used for each page together with the error flag. That is, since there are 256 pages in all, 512 bytes (16 pages) as a whole
Minute address table is required.

The area required for this address table is
Of course, since the original header data cannot be written, the area is reduced by about 6%. Also, in this example, one page has 32 bytes, but 16 pages
If it is a byte structure, double 1024 bytes are required,
There is a problem that the area that cannot be used becomes large and the header data area that should be used is squeezed.

Although it is necessary to prepare an area to be replaced in advance, if this area is reduced, it is conceivable that frequently accessed pages will be replaced many times and eventually there will be no replacement destination. In this case, although the large-capacity information data storage area can still be rewritten, the small-capacity header data storage area cannot be rewritten, so that the whole becomes unusable.

[0020]

As described above, SRA
Considering the use of the EEPROM for the memory card instead of the M, it is an important problem in practical use to improve the EEPROM card so that it can be used as an SRAM card. In particular, in order to replace the data in the error area of the EEPROM, the address table area must be secured, which reduces the original data area, limits the recorded data, and shortens the overall lifespan. Is strongly requested.

Therefore, the present invention has been made in consideration of the above circumstances, and it is not necessary to secure an address table area when replacing data in an error occurrence area by using an EEPROM, and it can be used in an SRAM card-like manner. It is an object of the present invention to provide an extremely good memory card device which has been improved.

[0022]

Means for Solving the Problems A memory card according to the present invention
The device can write and read in byte units,
Divided into multiple pages in units of several bytes
Detects whether there is an error in the EEPROM and each page.
Error detection means and a specific page of the multiple pages.
Page as an error flag area
An error flag document that records the error flag that indicates the presence or absence of raw
Writing means and writing of the page in which the error occurred
Write data by replacing data with free pages
Replacement means and the data on the page where the error occurred
Address for writing the replacement address to be replaced by the replacement means
Refer to the error writing area and the error flag area
Determine the page in which the error occurred and the byte data of that page
Is read to determine the replacement destination address, and the determined address
Read data from replacement page based on data read
And means.

In particular, the address writing means writes a replacement destination address in a plurality of bytes of the error occurrence page, and the data reading means reads data from a plurality of bytes of the error occurrence page and determines a replacement destination address by a majority decision. It is characterized by doing so.

[0024]

With the above structure, the EE is divided into a plurality of pages.
For the PROM, detect whether there is an error for each page,
With a specific page as the error flag area, an error flag indicating whether or not an error has occurred on each page is recorded, the write data on the error page is written by replacing it with a blank page, and the replacement destination address is written on the error page, At the time of reading, the error flag area is referred to determine the page in which the error occurred, the byte data of the page is read to determine the replacement destination address, and the data is read from the replacement page based on the determined address.

That is, since each error occurrence page can be identified only by referring to the error flag area, and the area for obtaining the replacement destination address is the error occurrence page, it is not necessary to reserve that area.

In particular, the replacement destination address is written in all the bytes of the error occurrence page or a part thereof, the data is read from all the bytes of the error occurrence page or a part thereof, and the replacement destination address is discriminated by the majority decision. The destination address is accurately obtained, and the reliability of data replacement when an error occurs is not impaired.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 11 is a memory card main body, which is connected to an electronic still camera main body (not shown) via a connector 12 installed at one end thereof. The connector 12 is supplied with digital data DA to be written to the memory card body 11, address data AD indicating the writing location, and a bus clock BCK synchronized with the address data AD from the electronic still camera body side. Further, although not shown, processing mode designating data designating processing of writing, reading, and erasing of the card is also supplied.

Here, the digital data DA output from the electronic still camera main body side includes memory card attribute information, various information peculiar to each image data, date information, and memory management information such as the number of recordable images. Header data H
D and image data PD (including sound) corresponding to the subject
And are included. Of these, the header data HD has a small total data amount of about 16 Kbytes, and has a property that it is often necessary to rewrite in byte units such as date information and information about the number of shootable images. ing. Further, the image data PD has a very large amount of data for one image, and has the property of being entirely sequential.

The digital data DA supplied to the connector 12 is once taken into the buffer memory 13 and recorded. At this time, the timing of fetching the digital data DA of the buffer memory 13 is as follows.
It is controlled by the address data output from 4. The address generation circuit 14 counts the clock CK selected by the selector 15 and generates address data for the buffer memory 13.

The selector 15 outputs from the data processing control circuit 16 one of the bus clock BCK supplied from the electronic still camera body side through the connector 12 and the read clock YCK supplied from the data processing control circuit 16. The selected signal SEL is selectively output. That is, the bus clock BCK is selected when the digital data DA of the buffer memory 13 is taken in, and the read clock YCK is derived to the address generation circuit 14 as the clock CK when reading it.

The data processing control circuit 16 switches to the designated processing mode based on the processing mode designation data supplied through the connector 12. The address data AD is supplied to the data processing control circuit 16,
It is determined whether the header address data HAD or the image address data PAD. The buffer memory 13 has a storage capacity (16 Kbytes or more) capable of storing all the header data HD. The digital data DA taken into the buffer memory 13 is read from the buffer memory 13 and written into the EEPROM 17 under the control of the data processing control circuit 16 which will be described later.

This EEPROM 17 has a large storage capacity of 4 Mbits or more, and cannot write or erase data in byte units, and can perform batch erasing or erasing in block units of several Kbytes, and several hundreds of bytes. Data can be written and read in page units of bytes.

The memory space area of the EEPROM 17 is divided into a header data HD storage area and an image data PD storage area. Of these, the header data HD storage area is configured as shown in FIG.
It is divided into 2 bytes, page capacity 32 bytes, and page number 256.

The error flag for 256 pages requires 256 bits = 32 bytes. This corresponds to one page. Here, the last page is reserved as the error flag area. FIG. 2B shows an enlarged error flag area. In the initial state, “0” is written in all bits as an error flag of each page, but when an error occurs in a page, the bit corresponding to that page can be rewritten to “1”. Further, the data of the error occurrence page is replaced with a predetermined page. At this time, as shown in an enlarged view of FIG. 2C, the address of the replacement destination page is written in each byte of the error occurrence page. ..

In the above structure, the operation control in the card is performed by the data processing control circuit 16. First, the processing mode designation data sent from the electronic still camera body side designates the writing process, and the header data HD
Also, the operation of writing the image data PD in the EEPROM 17 will be described.

When the data processing control circuit 16 determines that the input address data AD is the header address data HAD, the out enable data OE is activated to the EEPROM 17 (for example, H level).
And the header data HD of the EEPROM 17
All the header data HD stored in the EEPROM 17 is generated by generating the address data AD that specifies all the storage areas.
Operates so as to be read page by page.

Next, the data processing control circuit 16 sets the write enable data WE to the buffer memory 13 in the active state (for example, H level) and controls the select signal SEL to generate the read clock YCK generated by itself. However, the selector 15 is switched so as to be led to the address generation circuit 14. Therefore, all the header data HD read from the EEPROM 17 is written in the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK.

After that, in a state in which all the header data HD are written in the buffer memory 13, the data processing control circuit 16 determines, based on the header address data HAD.
The address generation circuit 14 generates the set address data SA that specifies the bytes of the header data HD to be rewritten.
And the address set data AS for setting the set address data SA in the address generation circuit 14 to the address generation circuit 14.

Then, the address generation circuit 14 generates address data from the set address data SA set based on the address set data AS, and outputs it to the buffer memory 13. At this time, the data processing control circuit 16 activates the write enable data WE to the buffer memory 13, so that the contents of the byte designated by the input address data of the buffer memory 13 are transferred via the connector 12. It is rewritten to the new header data HD that has been input.

When the rewriting of the header data HD in bytes is completed in the buffer memory 13, the data processing control circuit 16 generates the clock YCK generated by itself.
Selector 1 so that the
5 and controls the out enable data OE to the buffer memory 13 in the active state. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 14 based on the clock YCK.
The header data HD is sequentially read from 3.

At this time, the data processing control circuit 16 makes the E
The write enable data WE is activated for the EPROM 17, and the address data AD designating the entire header data HD storage area of the EEPROM 17 is generated. Therefore, all the header data HD after the rewriting stored in the buffer memory 13 is
The data is transferred to the ROM 17 and written in the header data HD storage area in page units.

After that, with all the header data HD written in the EEPROM 17, the data processing control circuit 16 sets the out enable data OE to the EEPROM 17 in the active state and specifies all the header data HD storage areas. Address data AD is output, the written header data HD is read, and write verification is executed to determine whether the header data HD matches the header data HD recorded in the buffer memory 13.

If the header data HD read from the EEPROM 17 and the header data HD recorded in the buffer memory 13 do not match, the header data HD is read from the buffer memory 13 to the EEPROM 17 again.
Is transferred and written, and this operation is
This is repeated until the header data HD read from M17 and the header data HD recorded in the buffer memory 13 completely match, and the header data HD is written there.

Here, in the data processing control circuit 16, the input address data AD is the image address data PA.
When it is determined that the data is D, the image address data PAD is output to the EEPROM 18 and the write enable data WE is activated. next,
The data processing control circuit 16 controls the select signal SEL to switch the selector 15 so that the clock YCK generated by itself is derived to the address generation circuit 14.

Therefore, the image data PD is sequentially read from the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK, and written in the EEPROM 17 page by page.

After that, the EEPROM 17 stores the image data P
With D written, the data processing control circuit 16
Out enable data O for the EEPROM 17
When E is set to the active state, the image address data PAD is output, the written image data PD is read out, and it is determined whether or not it matches the image data PD recorded in the buffer memory 13. Perform verification.

If the image data PD read from the EEPROM 17 and the image data PD recorded in the buffer memory 13 do not match, the image data PD is transferred from the buffer memory 13 to the EEPROM 17 again to perform the writing operation. Perform this operation, EEPRO
This is repeated until the image data PD read from M17 and the image data PD recorded in the buffer memory 13 completely match, and the image data PD is written there.

Next, when the processing mode designation data sent from the electronic still camera body side designates the reading process, the header data HD and the image data PD are read from the EEPROM 17 to the outside of the memory card body 11. The operation will be described.

First, the address where the data to be read from the electronic still camera main body side is specified via the connector 12 is designated. Then, the specified address is supplied to the data processing control circuit 16, and it is determined whether the address data HAD for the header or the address data PAD for the image.

After that, the data processing control circuit 16 activates the out enable data OE and the write enable data WE to the EEPROM 17 and the buffer memory 13 based on the determination result, and
The clock YCK generated by itself is the address generation circuit 1
4 switches the selector 15 so that the EEP
The header data HD and the image data PD are read from the ROM 17 in page units and written in the buffer memory 13.

Then, the data processing control circuit 16 switches the selector 15 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 14, and the bus clock BCK.
The address data generated by the address generation circuit 14 based on CK is read out from the buffer memory 13 and led out to the electronic still camera main body via the connector 12, where the header data HD and the image data PD are stored.
Is read. The operation of the EEPROM 17 when an error occurs in a page in the header data HD storage area will be described with reference to FIG.

When the data processing control circuit 16 determines the designation (Y) of the writing process (step a), it polls at the time of writing the data (step b) and determines whether an error has occurred (step). c). If no error has occurred, the (N) writing process ends.
When an error occurs (Y), for example, when an error occurs on the second page as shown in FIG. 2A, the same figure (b)
As described above, the bit corresponding to the second page in the error flag area is rewritten to "1" and an error flag is set (step d).

Here, if an error occurs in a certain page, the flag is held at "1". Therefore, the number of times of rewriting in the error flag area is 8 at the maximum, which is far below the guaranteed number (10,000 times or more) in general, and it can be considered that no error occurs in this area.

Next, a free replacement page is searched for, and its address (20th in FIG. 2) is searched as shown in FIG. 2C.
Write page 0 to all bytes (32 bytes) of page 2 (step e). In this example, the address is 1 byte, but the same applies to a 2-byte address. At this time, of course, the byte in which the error occurred cannot be written, but this is ignored.

Finally, returning to step b, the header data that should have been initially written is written in the replacement destination page (the 200th page). At this time, if it is determined in step c that an error has occurred again, steps d and e are repeated,
Perform replacement processing. If no error is detected, the writing process and the error page replacement process are terminated.

Further, when the data processing control circuit 16 determines the designation (N) of the reading process (step a), it first refers to the error flag area, and if the flag of the reading page is "0" (N), The data of the page is read (step i), and the reading process is completed. If the read page flag is "1" (Y), it is determined that there is an error page, and the replacement destination address of all bytes written in the error page is read (step g) and compared. The address is determined by majority (step h). Only a part of the data may be read out here. Finally, based on the determined replacement destination address, the header data is read from the replacement destination page (step i), and the reading process ends.

Therefore, according to the configuration of the above embodiment, when there is a rewriting request for the header data HD having a property that the data amount is small and the data is rewritten in byte units, all the headers are read from the EEPROM 17. The data HD is read to the buffer memory 13, and the header data HD is rewritten byte by byte in the buffer memory 13 by random access.
Since all the header data HD of No. 3 is written to the EEPROM 17 in page units, the EEPR having a large storage capacity in which writing and reading of data in byte units cannot be performed.
Even using the OM 17, it is possible to easily write and read data in byte units.

Moreover, since data transfer between the electronic still camera main body and the memory card main body 11 is always performed via the buffer memory 13, the data writing speed and the data reading speed are improved, and it is used for SRAM card-like. Will be able to. Also,
The write verify unique to the EEPROM 17 is also provided in the buffer memory 1 provided inside the memory card body 11.
3 is used, the memory card main body 11 can be used just like an SRAM card.

Further, the area required for replacing the data of the error page is only one page (32 bytes) for storing the error flag, and it is not necessary to reserve another address table area. 15 pages (480 bytes) can be reduced compared to the conventional case shown, and the ratio to the whole can be limited to about 0.4%. This reduced area can be used as an original header data write area, and can also be used as a replacement page, for example. As a result, it is possible to solve the problem that the replacement of the accessed page is reduced and the small-capacity header data storage area cannot be rewritten, so that the entire area becomes unusable.

The numerical values used in the above description are merely examples, and the present invention is not limited to these. Further, the present invention is suitable for a medium such as a memory card whose total capacity is limited, but can be applied to other media. In addition, various modifications can be made without departing from the scope of the invention.

[0062]

As described in detail above, according to the present invention,
By using the EEPROM, it is not necessary to secure the address table area when replacing the data in the error occurrence area, and it is possible to provide a very good memory card device improved so that it can be used for SRAM card-like.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration for an electronic still camera as an embodiment of a memory card device according to the present invention.

FIG. 2 is a configuration diagram showing a configuration of a header data storage area of an EEPROM used in the embodiment.

FIG. 3 is a flowchart for explaining an operation when an error occurs in the embodiment.

FIG. 4 is a diagram showing the lengths of an SRAM and an EEPROM in comparison.

FIG. 5 is a configuration diagram showing a configuration of a header data storage area adopted in a conventional EEPROM card.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Buffer memory, 14 ... Address generating circuit, 15 ... Selector, 16 ... Data processing control circuit, 17 ... EEPROM.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G11C 29/00 302 9288-5L

Claims (2)

[Claims] 1. An EEPROM capable of writing and reading in byte units and divided into a plurality of pages in units composed of several bytes, an error detecting unit for detecting the presence or absence of an error for each page, and the plurality of pages. Among them, an error flag writing unit that records an error flag indicating whether or not an error has occurred in each page by using a specific page as an error flag area, and data to be written by replacing the write data of the page in which the error has occurred with a blank page Write replacement means, address writing means for writing the replacement destination address to be replaced by the data replacement means on the page where the error has occurred, and the error flag area to determine the error page, and the byte data of the page To determine the replacement destination address, and based on the determined address, replace A memory card device, comprising: a data reading means for reading data from a page. 2. The address writing means writes a replacement destination address in a plurality of bytes of the error occurrence page, and the data reading means reads data from a plurality of bytes of the error occurrence page and determines a replacement destination address by a majority decision. The memory card device according to claim 1, wherein