JPH06139131A - Memory card device - Google Patents

Abstract

PURPOSE:To easily discriminate whether a host apparatus is initialized or not by detecting that the contents of a managing data storing area is changed from a state having data in at least one of respective reference areas to a state having no data in all the reference areas to-judge initialization. CONSTITUTION:An EEPROM 19 is connected to a microcomputer 16, header data are written in the EEPROM 19 and normal data are written in an EEPROM 13. A function that the contents of the storage area 19 for an MAT area corresponding to a cluster are rewritten to '00h' when the cluster in the ROM 13 is erased is utilized. Thereby the microcomputer 16 can easily judge the initialization of the host apparatus by detecting a change from a state in which at least one of all the MAT area storing areas 19 is not '00h' to a state indicating that all the storing areas 19 are '00h'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a memory card device using an EEPROM (electrically erasable and programmable read only memory) as a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized, and the built-in semiconductor memory is required to have a large storage capacity for recording a plurality of digital image data. For example, SR
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and has a high data writing speed and a high data reading speed, but holds the written data. Since it is necessary to store a backup battery for storing in the memory card, the storage capacity is reduced by the amount of the battery storage space and SR
There is a problem that the cost of AM itself is high and causes an economic disadvantage.

Therefore, in order to solve the problems of the SRAM, the EEPROM is now attracting attention as a semiconductor memory used for a memory card. This EEP
The ROM is attracting attention as a recording medium that replaces the magnetic disk. It does not require a backup battery for holding data and can reduce the cost of the chip itself, which is a unique advantage that SRAM does not have. Therefore, it has been actively developed for use as a memory card.

Here, FIG. 6 shows a comparison between the length of a memory card using an SRAM (SRAM card) and the length of a memory card using an EEPROM (EEPROM card). First, regarding the backup battery and the cost of the comparison items 1 and 2, as already described above, the SRAM card needs the backup battery and the cost is high, whereas the EEPROM card does not need the backup battery and the cost is high. Also has the advantage that it can be lowered.

Next, regarding the writing speed and the reading speed of the comparison items 3 and 4, random access common to the SRAM and the EEPROM for writing and reading data to or from a byte or bit arbitrarily designated by an address is performed. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode,
The SRAM has both a high writing speed and a high reading speed, and the EEPROM has a low writing speed and a low reading speed. In addition, EEPROM
In the page mode, since a large amount of data for one page is written and read all at once, the data write speed and the data read speed are faster than in the random access mode.

Further, the erase mode of the comparison item 5 is a mode peculiar to the EEPROM, and the SRAM is
Is a mode that does not exist in. That is, the EEPROM
When writing new data to an area where data has already been written, that is, when rewriting data, new data cannot be written unless the previously written data is erased once. The erase mode is executed when the rewriting is performed. The erase mode includes a chip erase that erases all the stored contents of the EEPROM at once and a block erase that erases the stored contents in units of blocks (several Kbytes) made up of a plurality of pages.

Also, the write verify of the comparison item 6 is a mode peculiar to the EEPROM and a mode not existing in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the written contents of the ROM and check whether or not they have been written correctly, which is the write verification.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM, and is written.
The written contents of the EEPROM are read and compared with the contents of the buffer memory to determine whether they match. Then, when it is determined as a result of the write verification that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM does not require a backup battery, is low in cost, and can write and read data in page units. It has unique advantages not found in SRAM. There is also a disadvantage that the writing speed and the reading speed are slow and that a mode such as an erase mode and a write verify which is not in the SRAM is required.

Therefore, as a semiconductor memory used for a memory card, EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, and the problem of needing erase mode and write verify, etc. are solved, and handling equivalent to that of a memory card with built-in SRAM can be performed. As described above, that is, it is important to make various improvements in details so that the card can be used in an SRAM card-like manner.

Therefore, the memory card using the EEPROM is provided with a buffer memory and a microcomputer inside, and when writing data, the input data is temporarily stored in the buffer memory under the control of the microcomputer, and the buffer memory and the EEPROM are combined. Write verify is performed between them, and when rewriting data, the EEPR is controlled under the control of the microcomputer.
By automatically erasing the data rewriting area of the OM, and irrespective of the host device, the above-mentioned problem of the EEPROM can be dealt with only inside the memory card.
It is considered to be usable for M-card like.

As described above, the memory card having the microcomputer therein can have a plurality of functions for coping with various problems of the EEPROM in addition to the above-mentioned functions. Although details will be described later, some functions are considered to be changed by using a certain state as a trigger. In the case of such a function, the most commonly considered trigger for the function is the initialization of the memory card. That is, the initialization of the memory card is because it is convenient for triggering the above-mentioned function in many cases because the entire data storage area of the EEPROM is erased.

By the way, the initialization of this memory card is
In a host device such as an electronic still camera equipped with a memory card, when an operation of initializing the memory card is performed, the host device erases all data storage areas of the EEPROM, that is, writes data such that 0 can be written. This is done by giving it to a memory card. That is, at the time of initialization, the host device does not supply the initialization command to the memory card, but only the write operation of writing the logical value 0 to all the memory cells is executed.

For this reason, the microcomputer in the memory card cannot easily determine whether or not the host device has initialized the memory card. Therefore, by providing the microcomputer in the memory card, various types of EEPROM can be provided. Although it is possible to provide a plurality of functions for coping with the above problem, there is a problem that those functions cannot be realized because initialization cannot be easily discriminated.

[0018]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
A conventional memory card with a built-in ROM cannot easily determine whether or not the host device has initialized it, and thus cannot implement a plurality of functions for coping with various problems of the EEPROM. I have a problem.

Therefore, the present invention has been made in consideration of the above circumstances, and an object thereof is to provide an extremely good memory card device capable of easily determining whether or not the host device has initialized. To do.

[0020]

A memory card device according to the present invention shows a data storage area divided into a plurality of reference areas having a fixed capacity and the presence / absence of data in each reference area of the data storage area. It is intended for one having a built-in semiconductor memory having a management data storage area in which management data is written. Further, the contents of the management data storage area are provided with a control means for detecting that at least one of the reference areas has changed from a state with data to a state without data, and it is judged as initialization. is there.

[0021]

According to the above configuration, it is determined that the contents of the management data storage area are initialized when it is detected that at least one of the reference areas has changed from the state with data to the state without data. By doing so, it becomes possible to easily determine whether or not the host device has performed initialization.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, reference numeral 11 denotes a memory card main body, which is connected to a host device (not shown) such as an electronic still camera main body via a connector 12 installed at one end thereof. The connector 12 is supplied with digital data to be written in the EEPROM 13 in the memory card body 11 and address data indicating the writing location from the host device. These digital data and address data are supplied to the bus line 14. Through memory control gate array 1
5 is being supplied.

From the host device, the connector 1
2, various control signals CT necessary for writing and reading data to and from the EEPROM 13 are supplied.
T is also supplied to the memory control gate array 15. Furthermore, this memory control gate array 1
From 5, the ready / busy switching signal RDY that specifies whether to permit the input of digital data from the host device
/ BSY is generated and supplied to the host device via the connector 12.

The memory control gate array 15 has a buffer memory (not shown) therein, and the microcomputer 16 can write and read digital data to and from the buffer memory.
Controlled by. That is, the digital data output from the host device and supplied to the connector 12 is once taken in and recorded in the buffer memory. At this time, the capture timing of the digital data in the buffer memory is
It is controlled by the address data generated by the microcomputer 16 based on the bus clock BCK synchronized with the address data by one of the control signals CT.

When the writing of the digital data to the buffer memory is completed, the microcomputer 16 generates address data based on the internal clock CK generated from the internal oscillator circuit 17, and the address data generates the digital data from the buffer memory. Is read and output to the EEPROM 13 via the bus line 18. At this time, the microcomputer 16
EEPR via memory control gate array 15
The address data AD is output to the OM 13, and the digital data read from the buffer memory is stored in the EEPROM 1
3 is controlled to be written in the unit of page of 512 bytes, for example.

Next, the microcomputer 16 uses the EE
With digital data written in the PROM 13,
Memory control gate array 15 to EEPROM
The address data AD that previously specifies the writing of data is output to 13 and the written digital data is read from the EEPROM 13 to check whether it matches the digital data recorded in the buffer memory. Execute the write verify, which is determined.

If the digital data read from the EEPROM 13 and the digital data recorded in the buffer memory do not match, the microcomputer 16 again transfers the digital data from the buffer memory to the EEPROM 13 to perform writing. This operation is repeated until the digital data read from the EEPROM 13 and the digital data recorded in the buffer memory completely match, and when they match, the writing operation of the digital data to the EEPROM 13 is completed.

When reading the digital data recorded in the EEPROM 13 to the host device, a read request is made from the host device via the connector 12 and the address where the digital data to be read is recorded is specified. Then, the microcomputer 16
Is an internal clock CK generated from the internal oscillator circuit 17.
Based on the address data AD generated based on
Digital data is read from the EPROM 13, and the memory control gate array 15 is read via the bus line 18.
Write to the buffer memory of.

After that, the microcomputer 16 generates address data on the basis of the bus clock BCK given from the host device, reads digital data from the buffer memory by this address data, and the host line via the bus line 14 and the connector 12. The digital data is read out from the EEPROM 13 to the device.

Further, when the host device is operated to initialize the memory card body 11, the host device outputs address data, digital data and a control signal CT for writing 0 to all data storage areas of the EEPROM 13. The memory card main body 11 is initialized by giving it to the connector 12.

Here, the data generated from the host device and supplied to the connector 12 of the memory card body 11 includes:
If normal data, that is, if the host device is an electronic still camera, there are still image data obtained by shooting, and various management information (header data) including attribute information of this data. The microcomputer 16 is provided with E
An EPROM 19 is connected, and this EEPROM 1
Header data is written in 9 and normal data is EEP
It is adapted to be written in the ROM 13.

That is, the EEPROM 19 and the EEPROM
The address space combined with M13 is, as shown in FIG. 2, n + 1 clusters 0 each consisting of 8 kbytes.
Are divided into clusters 0 to 1, that is, the clusters 0 and 1, that is, addresses 000000h to 003FFFh are header areas in which header data is written, and the clusters 2 to n, that is, addresses 00400h to FFFFFFh are data areas in which normal data is written. The h added to the end of the address means that it is hexadecimal.

In the microcomputer 16, the address designated by the host device to write data is 00
If it is in the range of 0000h to 003FFFh, it is determined that the data to be written is header data, the header data is controlled to be written in the EEPROM 19, and the address designated by the host device to write the data is 004000h to FFFFFFh. If it is within the range, it is determined that the data to be written is normal data, and the data is controlled to be written in the EEPROM 13.

Here, in the header area, as shown in FIG.
As shown in (a), a MAT (memory allocation table) area is set. In this MAT area, as shown in FIG. 3B, n + 1 clusters 0
Storage areas 19 ₀ , 19 ₁ , ...
, 19 _n are provided, and each storage area 19 ₀ , 19
_{The number} of the cluster in which the data following the data written in the clusters 0 to _n of the EEPROM 13 is stored in _{1, ...,} 19n, that is, the chain destination cluster number is written.

That is, for example, assuming that the data A for one still image is divided into four clusters 2, 10, 50, 31 and written in this order, each cluster 2, 10, 50, As shown in FIG. 4, the storage areas 19 ₂ , 19 ₁₀ , 19 ₅₀ , and 19 ₃₁ of the MAT area corresponding to ₃₁ are respectively 10h, 50h, 31h, and FFh.
Data is written.

The cluster number (2 in this case) in which the head data of the data A is written is written in the other part of the header area, and when the reading of the data A is requested, the micro first. The computer 16 reads from that portion that the cluster number in which the leading data of the data A is written is 2, and the EEPROM 13
The data stored in the cluster 2 is read. Next, the microcomputer 16 reads the data 10h in the storage area 19 ₂ corresponding to the cluster 2 in the MAT area, so that the data following the data stored in the cluster 2 in the EEPROM 13 is stored in the cluster 10. Judgment is made and the data stored in the cluster 10 of the EEPROM 13 is read.

After that, the microcomputer 16 makes the M
By reading the data 50h in the storage area 19 ₁₀ corresponding to the cluster 10 in the AT area, it is determined that the data following the data stored in the cluster 10 in the EEPROM 13 is stored in the cluster 50, and the EEPROM 13
The data stored in the cluster 50 is read. Then, the microcomputer 16, by reading the data 31h of the storage area 19 ₅₀ corresponding to cluster 50 of the MAT area, determines that the data following the data stored in the cluster 50 of EEPROM13 is stored in the cluster 31 Then, the cluster 31 of the EEPROM 13
The data stored in is read, and all the data A is read here.

Next, the microcomputer 16 uses the MA
The data FFh in the storage area 19 ₃₁ corresponding to the cluster 31 in the T area is read, but since this FFh represents the end of the chain of data, the EEPROM 1
The operation of reading data from 3 will be completed.

Here, the point to be noted is the EEPROM 1
Cluster 0 to n in which no data of 3 is written
Storage areas 19 ₀ , 19 ₁ , ... Of the MAT area corresponding to
.., 19 _n are all written with data 00h. And this, in other words,
From the host device, an arbitrary cluster i in the EEPROM 13
When it is requested to erase the data written in (0 ≦ i ≦ n), the content of the storage area 19 _i of the MAT area corresponding to the cluster i is also rewritten to 00h by the instruction from the host device. It means that.

Therefore, the microcomputer 16 is
By detecting that the content of the arbitrary storage area 19 _i of the MAT area has changed from a value other than 00h to 00h,
It can be determined that the cluster i in the EEPROM 13 has been erased. The initialization of the memory card body 11 by the host device means that all the storage areas 19 ₀ , 19 ₁ , ..., 19 _{n in} the MAT area are all 00h, and therefore the microcomputer 16 uses the MAT Periodically looking at the contents of the area, the entire storage area 19 of the MAT area
_When at least one of ₀ , 19 ₁ , ..., 19 _n changes from the state where it is not 00h to the state where all are 00h, it can be judged that it has been initialized.

Therefore, according to the configuration of the above embodiment, when the cluster i of the EEPROM 13 is erased, the storage area 19 of the MAT area corresponding to the cluster i
By the content of _i is to utilize the fact that rewritten to 00h, the microcomputer 16, the entire storage area 19 _0, 19 ₁ of MAT area, ..., at least one but not 00h condition of 19 _n, all 00h By detecting the change to the state, it becomes possible to easily determine that the initialization has been performed.

Here, as a function for coping with various problems of the EEPROM 13 described above, a function triggered by the initialization of the memory card body 11 will be specifically described. That is, the EEPROM 13 is
If the number of data rewrites exceeds a certain number, the memory cells are rapidly deteriorated, and a data write defect is likely to occur. This is because the EEPROM 13 was developed for recording program data, and is intended to be able to rewrite data when the version of the program is upgraded, so that it is possible to support many times of data rewriting. Because it is not designed to.

However, as described above, when the EEPROM 13 is used instead of the conventionally used SRAM as a semiconductor memory for a memory card used in, for example, an electronic still camera device, it goes without saying. Since the EEPROM 13 is used in such a manner that data is frequently rewritten, it is inevitable that the occurrence rate of write defects will increase dramatically. Become.

With respect to this writing failure, conventionally, it is determined that the writing failure occurs when the writing verification processing described above is not correctly written even after repeating a predetermined number of times. Therefore, if data is frequently rewritten in a specific storage area of the EEPROM 13 by a command from the electronic still camera side, the storage area may become defective in a very short period of time. Occurs. In this case, conventionally, the EEPROM 13
Other EE's storage area is normal, but its EE
Since the entire memory card containing the PROM 13 is treated as a defective product, there is a disadvantage that it is very inefficient and causes an economic disadvantage.

Therefore, it is conceivable to form a management table in the EEPROM 19 for associating the address of the EEPROM 13 (hereinafter referred to as a logical address) designated by the host device with the actual address of the EEPROM 13 (hereinafter referred to as a physical address). ing. In this management table, the entire data storage area of the EEPROM 13 is set to 1
It is divided into 00 blocks, and the correspondence between the logical address and the physical address is managed in block units.

That is, as shown in FIG.
The PROM 19 has 100 logical addresses 0, 1, ...
, 99 corresponding to physical address storage areas 20
_0, 20 _1, ..., 20 ₉₉ are provided, each of the physical address storage area 20 _0, 20 _1, ..., 20 ₉₉ EEP
The physical addresses 0, 1, ..., 99 of the ROM 13 are respectively written to form a management table. In this case, when the host device requests the data rewriting for the logical address 0, the microcomputer 16
By referring to the management table, the physical address 0 of the EEPROM 13 is requested to rewrite data, and E
Digital data is rewritten to the physical address 0 in the EPROM 13.

Here, when the microcomputer 16 detects that the memory card body 11 has been initialized as described above, the microcomputer 16 operates as shown in FIG.
As shown in (b), the physical address storage areas 20 ₀ , 2
The contents of 0 ₁ , ..., 20 ₉₉ are shifted by 13, and the physical address storage areas 20 ₀ , 20 ₁ , ..., 20 ₉₉ corresponding to the logical addresses 0, ₁ ,.
The management table is rewritten so that the physical addresses 13, 14, ..., 12 of the ROM 13 are respectively written. In this case, when the host device requests the data rewriting for the logical address 0, the microcomputer 16 refers to the management table to read the EEPR.
The physical address 13 of the OM 13 is requested to rewrite data, and the EEPROM 13 rewrites the digital data to the physical address 13.

Similarly, every time the memory card body 11 is initialized, the microcomputer 16 sets the contents of the physical address storage areas 20 ₀ , 20 ₁ , ..., 20 ₉₉ to 1 by 1.
Shift by three. Therefore, even if the same logical address 0 is designated by the host device, the physical address of the EEPROM 13 where the digital data is actually rewritten will be different each time it is initialized.
It is possible to equalize the number of times data is rewritten to the entire data storage area of the EPROM 13. In this case, the conversion of the logical address supplied from the host device into the physical address is performed by the microcomputer 16 in the memory card body 11 referring to the conversion table stored in the EEPROM 19, regardless of the host device. Since it is executed only by internal processing, it can be used as an SRAM card when viewed from the host device.

The physical address storage areas 20 ₀ , 20
Physical address 0, 1, written in ₁ , ..., 20 ₉₉
The number of shifts of 99 cannot be divided by the number of divisions 100 of the entire data storage area of the EEPROM 13 13
Therefore, even if the initialization is repeated, for example, eight times and completes one round, as shown in FIG. 5C, the physical address storage area 2
The physical addresses 5, 6, ..., 4 of the EEPROM ₁₃ are written in 0 ₀ , 20 ₁ , ..., 20 ₉₉ , respectively, and the data does not become the same as the management table shown in FIG. It is effective in leveling the number of rewriting of. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0050]

As described above in detail, according to the present invention,
It is possible to provide a very good memory card device that can easily determine whether or not the host device has initialized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a diagram shown for explaining an address space of an EEPROM in the embodiment.

FIG. 3 is a diagram shown for explaining a MAT region in the example.

FIG. 4 is a diagram shown for explaining an operation using the same MAT region.

FIG. 5 is a diagram shown for explaining an example of a function for solving the problem of the EEPROM to which the present invention is applied.

FIG. 6 is a diagram showing the lengths of an SRAM and an EEPROM in comparison with each other.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... EE
PROM, 14 ... Bus line, 15 ... Memory control gate array, 16 ... Microcomputer, 17 ...
Internal oscillator circuit, 18 ... Bus line, 19 ... EEPRO
M.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/907 B 7916-5C

Claims (1)

[Claims] 1. A data storage area divided into a plurality of reference areas having a fixed capacity, and a management data storage area in which management data indicating the presence or absence of data for each reference area of the data storage area is written. In a memory card device having a built-in semiconductor memory, the content of the management data storage area is initialized by detecting that at least one of the reference areas has changed from a state with data to a state without data. A memory card device comprising control means for making a judgment.