JP3099908B2 - EEPROM control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention relates to a control device for E EPROM (Electrically Karie-erasable-and-programmable read only memory), especially
About those suitable for use in a memory card or the like of the electronic still camera apparatus.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed subject into an electric image signal using a solid-state image sensor, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-like case is configured to be detachable from a camera body, so that a film in an ordinary camera can be obtained. Equivalent handling is provided.

[0003] Here, the standardization of the memory card of the electronic still camera device is currently in progress. The built-in semiconductor memory is required to have a large storage capacity to record a plurality of digital image data.
AM (static random access memory),
Mask ROMs and electrically erasable EEPROMs and the like have been considered, and memory cards using SRAMs have already been commercialized.

A memory card using an SRAM has an advantage that it can support a data structure of any format and has a high data write speed and a high data read speed. On the other hand, since it is necessary to store a backup battery for holding written data in the memory card, the storage capacity is reduced by the amount of the battery storage space, and the S
There is a problem that the cost of the RAM itself is high and causes economic disadvantage.

[0005] Therefore, at present, an EEPROM is attracting attention as a semiconductor memory for solving the problems of the SRAM. This EEPROM is regarded as a promising recording medium in place of a magnetic disk. In particular, there is a special advantage that SRAM does not have, such as not requiring a backup battery for retaining data and reducing the cost of the chip itself. For this reason, development for use as a memory card has been actively conducted. FIG. 7 shows a memory card using an SRAM (SRAM card) and a memory card using an EEPROM (EEPRO).
M card).

First, regarding the backup battery and the cost of the comparison items 1 and 2, as described above, the SRAM
The card has a problem that a backup battery is required, it is difficult to increase the capacity, and the cost is high. On the other hand, the EEPROM card has the advantages that a backup battery is not required, the capacity can be easily increased, and the cost can be reduced.

Next, with regard to the write speed and read speed of the comparison items 3 and 4, data is written and read to and from a byte or a bit arbitrarily designated by an address. By designating a mode and a page composed of a plurality of consecutive bytes (several hundred bytes), it is possible to divide the mode into a page mode unique to an EEPROM in which data is written and read in a page unit at a time.

In the random access mode, the SRAM
Has a fast write and read speed,
The EEPROM has a low write speed and a low read speed. In page mode,
Since the EEPROM writes and reads a large amount of data for one page at a time, the data write speed and the data read speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM.
This mode does not exist in. That is, the EEPROM
When writing new data to a storage area in which data has already been written, new data cannot be written unless the previously written data is erased once. Therefore, when writing data,
This erase mode is executed. The erase mode includes a page erasing operation in page units, a block erasing operation in block units of several kilobytes, and a chip erasing mode in which the entire operation is collectively erased.

The write verify of the comparison item 6 is also a mode peculiar to the EEPROM, and is a mode not existing in the SRAM. That is, the EEPROM is
In the case of performing data write, usually, complete write is not performed by one write operation. For this reason, EEP
Each time a write operation is performed on the ROM, EEP
It is necessary to read out the written contents of the ROM and check whether or not the contents are correctly written. This is write verification.

Specifically, data to be written to the EEPROM is recorded in a buffer memory, and after the data is transferred from the buffer memory to the EEPROM and written,
The written contents of the EEPROM are read and compared with the contents of the buffer memory to determine whether they match. If it is determined that there is a mismatch (error) as a result of the write verification, the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is apparent from the above comparison results, EE
PROMs have unique advantages not found in SRAMs, such as no need for a backup battery, easy capacity increase, low cost, and the ability to write and read data in page units. . On the other hand, there is also a disadvantage that data write speed and read speed in the random access mode are slow, and a mode not provided in the SRAM such as an erase mode or a write verify is required.

Therefore, as a semiconductor memory used for a memory card, EE is used instead of the SRAM currently used.
Considering the use of a PROM, the problem of data write speed and data read speed, and the problem of requiring an erase mode and write verify, etc. can be solved, and a handling equivalent to a memory card having a built-in SRAM can be performed. Thus, it is important to make various improvements in detail so that it can be used for SRAM card-like.

[0014]

As described above, the SRA
When considering the use of an EEPROM for a memory card instead of M, it is an important problem in practical use to make an improvement so that the EEPROM card can be used for an SRAM card-like. Shortening is strongly desired.

Therefore, the present invention has been made in view of the above circumstances, and it is possible to minimize the processing time for writing image data by using an EEPROM. EEPROM
It is an object of the present invention to provide a control device.

[0016]

An EEPR according to the present invention
OM control device, the image data is written in the first storage area Rutotomoni, date information and Ta relating to the image data
It is intended for an EEPROM in which management data including shadow information is written to a second storage area. Then, there is provided a control means for batch-erasing the first storage area based on the initialization of the second storage area.

[0017]

According to the above arrangement, the image data is
Management data including date information and shooting information has been initialized
Occasionally, because so as to erase the image automatically data <br/> data managed by the management data, it is not necessary to perform a process of erasing the image data in the write processing, thereby the image data to the EEPROM Write processing time can be shortened.
It becomes suitable .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described below in detail with reference to the drawings.

In FIG. 1, reference numeral 11 denotes a memory card main body which is connected to an electronic still camera main body (not shown) via a connector 12 provided at one end of the memory card main body. The connector 12 is supplied with digital data DA to be written to the memory card main body 11, address data AD indicating a writing location, and a bus clock BCK synchronized with the address data AD from the electronic still camera main body. Although not shown, command data for designating the writing, reading, erasing, and initialization of the card is also supplied.

Here, the digital data DA output from the electronic still camera body side is memory management information such as attribute information of a memory card, various information unique to each image data, date information and information on the number of recordable images. Header data H
D and image (including sound) data PD corresponding to the subject
And are included. Among them, the header data HD has a small data capacity of about 16 Kbytes, and has a property that many data such as date information and information on the number of recordable images need to be rewritten in byte units. ing. Further, the image data PD has such a property that the data amount of one image is very large, and is entirely sequential.

The digital data DA supplied to the connector 12 is once taken into the buffer memory 13 and recorded. At this time, the fetch timing of the digital data DA into the buffer memory 13 is determined by the address generation circuit 1.
4 is controlled by the address data output from. The address generation circuit 14 counts the clock CK selected by the selector 15 and generates address data for the buffer memory 13.

The selector 15 outputs from the data processing control circuit 16 either the bus clock BCK supplied from the electronic still camera body side through the connector 12 or the read clock YCK supplied from the data processing control circuit 16. Selectively output according to the selected select signal SEL. That is, the bus clock BCK is selected when the digital data DA is fetched from the buffer memory 13, and the read clock YCK is derived to the address generation circuit 14 as the clock CK when the digital clock DA is read.

The data processing control circuit 16 switches to the designated processing mode based on the command data supplied through the connector 12. The address data AD is supplied to the data processing control circuit 16, and the header address data HAD or the image address data PAD is supplied.
Is determined. The buffer memory 13 has a storage capacity (1) capable of storing all the header data HD.
6K bytes or more). This buffer memory 1
The digital data DA fetched into 3 is read out from the buffer memory 13 and written into the EEPROM 17 under the control of the data processing control circuit 16 described later.

The EEPROM 17 has a large storage capacity of 4 Mbits or more, and cannot perform writing and erasing of data in units of bytes, but can perform erasing in batches and erasing in blocks of several kilobytes, as well as several hundreds of bytes. Data can be written and read in page units of bytes. This erasing process is performed by the erasing circuit 18.

According to a standard format which has recently been standardized for a memory card in an electronic still camera, the memory space area of the EEPROM 17 is divided into N banks as shown in FIG. . Each bank is divided into a header data HD storage area A and an image data PD storage area B. The spatial configuration is in cluster units. As shown in FIG. 3, the structure of the cluster is composed of erase blocks, and M (a fixed value of 1 or more)
It consists of blocks. Data is handled in packet units, and as shown in FIG. 4, L (an arbitrary value of 1 or more)
It consists of clusters.

As an example, FIG. 5 shows a data format in the header data storage area A of bank 0. In this area, the absolute address 0h to 3FFh is code-specific attribute information, and each bank is from 400h to 3FFFFh.
The addresses up to and including the address management of the image data stored in the address after 4000h (image data PD storage area) and various information related to the image data (bank header information, packet selection information, packet related information,
Directory information, MAT (memory allocation
Table)).

In the above configuration, operation control in the card is performed by the data processing control circuit 16. First, the operation when the command data sent from the electronic still camera main body specifies the writing process and the header data HD and the image data PD are written in the EEPROM 17 will be described.

When the data processing control circuit 16 determines that the input address data AD is the header address data HAD, it sets the out enable data OE to the EEPROM 17 in an active state (for example, H level).
And the header data HD of the EEPROM 17
Address data AD for designating all storage areas is generated, and all header data HD stored in EEPROM 17 are generated.
Is read in page units.

Next, the data processing control circuit 16 sets the write enable data WE to an active state (for example, H level) for the buffer memory 13 and controls the select signal SEL to generate the read clock YCK generated by itself. Switch the selector 15 so as to be derived by the address generation circuit 14. Therefore, all the header data HD read from the EEPROM 17 is written to the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK.

After that, in a state where all the header data HD has been written into the buffer memory 13, the data processing control circuit 16 performs the following based on the header address data HAD.
The address generation circuit 14 generates set address data SA designating a byte of the header data HD to be rewritten.
And the address set data AS for setting the set address data SA in the address generation circuit 14 is output to the address generation circuit 14.

Then, the address generation circuit 14 generates address data from the set address data SA set based on the address set data AS, and outputs the address data to the buffer memory 13. At this time, the data processing control circuit 16 activates the write enable data WE for the buffer memory 13 so that the contents of the byte specified by the input address data of the buffer memory 13 are transmitted through the connector 12. Is rewritten with the new header data HD input by the user.

When the rewriting of the header data HD in the byte unit in the buffer memory 13 is completed, the data processing control circuit 16 generates the clock YCK generated by itself.
Is selected by the selector 1 so that
5 and activates the out enable data OE for the buffer memory 13. Therefore, the buffer memory 1 uses the address data generated by the address generation circuit 14 based on the clock YCK.
3, the header data HD is sequentially read.

At this time, the data processing control circuit 16
The write enable data WE is activated for the EPROM 17 and the address data AD for designating the entire header data HD storage area of the EEPROM 17 is generated. For this reason, all the header data HD stored in the buffer memory 13 after rewriting is stored in the EEP.
The data is transferred to the ROM 17 and written into the header data HD storage area in page units.

Thereafter, with all the header data HD written in the EEPROM 17, the data processing control circuit 16 sets the out enable data OE to the active state and designates all the header data HD storage areas for the EEPROM 17. Then, the address data AD to be output is output, the written header data HD is read, and write verification is performed to determine whether or not the header data HD matches the header data HD recorded in the buffer memory 13.

If the header data HD read from the EEPROM 17 does not match the header data HD recorded in the buffer memory 13, the header data HD is transferred from the buffer memory 13 to the EEPROM 17 again.
Is transferred and writing is performed. This operation is called EEPRO
This is repeated until the header data HD read from M17 and the header data HD recorded in the buffer memory 13 completely match, and the writing of the header data HD is performed here.

Here, the data processing control circuit 16 determines that the input address data AD is the image address data PA
If it is determined to be D, the image address data PAD is output to the EEPROM 18 and the write enable data WE is activated. next,
The data processing control circuit 16 controls the select signal SEL and switches the selector 15 so that the clock YCK generated by the data processing control circuit 16 is guided to the address generation circuit 14.

For this reason, the image data PD is sequentially read from the buffer memory 13 by the address data generated by the address generation circuit 14 based on the read clock YCK, and written in the EEPROM 17 in page units.

Thereafter, the image data P is stored in the EEPROM 17.
With D written, the data processing control circuit 16
For the EEPROM 17, the out enable data O
E is set to an active state, the image address data PAD is output, the written image data PD is read, and it is determined whether or not the image data PD matches the image data PD recorded in the buffer memory 13. Perform verification.

If the image data PD read from the EEPROM 17 and the image data PD recorded in the buffer memory 13 do not match, the image data PD is transferred from the buffer memory 13 to the EEPROM 17 again to perform a write operation. This operation is called EEPRO
The process is repeated until the image data PD read from M17 and the image data PD recorded in the buffer memory 13 completely match, and writing of the image data PD is performed here.

Next, the command data sent from the electronic still camera main body designates the reading process.
An operation for reading the header data HD and the image data PD from the EPROM 17 to the outside of the memory card main body 11 will be described.

First, an address at which data to be read is recorded is designated from the electronic still camera body via the connector 12. Then, the specified address is supplied to the data processing control circuit 16, and it is determined whether the address data is a header address data HAD or an image address data PAD.

Thereafter, the data processing control circuit 16 activates the out enable data OE and the write enable data WE for the EEPROM 17 and the buffer memory 13 based on the determination result,
The clock YCK generated by itself is generated by the address generation circuit 1
The selector 15 is switched to be derived to
The header data HD and the image data PD are read out from the ROM 17 in page units and written into the buffer memory 13.

The data processing control circuit 16 switches the selector 15 so that the bus clock BCK supplied from the electronic still camera main body via the connector 12 is led out to the address generation circuit 14, and the bus clock B
The address data generated by the address generation circuit 14 based on CK is read out from the buffer memory 13 and is led out to the main body of the electronic still camera via the connector 12, where the header data HD and the image data PD
Is read.

By the way, once the image data read by the above read processing is written in another recording medium, the memory card can be completely newly used by initializing the memory card. Further, there is a case where a specific bank is desired to be initialized by, for example, editing. Under these circumstances, the main body of the electronic still camera must initialize the memory card with initialization command data without specifying a bank when initializing all banks. Initialization command data with a bank designation is supplied to the memory card.

Here, in the case of the SRAM card, since overwriting is possible, only the header data HD storage area is initialized by the initialization command. EE
In the PROM, since overwriting cannot be performed, if only the header data HD storage area is initialized, erasure processing of the image data PD storage area is required at the time of writing, and the erasure processing also involves repeatedly executing block erasure. Therefore, it takes a long time for the writing process. Therefore, when the data processing control circuit 16 receives the initialization command data, the data processing control circuit 16 sends the EEPRM1
7, the following erasing process is executed.

First, it is determined whether or not initialization command data has been input, and if so, it is determined whether or not a bank has been designated. If no bank is specified here, it is determined that all banks are to be initialized at once, and the erase circuit 18 is initialized.
Through this process, all data in the header data HD storage area A is repeatedly executed for each of the banks 0 to N shown in FIG. Further, when it is detected that the initialization of each header data HD storage area A of all the banks 0 to N is completed, each image data PD storage area B of all the banks 0 to N is detected.
, All data is erased repeatedly. This is done by chip erasure, which
The initialization of the entire area of the ROM 17 can be completed in a short time.

When the bank designation is determined,
For each of the specified banks, header data HD
All data erasure of the storage area A is repeatedly executed.
Further, when it is detected that the initialization of each header data HD storage area A of the designated bank is completed, all data erasure is repeatedly executed for each image data PD storage area B of the designated bank. This is performed by chip erasing, whereby the initialization of the entire area of the designated bank of the EEPROM 17 can be completed in a short time. Another initialization method will be described.

As shown in FIG. 5 (an example of bank 0, other banks have the same configuration), the header data HD storage area of each of banks 0 to N has addresses 0h to 3FFh.
Card attribute information and address from 400h to 3FFF
h of address management information. Of these, the card attribute information does not need to be initialized, and the usage status of the entire storage area in the bank is recorded in a temporary information tuple at addresses 404h to 40Fh.

Accordingly, the main body of the electronic still camera rewrites the temporary information tuple of each bank in the card to the initial state. The data processing control circuit 16 detects the rewriting and refers to the tuple to determine that the bank is to be initialized. Then, the address management portion from 800h to 3FFFFh in the header data HD storage area A is collectively erased, and the FFs after the address 4000h are deleted.
The image data PD storage area B up to FFFFh is collectively erased.

The initialization portion to be executed first is not limited to the temporary information tuple, and the address management portion from 800h to 3FFFh can be similarly executed as long as the initialization can be detected.

Therefore, according to the configuration as in the above-described embodiment, when a rewrite request is issued to the header data HD having a property that the data amount is small and the data is often rewritten in byte units, the entire header is sent from the EEPROM 17. The data HD is read out to the buffer memory 13, and the header data HD is rewritten in the buffer memory 13 in units of bytes by random access.
3 is written in the EEPROM 17 in page units in the EEPROM 17, so that a large storage capacity EEPROM cannot be written or read in byte units.
Even when the OM 17 is used, writing and reading of data in byte units can be easily performed.

Moreover, since the data transfer between the electronic still camera main body and the memory card main body 11 is always performed via the buffer memory 13, the data writing speed and the reading speed are also improved, and the data is used for an SRAM card like. Will be able to do it. Also,
The write verification unique to the EEPROM 17 is also performed by the buffer memory 1 provided inside the memory card body 11.
3, so that the memory card body 11 can be completely used like an SRAM card.

Further, in the erase processing mode, when the header data is rewritten to be unused by the erase processing on the electronic still camera main body side, the information data is also automatically erased on the card side, so that the data is re-used. There is no need to perform erasure processing of information data at the time of writing, which can significantly reduce the writing processing time,
The electronic still camera body uses an EEPROM card for SRA
It can be used without distinction from M card.

By the way, recently, as an EEPROM, NA
Cells using the ND type structure have been developed. This NAN
FIGS. 6A and 6B show the planar structure of a D-type cell (8 bits) and its equivalent circuit, respectively. The erasing operation for a cell having this structure is performed, for example, by setting 0 [V] to the bit line BL,
By applying a voltage of 17 [V] to the control gates SGn and CGn, charges are stored in the floating gates M1 to M8,
Erasure of one byte becomes possible. With this application, erasing can be performed on a cell array in which a plurality of cells of the NAND type structure are connected to form one block.

In consideration of a large-capacity memory card exceeding 1 Mbit, the type and capacity of data to be recorded are not fixed, and the erasing operation for a card on which a plurality of data are recorded is performed on the target data. This is the only erasure, and the other data must be kept as it is. Therefore, the size of the block in which the cells of the NAND type structure are connected is a unit that does not affect other data even if the data is erased collectively, and is considerably smaller than the total capacity of the card.

Data of a capacity of several hundred kilobytes or more is recorded on such a NAND type EEPROM card.
When erasing this data or when initializing the entire memory card and erasing all data, it is necessary to repeat the above-described erasing in block units. From this, assuming that the erase time of one block is t [sec] and the number of blocks to be erased is n [block], the time required for erase S
1 is S1 = n · t (1)

Is as follows. In addition, in order to erase one block, it is necessary to specify the address, specify the initialization, and take the time required for the interface.
c], when the number of blocks to be erased is n [blocks], the time S2 required for the interface is S2 = n · x (2), and the time S required for erasing the entire card is S = S1 + S2 = n T + n · x (3)

In order to initialize the entire data storage area of a memory card using such an EEPROM as a semiconductor memory, it is necessary to repeatedly erase all blocks in block units. Therefore,
As is apparent from the equation (3), the time S [sec] required for initializing the card is extremely long because the time required for the interface is added up by the number of blocks.

Therefore, when the NAND type EEPROM card is initialized by executing the above-described initialization processing,
Since chip erasing of a necessary area is performed, the time required for the interface can be reduced, the processing time for writing information data can be shortened as much as possible, and it can be used like an SRAM card. It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the invention.

[0060]

As described in detail above, according to the present invention,
By using the EEPROM, it is possible to shorten the image data write processing time as much as possible, and it is possible to provide an extremely good EEPROM control device suitable for use in a memory card or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration for an electronic still camera as an embodiment of an EEPROM control device according to the present invention.

FIG. 2 is a configuration diagram showing a memory space configuration of an EEPROM used in the embodiment.

FIG. 3 is a configuration diagram showing a cluster structure in a memory of the EEPROM.

FIG. 4 is a configuration diagram showing a packet structure stored in the EEPROM.

FIG. 5 is a configuration diagram showing a data format of a header data storage area in the memory space configuration.

FIG. 6 shows an example of an EEPROM to which the embodiment can be applied.
The figure which shows the planar structure which shows the structure by the cell using ND type structure, and its equivalent circuit.

FIG. 7 is a diagram showing a comparison between the lengths of an SRAM and an EEPROM.

[Explanation of symbols]

11 memory card body, 12 connector, 13 buffer memory, 14 address generation circuit, 15 selector, 16 data processing control circuit, 17 EEPROM
18: erase circuit, A: header data storage area, B: information data storage area

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-298600 (JP, A) JP-A-3-105640 (JP, A) JP-A-4-367834 (JP, A) JP-A-4- 307644 (JP, A) JP-A-4-313882 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 16/00-16/34 G06F 1/00 G06F 12/00 H04N 5/907

Claims (1)

(57) [Claims] 1. A picture data Re <br/> written into the first memory area Rutotomoni, date information and shot information relating to the image data
The management data including the information is written to the second storage area.
An EEPROM, comprising: a control unit for batch-erasing the first storage area based on the initialization of the second storage area.
Control device.