JP3359942B2 - Memory card device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Electrically Eraseable and Programmable Read-Only Memory) and the like.

[0002]

2. Description of the Related Art As is well known, EEPROMs are currently
An SRAM (Static Random Access Memory), which has attracted attention as a data recording medium that replaces a magnetic disk, does not require a backup battery for retaining data, and can reduce the cost of the chip itself. ) And D (Dynamic) RAM have particular advantages, and therefore, developments especially for use in memory cards have been actively conducted.

The memory card converts an optical image of a photographed object into an electric image signal using a solid-state image sensor, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. It is suitable for use in a still camera or the like. By configuring a memory card in which an EEPROM is built in a card-shaped case so that it can be attached to and detached from the camera body, handling equivalent to a film in an ordinary camera is achieved. Is made possible.

Here, the EEPROM has a page mode in which data is written and read in a page unit by specifying a page consisting of a plurality of consecutive bytes (for example, 512 bytes). By writing and reading a large amount of data for one page at a time, there is an advantage that the data writing speed and reading speed can be improved, but there is a problem that write verification is required when writing data. are doing.

That is, when data is written to the EEPROM, complete writing is not normally performed by one writing operation. For this reason, it is necessary to read the contents of the EEPROM every time one write operation is performed on the EEPROM and check whether or not the data has been correctly written. This is the write verify.

Specifically, one page of data to be written to the EEPROM is recorded in a buffer memory,
After data is transferred from the buffer memory to the EEPROM and written, the written contents of the EEPROM are read,
The contents of the buffer memory are compared to determine whether they match. If it is determined that there is a mismatch (error) as a result of the write verification, the operation of writing the contents of the buffer memory to the EEPROM again is repeated. For this reason, as the number of times of write verification increases, the number of times of rewrite increases, so that it takes time to write data and the data writing speed is deteriorated.

FIG. 6 is a flow chart showing a conventional data write processing operation when data is written to the EEPROM in page units. Here, assuming that the data write processing operation is controlled by a CPU (Central Processing Unit) (not shown), first, when it is started (step S1), the CPU sets the number of times of verification N to 1 in step S2. At the same time, the page number is set to 0, and control is performed to start writing from the first page of the EEPROM.

Then, the CPU sets the in-page address to 0 in step S3. That is, if one page is composed of 512 bytes as described above, the address of the first byte is set. After that, the CPU
In step S4, a write command for writing data is set in the EEPROM, and in step S5, the address and data for one page are transferred to the EEPROM.
Execute data writing.

Here, in the EEPROM, a high voltage of 20 V or more is applied to the gate of the transistor, and electrons in the channel are moved to cause a tunnel phenomenon.
Data is written to the memory cells. For this reason, after causing the CPU to execute data writing,
In step S6, in order to wait for a tunnel phenomenon to occur, a voltage application time obtained by multiplying a preset reference unit time of 40 μs (program time) by the number of times of verification N is waited. Set the instruction in the EEPROM.

Then, the CPU determines in step S8 that EE
Read the written data from the PROM, and execute step S
At 9, verification is performed to determine whether the read data matches the written data. And
As a result of the verification, if it is determined that they match (O
K) In step S10, the CPU determines whether the address in the page is 511, that is, whether it is the last byte of one page. If it is not the last byte (NO), the CPU proceeds to step S1.
In step 1, the address in the page is incremented by 1, and the process returns to step S8.

If it is the last byte (YES), C
In step S12, the PU determines whether or not the page is the last page. If the page is not the last page (NO), the PU proceeds to step S1.
In step 3, the page number is incremented by one, and the process returns to step S3. If it is the last page (YES), the CPU
Sets the reset command in the EEPROM in step S14, and here, the data write operation in the EEPROM in page units is completed (step S15).

On the other hand, if it is determined in step S9 that they do not match (NG), the CPU determines in step S16 whether or not the number of times of verification N has exceeded 100, and
If it is 0 or less (NO), the number of verifications N is incremented by 1 in step S17, the address in the page is set to 0 in step S18, and the write command is set to E in step S19.
The address and the data for one page are transferred to the EEPROM in step S20, and the data is written again in step S20.
After waiting for the voltage application time of 0 μs, the process returns to step S7.

If it is determined in step S16 that the value exceeds 100 (YES), the CPU proceeds to step S22.
Then, the reset command is set in the EEPROM, the page area is determined to be defective, and the process is terminated (step S23).

The data writing time for each memory cell of the EEPROM depends on the moving speed of electrons in the channel, that is, the voltage application time until a tunnel phenomenon occurs. That is, a memory cell in which a tunnel phenomenon occurs by applying a voltage for a short time requires a small number of times of verification, and a memory cell in which a tunnel phenomenon does not occur unless a voltage is applied for a long time inevitably increases the number of times of verification and increases the data write speed. Slows down.

The number of times of verification required by each memory cell to write data varies greatly within the same EEPROM chip. For this reason, even when writing data in page units, the number of times of verification is not limited to every page. There is a page in which data is written in a short time with a small number of times of verification and a short time, and a page in which data cannot be written unless the number of times of verification is long and a long time is required.

The variation in the number of times of verification is caused not only in the EEPROM chip but also in the EEPROM.
It also exists for each chip. For this reason, a memory card in which the number of times of verification is small and data writing is completed in a short time is also required for each memory card equipped with an EEPROM chip.
There are memory cards that cannot write data unless the number of times of verification is long and a long time is required.Thus, even if the memory card is of the same type, the data writing speed varies, making it difficult to average the quality. There is a problem that there is.

[0017]

As described above, a memory card having an EEPROM as a semiconductor memory is
Since the data writing time required for each memory cell of the EEPROM greatly varies, there is a problem that the data writing speed differs for each card and it is difficult to average the quality of the cards.

Therefore, the present invention has been made in view of the above circumstances, and provides an extremely good memory card device capable of absorbing a variation in data writing speed for each card and making the data writing speed uniform. The purpose is to:

[0019]

A memory card device according to the present invention executes a data write operation for a predetermined unit time, reads out the written data and compares it with the original data. It is intended for a device having a semiconductor memory in which data writing is performed by repeating data writing. Then, the memory area of the semiconductor memory is divided into predetermined reference areas, and a memory in which a table in which priority is assigned to each of the reference areas in ascending order of the time required for writing the data is formed, and a memory formed in this memory. Control means for sequentially writing data to each reference area of the semiconductor memory based on the priority of the table.

[0020]

According to the above arrangement, priorities are assigned in advance to the respective reference areas of the semiconductor memory in ascending order of the data write time, and when data write to the semiconductor memory is requested, Since data writing is started from the reference area where the data writing time is the shortest at the time, variations in the data writing speed for each card can be absorbed, and the data writing speed can be made uniform.

[0021]

An embodiment of the present invention will be described below in detail with reference to the drawings. In FIG. 1, reference numeral 11 denotes a memory card main body, which is connected to a host device (not shown) such as an electronic still camera main body via a connector 12 provided at one end thereof. The connector 12 is supplied with digital data to be written to the EEPROM 13 in the memory card main body 11, address data indicating the writing location, and the like from the host device. These digital data and address data are transmitted through the bus line 14. Memory control gate array 1 via
5.

Also, a connector 1 is provided from the host device.
2 are supplied with various control signals CT necessary for writing and reading data to and from the EEPROM 13.
T is also supplied to the memory control gate array 15. Further, the memory control gate array 1
5, the ready / busy switching signal RDY for designating whether to permit input of digital data from the host device.
/ BSY is generated and supplied to the host device via the connector 12.

Here, the memory control gate array 15 has a buffer memory (not shown) therein, and the operation of writing and reading digital data to and from the buffer memory is performed by the microcomputer 16.
Is controlled by That is, digital data output from the host device and supplied to the connector 12 is temporarily captured and recorded in the buffer memory. At this time, the digital data capture timing of the buffer memory is
It is controlled by address data generated by the microcomputer 16 based on a bus clock BCK synchronized with the address data by one of the control signals CT.

When the writing of the digital data to the buffer memory is completed, the microcomputer 16 generates the address data based on the internal clock CK generated from the internal oscillation circuit 17, and uses the address data to generate the digital data from the buffer memory. Is read out and output to the EEPROM 13 via the bus line 18. At this time, the microcomputer 16
EEPR via memory control gate array 15
The OM 13 outputs the address data AD, and the digital data read from the buffer memory is stored in the EEPROM 1
3 is controlled to be written in units of, for example, 512-byte pages.

Next, the microcomputer 16 executes EE
With the digital data written to the PROM 13,
From the memory control gate array 15 to the EEPROM
13 to output the address data AD for which data writing was previously specified, read the digital data written from the EEPROM 13, and determine whether or not it matches the digital data recorded in the buffer memory. A write verify operation for discrimination is performed.

If the digital data read from the EEPROM 13 does not match the digital data recorded in the buffer memory, the microcomputer 16 transfers the digital data from the buffer memory to the EEPROM 13 again and writes the digital data. This operation is repeated until the digital data read from the EEPROM 13 completely matches the digital data recorded in the buffer memory, and when the digital data matches, the operation of writing the digital data into the EEPROM 13 ends.

When reading digital data recorded in the EEPROM 13 to the host device, a read request is made from the host device via the connector 12, and an address at which the digital data to be read is recorded is specified. Then, the microcomputer 16
Is the internal clock CK generated from the internal oscillation circuit 17
The address data AD generated on the basis of
The digital data is read out from the EPROM 13 and the memory control gate array 15 is read out via the bus line 18.
In the buffer memory.

Thereafter, the microcomputer 16 generates address data based on the bus clock BCK given from the host device, reads digital data from the buffer memory by using the address data, and outputs the digital data from the buffer memory via the bus line 14 and the connector 12. The digital data is read out from the EEPROM 13 by the device.

Further, assuming that an operation for initializing the memory card body 11 is performed in the host device, the host device transmits address data, digital data, and a control signal CT for writing 0 to all data storage areas of the EEPROM 13. By giving the signal to the connector 12, the memory card main body 11 is initialized.

Here, an EEPROM 19 is connected to the microcomputer 16.
The OM 19 stores various management information including attribute information of data written in the EEPROM 13 and the like. A priority management table is formed in a part of the management information storage area of the EEPROM 19, as shown in FIG. As shown in FIG. 3, the priority management table stores the block number storage areas 19 ₁ , 19 ₂ , 19 ₃ ,... Corresponding to the priorities ₁ , ₂ , ₃ ,.
Is provided.

The EEPROM 13 has a block (several k) whose data storage area is composed of a plurality of continuous pages.
.., And are sequentially written in the block number storage areas 19 ₁ , 19 ₂ , 19 ₃ ,. That is,
EE is stored in the block number storage area 19 ₁ having the priority of 1.
Shortest block number of the data write time has been written in each block of the PROM 13, the block number storage area 19 ₂ of priority 2, EEPROM
The number of the block having the second shortest data write time among the 13 blocks is written.

This priority management table measures the time required to write data in block units when a data write test is performed on the EEPROM 13 at the time of shipment at the manufacturing factory of the memory card main body 11. It is created by writing a block number into the priority management area. Each of the block number storage areas 19 ₁ , 19 ₂ , 19 ₃ ,... Is selectively designated by a pointer.

Here, when the memory card main body 11 is initialized and the entire data storage area of the EEPROM 13 is set to 0, the pointer points to the block number storage area 19.
Indicate _one . In this state, when the data from the host apparatus writing is required, the microcomputer 16 reads the block number priority looking the position of the pointer is written to the block number storage area 19 ₁ of 1, the The address data AD corresponding to the block number is output to the EEPROM 13 via the memory control gate array 15 to write the data.

Thus, the block number storage area 1
9 blocks being written block number to _1, that is, when the data writing for the most data write time shorter blocks in each block of EEPROM13 is finished, the microcomputer 16 instructs the block number storage area 19 ₂ moving the position of the pointer as, subsequently, data write request from the host device, data writing block of the block number written in the block number storage area 19 _2, i.e. the second largest of each block of EEPROM13 It is controlled so that it is written in the short time block.

Therefore, according to the configuration as in the above embodiment, priorities are assigned in advance to the blocks of the EEPROM 13 in ascending order of the data write time, and
In a state where data writing to the PROM 13 has been requested,
Since data writing is started from the block with the shortest data writing time at that time, variations in the data writing speed for each card can be absorbed, and the data writing speed can be made uniform. in this case,
The microcomputer 16 in the memory card body 11 writes the data based on the priority order by the EEPROM.
Referring to the priority management area stored in No. 19,
Since it is executed by processing only inside the memory card main body 11 irrespective of the host device, it can be used completely like an SRAM card from the viewpoint of the host device.

Here, it has been described above that the data write time varies in the EEPROM 13 in page units. However, the data write time variation also occurs in byte units constituting a page. Here, the problem is that data writing to the EEPROM 13 is performed in page units. For example, if even one extremely long byte of data writing time exists in the same page, the byte has already been normally written. In this case, data writing is repeatedly performed on the other bytes in which data has been written, and this is what is called excessive writing.

In this case, the data writing to the EEPROM 13 utilizes the tunnel phenomenon caused by the movement of the electrons as described above. Therefore, if the data writing is repeated and the voltage application time becomes longer than necessary, the movement of the electrons is stopped. Becomes extreme, the threshold value of the memory cell changes, and a phenomenon that reading cannot be performed occurs. For this reason, although it is necessary to avoid extreme overwriting, since data is written in page units, it is not possible to prevent occurrence of overwriting in byte units.

FIG. 4 shows a means for solving such a problem. The means shown in FIG.
It utilizes the special properties of M. That is,
When a logical value 0 is written in a state of a logical value 1, the memory cell of the EEPROM is inverted to a logical value 0. However, even if a logical value 1 is written in a state of a logical value 0, the logical value of the logical value 0 is not inverted. It has the property that an erasing operation must be performed to invert from the state of the logical value 0 to the state of the logical value 1. Note that even if an erasing operation is performed in the state of the logical value 1, the logical value remains at 1. That is, EEP
For the ROM, erasing means setting the storage area to be erased to logical value 1.

Therefore, when data is written to the EEPROM, the data cannot be overwritten as in the case of the SRAM. Therefore, the storage area where the data is to be written is once erased, set to the logical value 1, and then again. Data needs to be written. The nature of such an EEPROM is such that a state in which a voltage is applied to a memory cell and electrons are moved in an erased state is written as a logical value 0,
A state in which a voltage is not applied to the memory cell and electrons are not moved, that is, a state in which nothing is performed is defined as writing of a logical value 1.
Since it is a well-known matter due to the cell structure of the EPROM, a detailed description is omitted.

In FIG. 4, digital data to be written into the EEPROM 13 is supplied to the input terminal 20. This digital data has a page length of 8 bytes as shown in FIG. 5A for convenience of description, and data is set to 0 and 1 for convenience. Then, the digital data is once written to the buffer memory 21 and then read out, and is written to the EEPROM 13 via the OR circuit 22 and the buffer circuit 23. The digital data for one page written in the EEPROM 13 in this manner is read from the EEPROM 13 and is compared by the comparison circuit 24 with the digital data read from the buffer memory 21.

The comparison circuit 24 compares the digital data read from the EEPROM 13 with the digital data read from the buffer memory 21 on a byte-by-byte basis. In the case of non-coincidence in (0), a comparison output which becomes H level (logical value 1) is generated. Therefore, assuming that the digital data read from the EEPROM 13 is as shown in FIG.
As shown in (c), a comparison output in which the second byte and the eighth byte from the left side in the figure are at H level is generated.

The comparison output of the comparison circuit 24 is supplied to the 1-bit RAM 25, and the comparison result for one page is held. Then, the digital data read from the buffer memory 21 and the output of the 1-bit RAM 25 are used for the knot circuit 2.
The digital data obtained by performing an OR operation on the data inverted in step 6 in the OR circuit 22 is data to be written to the EEPROM 13 for the second time. As shown in FIG. 5D, the digital data written to the EEPROM 13 for the second time is such that only the bytes in which the comparison result of the comparison circuit 24 does not match become the logical value 0, and the comparison result matches, that is, the data is normally written. Has a logical value of 1.

In other words, at the time of writing data to the EEPROM 13 for the second time, the logical value 0 is written to the byte where the comparison result of the comparing circuit 24 does not match, and the logical value 1 is written to the byte where the comparison result matches. Become like That is, as described above, writing a logical value 1 means that no voltage is applied to the memory cell, that is, nothing is performed. Therefore, writing a logical value 1 to a byte where the comparison result matches is performed as described above. This prevents the voltage from being applied to the memory cell of the byte any more, thereby preventing overwriting.

The digital data written in the EEPROM 13 is read from the EEPROM 13 and is compared again by the comparator 24 with the digital data read from the buffer memory 21. In this case, EE
The digital data read from the PROM 13 is shown in FIG.
If it is as shown in (e), the comparison circuit 2
4 generates a comparison output in which the second byte from the left in the figure is at the H level, as shown in FIG. 5 (f). The comparison output of the comparison circuit 24 is stored in the 1-bit RAM 25.
The digital data as shown in FIG. 5 (g) obtained by performing an OR operation on the data obtained by inverting the output of the NOT circuit 26 and the digital data read from the buffer memory 21 by the OR circuit 22 is shown in FIG. Is the data to be written for the third time.

After that, the result of reading the digital data written in the EEPROM 13 completely matches the original digital data shown in FIG. 5A as shown in FIG. Is no longer generated, the writing of the digital data to the EEPROM 13 is completed. The 1-bit RAM 25
Is cleared when a clear signal from the microcomputer 16 is supplied through the input terminal 27.

Therefore, the same digital data for one page is not repeatedly written in the EEPROM 13 until the comparison result by the comparison circuit 24 matches, but the logical value 1 is written in the byte in which the comparison result matches. Since the digital data to be written is changed, the voltage is no longer applied to the memory cell of the byte in which the data has been written normally, preventing the occurrence of excessive writing in byte units. it can. It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications without departing from the scope of the present invention.

[0047]

As described in detail above, according to the present invention,
It is possible to provide a very good memory card device capable of absorbing variations in the data writing speed for each card and making the data writing speed uniform.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a diagram showing a priority management table of the embodiment.

FIG. 3 is a diagram showing details of the priority management table.

FIG. 4 is a block diagram showing a means for preventing occurrence of excessive writing in byte units.

FIG. 5 is a view for explaining the operation of the means.

FIG. 6 is a flowchart showing an operation of writing data to an EEPROM.

[Explanation of symbols]

11: Memory card body, 12: Connector, 13: EE
PROM, 14 bus line, 15 memory control gate array, 16 microcomputer, 17
Internal oscillation circuit, 18 bus line, 19 EEPRO
M, 20: input terminal, 21: buffer memory, 22: OR circuit, 23: buffer circuit, 24: comparison circuit, 25:
1-bit RAM, 26 ... knot circuit, 27 ... input terminal.

Claims (2)

(57) [Claims] 1. A semiconductor in which data is written by executing a data write operation for a preset unit time, reading the written data, comparing the read data with the original data, and repeating the data writing again if the data does not match. In a memory card device provided with a memory, a memory in which a storage area of the semiconductor memory is divided into predetermined reference areas, and a table in which priority is assigned to each of the reference areas in ascending order of time required for writing data, is formed. And a control means for sequentially writing data to each reference area of the semiconductor memory based on the priority of a table formed in the memory. 2. The semiconductor memory according to claim 1, further comprising:
Can be inverted from the first logic state to the second logic state,
Cannot be inverted from the logic state of
From the logic state 2 to the first logic state by an erasure process
A cell to be inverted, wherein the control means performs a previous operation based on the priority of the table.
Write data to the semiconductor memory in units of each reference area
When performing, read the written data and
If they do not match, repeat the data writing.
When returning, the matching part of the data to be written is
2. The method according to claim 1, wherein the logic state is set to one.
Memory card device.