JP2008079754A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology that can use a NAND-type flash memory as a memory device for game machine. <P>SOLUTION: A display control section 60 of a Pachinko machine 10 is provided with a NAND-type flash memory 660, an ROM interface 658, and a relay CPU 658 which relays data transmission between the NAND-type flash memory 660 and the ROM interface 658. The relay CPU 658 determines defective blocks (step S730), creates an address-corresponding table 720, and executes writing into the NAND-type flash memory 660 (S step S740, S750). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gaming machine having a display screen for displaying a moving image.

  2. Description of the Related Art A gaming machine is known that includes an image display device such as a liquid crystal display and displays a moving image on the image display device to enhance the interest of the game. In drawing display, which is one of the moving image displays, a plurality of still images drawn one after another using character data previously written in a mask ROM (Masked Read Only Memory) are continuously displayed on the image display device. Moving image display is realized. In the reproduction display which is one of the moving image displays, the moving image display is realized by continuously displaying frames reproduced one after another from the movie data written in the mask ROM on the image display device.

  A mask ROM for storing digital image data because the amount of digital image data such as character data and movie data, which is the source of moving image display, increases as the display of moving images by drawing display and playback display is elaborated. The storage capacity required for this is constantly increasing. Patent Document 1 below discloses a gaming machine that displays moving images using digital image data written in a mask ROM.

Japanese Patent Laid-Open No. 2004-8483

  In recent years, large-capacity and low-cost NAND flash memories have become widespread, and it is conceivable to use NAND flash memories in game machines instead of mask ROMs as media for recording digital image data. There were various problems due to the difference in characteristics.

  For example, a NAND flash memory may have a defective block in which data cannot be recorded due to its structure, and the presence and location of the defective block varies from individual to individual. Therefore, in the case of a NAND flash memory, the presence or absence of a memory address for avoiding a defective block and the part thereof are also undefined for each individual, and data cannot be accessed using a series of memory addresses like a mask ROM. Also, as a problem peculiar to gaming machines, when checking the falsification of data recorded in the memory, there is a problem that it is not possible to perform a data check using a memory address common to the same type of memory as a mask ROM. there were.

  In view of the above-described problems, an object of the present invention is to provide a technology capable of using a NAND flash memory as a memory device for gaming machines.

  In order to solve the above-described problems, a gaming machine control device according to the present invention is a gaming machine control device that controls a display mode of a moving image displayed on a display screen of a gaming machine, in which digital image data is recorded. A NAND flash memory, a sequential interface that performs sequential access, a relay unit that relays data transmission between the NAND flash memory and the sequential interface, and the NAND flash memory through the sequential interface. A video display processor for generating a video signal for displaying the moving image based on the read digital image data, and the NAND flash memory has a series of physical block addresses assigned in the order of physical memory arrangement. Multiple The digital image data has a physical data block, and the digital image data is a good block capable of physically recording data by avoiding a defective block that cannot physically record data among the plurality of physical data blocks. And the relay unit determines the good blocks and the bad blocks included in the plurality of physical data blocks before the digital image data is recorded in the NAND flash memory, and the digital image Before data is recorded in the NAND flash memory, a series of physical block addresses arranged with the physical block addresses of the determined good blocks are sequentially converted into a series of logical block addresses used by the sequential interface for data exchange. A means for creating an associated address correspondence table and Before the digital image data is recorded in the NAND flash memory, characterized in that it comprises a means for writing an address correspondence table described above created the good block. According to the gaming machine control device described above, the address configuration of the NAND flash memory can be set so that it can be handled as a mask ROM in the gaming machine.

  The gaming machine control device described above can also take the following modes. For example, the relay unit further receives means for instructing writing of the digital image data using the logical block address before the digital image data is recorded in the NAND flash memory. Means for specifying a physical block address corresponding to a logical block address instructed to be written by the received write signal based on the address correspondence table before the digital image data is recorded in the NAND flash memory; The digital image data instructed to be written by the received write signal may be written to a good block to which the specified physical block address is assigned. Thus, digital image data can be recorded in the NAND flash memory so that it can be handled as a mask ROM in a gaming machine.

  The relay unit further includes means for receiving a read signal instructing reading of the digital image data using the logical block address, and a physical block corresponding to the logical block address instructed to read by the received read signal. Means for specifying an address based on the address correspondence table; means for reading the digital image data from a physical data block to which the specified physical block address is assigned; and the read digital image data for the sequential interface And a means for providing the above. Thus, digital image data can be read from the NAND flash memory so that it can be handled as a mask ROM in a gaming machine.

  The good block to which the address correspondence table is written may include a good block to which a physical block address preceding the good block to which the digital image data is written is assigned. Thereby, when digital image data is read from the memory device mounted on the gaming machine, the reading speed of the address correspondence table by the computer of the memory device can be improved.

  The good block in which the address correspondence table is written may include the first good block in the NAND flash memory. Thereby, when the digital image data is read from the memory device mounted on the gaming machine, the reading speed of the address correspondence table by the computer of the memory device can be further improved.

  The series of physical block addresses associated with the logical block address by the address correspondence table may include an address group in which the defective blocks are skipped and the good blocks are arranged in the physical memory arrangement order. Thereby, a good block for writing digital image data can be selected from a plurality of physical data blocks.

  Further, a series of physical block addresses associated with the logical block address by the address correspondence table replaces the defective block included in the series of physical block addresses arranged in the physical memory arrangement order with another good block. The address group in which the good blocks are arranged may be included. Thereby, a good block for writing digital image data can be selected from a plurality of physical data blocks.

  Note that the aspect of the present invention is not limited to the gaming machine control device, and a gaming machine including the gaming machine control device of the present invention, or a gaming machine storing digital image data displayed on the display screen of the gaming machine. The present invention can be applied to various modes such as a computer memory device, a NAND flash memory handling method, a gaming machine memory device manufacturing method, and a computer program for controlling a gaming machine control device. Note that gaming machines to which the present invention is applied include pachinko machines and slot machines.

  In order to further clarify the configuration and operation of the present invention described above, a gaming machine to which the present invention is applied will be described below.

A. Configuration of the pachinko machine 10:
A-1. Overall configuration of the pachinko machine 10:
A configuration of the pachinko machine 10 that is one of the embodiments of the present invention will be described. FIG. 1 is a front view showing the overall configuration of the pachinko machine 10. The pachinko machine 10 includes an outer frame 20 fixed to a so-called island facility of a pachinko store, an inner frame 30 fitted into the outer frame 20, and a gaming panel that is fitted near the center of the inner frame 30 to play a game ball. 40, a glass frame 50 having a glass plate covering the front surface of the game panel 40 and pivotally attached to the inner frame 30 so as to be openable and closable, and a card unit 80 for accepting rental of game balls by a prepaid card.

  The gaming panel 40 of the pachinko machine 10 includes a winning opening 44 for receiving a winning game ball, a liquid crystal display (LCD) 42 for displaying video as a game effect, and a light emitting diode (LED) 462 for emitting light as a game effect. A plurality of built-in electric decoration units 46, an effect driving unit 45 that moves a character doll as an effect of the game, and an effect sensor 47 that senses the infrared rays of the hand held by the player in order to allow the player to select an effect mode of the game Is provided. The winning opening 44 includes a gaming ball sensor 442 that detects a game ball that has won the winning opening 44 and a winning opening driver 444 that expands or contracts the introduction path of the gaming ball to the winning opening 44. In the present embodiment, the game ball sensor 442 includes an eddy current type sensor, the winning opening driving unit 444 includes a mechanism that drives a solenoid (not shown) as a power source, and the effect driving unit 45 includes steps. A mechanism for driving a motor (not shown) as a power source is included.

  The glass frame 50 of the pachinko machine 10 includes a speaker 55 that outputs high-frequency sound as a game effect, and an electrical decoration unit 56 that includes a plurality of light emitting diodes (LEDs) 562 that emit light as a game effect. The inner frame 30 of the pachinko machine 10 includes a handle 32 that receives an operation by the player for launching a game ball on the game panel 40, a speaker 34 that outputs a low-frequency sound as a game effect, and a game to the player. In order to select an effect mode, an effect sensor 36 that detects button input from the player is provided.

  FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 controls the progress of the game based on the input from the game ball sensor 442, and the production of each part according to the progress of the game based on the main command that is an instruction from the main control board 410 A peripheral control board 420 that controls the display, a display control unit 60 that controls a display mode of a moving image displayed on the LCD 42 based on a display command that is an instruction from the peripheral control board 420, and an instruction from the peripheral control board 420 A panel illumination board 430 that controls the luminance gradation of the LED 462 based on a certain gradation command, a peripheral distribution board 440 that distributes various signals from the peripheral control board 420 to each part of the pachinko machine 10, and a peripheral distribution board 440 A frame lighting board 450 for controlling the luminance gradation of the LED 562 based on an instruction from the peripheral control board 420 via the main control board 410 And a dispensing control board 310 for controlling the payout of game balls based on the payout command is shown. The circuit boards of the main control board 410, the peripheral control board 420, the panel lighting board 430, the peripheral distribution board 440, the display control unit 60, the frame lighting board 450, and the payout control board 310 are the inner frame 30 shown in FIG. Are provided on the back side (not shown).

  In this embodiment, the main control board 410, the peripheral control board 420, the display control unit 60, and the payout control board 310 are a read-only memory that stores in advance a CPU that executes various arithmetic processes and a program that defines the arithmetic processes of the CPU. Depending on the function of each circuit board such as a memory (Read Only Memory, hereinafter referred to as “ROM”) and a random access memory (Random Access Memory, hereinafter referred to as “RAM”) that temporarily stores data handled by the CPU An electronic circuit on which electronic components are mounted is provided. In this embodiment, the panel illumination board 430, the peripheral distribution board 440, and the frame illumination board 450 are each a large scale integrated circuit (Large Scale Integration, hereinafter referred to as “LSI”) corresponding to the function of each circuit board. An electronic circuit on which electronic components corresponding to the function of the circuit board are mounted is provided.

  The main command transmitted from the main control board 410 to the peripheral control board 420 includes information for instructing basic effects relating to the game such as so-called “big hit” and “out of play”. The peripheral control board 420 that has received the main command from the main control board 410 determines the effects to be executed by the effect execution units such as the LCD 42, the LED 462, the LED 562, the speaker 34, the speaker 55, and the effect drive unit 45 based on the main command. And various signals according to each production execution part are output. A signal from the peripheral control board 420 to the display control unit 60 includes a display command for instructing the display control unit 60 of the content of the video to be displayed on the LCD 42. The signal from the peripheral control board 420 to the panel illumination board 430 includes a gradation command that specifies the light emission mode of the LED 462.

A-2. Detailed configuration of the display control unit 60 in the pachinko machine 10:
FIG. 3 is a block diagram mainly showing an electrical configuration of the display control unit 60 in the pachinko machine 10. The display control unit 60 includes a gaming machine control device designed exclusively for gaming machines. In this embodiment, the display control unit 60 is configured as an electronic circuit board separate from the peripheral control board 420 and the LCD 42. However, it may be configured integrally with the peripheral control board 420 or may be configured integrally with the LCD 42.

  The display control unit 60 is a ROM that stores a drawing control unit 610 that controls each unit of the display control unit 60 based on display commands from the peripheral control board 420 and digital image data 730 used for moving image display on the LCD 42. Based on the VDP command from the rendering controller 610, the ROM interface 640 for exchanging data with the pseudo ROM device 650 by sequential access in accordance with the data transmission method with the ROM, and the functioning pseudo ROM device 650. An image display processor (Video Display Processor, VDP) 620 that generates a video signal to be driven from digital image data 730 of the pseudo ROM device 650 is provided. In the present embodiment, the drawing control unit 610 of the display control unit 60 is a computer including electronic components such as a CPU, a ROM, and a RAM. In this embodiment, the video signal output from the VDP 620 of the display control unit 60 to the LCD 42 includes an RGB (Red Green Blue) signal and a SYNC (synchronization) signal. Details of the pseudo ROM device 650 of the display control unit 60 will be described later.

  In this embodiment, the digital image data 730 of the pseudo ROM device 650 includes data that is a source of moving image display such as character data and movie data, and is recorded as compressed compressed data. In this embodiment, the display control unit 60 further includes a decompression circuit 632 that decompresses the digital image data 730 read from the pseudo ROM device 650 via the ROM interface 640 based on the decompression command from the drawing control unit 610, and a decompression circuit 632. Two decompression RAMs 636 and 638 for storing the digital image data 730 decompressed by the circuit 632 and a bus switch circuit 634 for switching the memory bus connection between the decompression circuit 632 and the VDP 620 for each of the decompression RAMs 636 and 638 are provided.

  In the present embodiment, the bus switch circuit 634 of the display control unit 60 performs drawing so that memory access to one of the decompression RAMs 636 and 638 by the decompression circuit 632 and memory access to the other of the decompression RAMs 636 and 638 by the VDP 620 can be executed simultaneously. Based on an instruction from the control unit 610, the memory bus connection to each of the expansion RAMs 636 and 638 is switched. By switching the memory bus connection by the bus switch circuit 634, each of the address spaces in the decompression RAMs 636 and 638 is associated with the same logical block address space used by the VDP 620 for memory access, and the decompression RAMs 636 and 638 are connected from the VDP 620. Is recognized as a single RAM. As a result, the writing of the digital image data 730 by the decompression circuit 632 and the reading of the digital image data 730 by the VDP 620 can be executed simultaneously, and the compressed digital image data 730 is efficiently transmitted from the pseudo ROM device 650 to the VDP 620. can do.

A-3. Detailed configuration of pseudo ROM device 650 in display control unit 60:
The pseudo ROM device 650 of the display control unit 60 is a gaming machine memory device designed exclusively for gaming machines, and includes a NAND type flash memory 660 in which digital image data 730 is recorded, and a pseudo ROM device. Relay CPU 652 that controls each part of 650, relay memory 656 that stores in advance relay program 710 that defines the operation of relay CPU 652, relay RAM 654 that temporarily stores data handled by relay CPU 652, and ROM interface as a ROM device And a pseudo ROM interface 658 for exchanging data with the 640. Details of the operation of the relay CPU 652 of the pseudo ROM device 650 will be described later.

  The pseudo ROM interface 658 of the pseudo ROM device 650 is a write terminal 659 that receives an input of a write signal indicating whether data can be written to the NAND flash memory 660 as one of various terminals electrically connected to the ROM interface 640. Is provided. In the present embodiment, in the pseudo ROM device 650 mounted on the display control unit 60, the write terminal 659 of the pseudo ROM interface 658 is connected to the ground, so that the write signal input to the write terminal 659 is binary. It is always maintained at the “low level (0)” of the signal.

  The NAND flash memory 660 of the pseudo ROM device 650 has a plurality of physical data blocks to which a series of physical block addresses are assigned in the order of physical memory arrangement. The physical data blocks of the NAND flash memory 660 include “good blocks” in which data can be physically recorded and “bad blocks” in which data cannot be physically recorded. In this embodiment, the NAND flash memory 660 has a storage area of 64 pages per physical data block, and a user data area of 2048 bytes and a redundant area of 64 bytes per page. The digital image data 730 is stored in the user data area in the good block. In this embodiment, when a physical block is a defective block, a flag indicating the defective block is written in the redundant area of the physical block.

  In the NAND flash memory 660 of the pseudo ROM device 650, an address correspondence table 720 that defines address correspondence between the pseudo ROM interface 658 and the NAND flash memory 660 is recorded in advance. The address correspondence table 720 is data prepared in advance for each NAND flash memory 660 installed in the pseudo ROM device 650 according to the storage state of the digital image data 730 in the NAND flash memory 660. In this embodiment, the address correspondence table 720 is stored in the user data area in the good block to which the physical block address preceding the good block in which the digital image data 730 is recorded is assigned.

  FIG. 4 is an explanatory diagram showing an example of the address correspondence table 720 stored in the relay memory 656. The address correspondence table 720 includes a series of logical block addresses 722 used by the ROM interface 640 for data exchange, a series of physical block addresses 724 in the NAND flash memory 660, and each physical block address is a good block or a bad block. The block status 726 indicating the stored data 728 recorded in each physical block address is shown, and the series of logical block addresses 722 is associated with the physical block address of the good block in which the digital image data 730 is recorded. It has been.

  In this embodiment, the NAND flash memory 660 has 10,000 physical data blocks, and 10,000 physical block addresses from “PBA0000” to “PBA9999” are stored in these physical data blocks. The type flash memory 660 is assigned in order of physical memory arrangement. In this embodiment, the NAND flash memory 660 records digital image data 730 indicated by codes from “GD0000” to “GD9799” corresponding to the data amount of 9800 physical data blocks. In the present embodiment, 9800 logical block addresses from “LBA0000” to “LBA9799” are prepared in accordance with the amount of digital image data 730 recorded in the NAND flash memory 660.

  In this embodiment, the digital image data 730 is sequentially recorded in the NAND flash memory 660 in the order of a series of physical block addresses following the address correspondence table 720, and the physical data block to be recorded is a defective block. In this case, data to be recorded after the defective block is sequentially recorded after the good block following the defective block. In the example shown in FIG. 4, the address correspondence table 720 is recorded in the physical data block of the physical block address PBA0000 which is the first good block. In the example shown in FIG. 4, digital image data GD0000 to GD0002 are sequentially recorded in the physical data blocks of physical block addresses PBA0001 to PBA0003 which are good blocks following the good block in which the address correspondence table 720 is recorded. The physical data block of the physical block address PBA0004 is skipped, and the digital image data “GD0003” is recorded in the physical data block of the physical block address PBA0005, which is a subsequent good block, and the subsequent digital image data is sequentially recorded in the same manner. Has been.

  In this embodiment, the series of logical block addresses 722 are sequentially associated with a series of physical block addresses in which the physical block addresses of good blocks in which the digital image data 730 is recorded are arranged in ascending order. In the example shown in FIG. 4, the logical block address LBA0000 is associated with the physical block address PBA0001, the logical block address LBA0001 is associated with the physical block address PBA0002, and the logical block address LBA0002 is associated with the physical block address PBA0003. The logical block address LBA0003 skips the physical block address PBA0004, which is a bad block, and is associated with the physical block address PBA0005, and the subsequent logical block addresses are sequentially associated with the physical block addresses in the same manner.

B. Operation of the pachinko machine 10:
FIG. 5 is a flowchart showing a read relay process executed by the relay CPU 652 of the pseudo ROM device 650. When the data read signal is input to the pseudo ROM interface 658, the relay CPU 652 starts the read relay process shown in FIG. When the relay CPU 652 starts the read relay process shown in FIG. 5, the relay CPU 652 receives a read signal from the pseudo ROM interface 658 (step S110). Thereafter, the relay CPU 652 refers to the logical block address designated by the received read signal in the address correspondence table 720, and specifies the physical block address associated with the logical block address (step S120). Thereafter, the relay CPU 652 reads out the digital image data 730 recorded at the specified physical block address from the NAND flash memory 660 (step S130). Thereafter, the relay CPU 652 provides the read digital image data 730 to the ROM interface 659 outside the pseudo ROM device 650 via the pseudo ROM interface 658 (step S140).

  In this embodiment, when the power of the pachinko machine 10 is turned on, the relay CPU 652 reads the address correspondence table 720 from the NAND flash memory 660 into the relay RAM 654 as an initial setting. Thereafter, the relay CPU 652 executes the read relay process of FIG. 5 with reference to the address correspondence table 720 read into the relay RAM 654. Thereby, the reading speed of data from the NAND flash memory 660 can be improved.

  FIG. 6 is a flowchart showing the write relay process executed by the relay CPU 652 of the pseudo ROM device 650. When a data write signal is input to the pseudo ROM interface 658, the relay CPU 652 starts the write relay process shown in FIG. When the relay CPU 652 starts the write relay process shown in FIG. 6, it receives a write signal from the pseudo ROM interface 658 (step S210). Thereafter, the relay CPU 652 determines whether or not the write signal input to the write terminal 659 of the pseudo ROM interface 658 is at a high level (1) (step S215).

  When the write signal input to the write terminal 659 is at a low level (0), for example, when the pseudo ROM device 650 is mounted on the display control unit 60 (step S215), the relay CPU 652 starts from the pseudo ROM interface 658. The write relay process is terminated without executing data writing based on the received write signal.

  On the other hand, when the write signal input to the write terminal 659 is at a high level (1), for example, when the digital image data 730 is recorded in the pseudo ROM device 650 prior to mounting on the display control unit 60 (step S215). The relay CPU 652 identifies the physical block address associated with the logical block address by referring to the address correspondence table 720 for the logical block address designated by the write signal received from the pseudo ROM interface 658 (see FIG. Step S220). Thereafter, the relay CPU 652 writes the digital image data 730 included in the write signal to the physical block address specified by the address correspondence table 720 (step S230).

C. Pseudo ROM device manufacturing method:
FIG. 7 is a flowchart showing a method for manufacturing the pseudo ROM device 650. In this embodiment, the pseudo ROM device 650 is a multi-chip module (MCM: Multi-Chip Module) in which a plurality of chips are sealed in one package. When the pseudo ROM device 650 is manufactured, the address correspondence table 720 and the digital In addition to the chips of the NAND flash memory 660 before the image data 730 is recorded and the relay memory 656 in which the relay program is recorded in advance, the chips of the relay CPU 652, the relay RAM 654, and the pseudo ROM interface 658 are prepared. . Thereafter, the prepared plurality of chips are sealed on the device substrate by the MCM manufacturing system (not shown), and the pseudo ROM device 650 is formed (step S710). In this embodiment, the relay memory 656 is a mask ROM in which a program that defines the operation of the relay CPU 652 is recorded in advance.

  Thereafter, the pseudo ROM interface 640 of the pseudo ROM device 650 is connected to a ROM writer (not shown) capable of exchanging data by sequential access (step S720). In this embodiment, the ROM writer connected to the pseudo ROM interface 640 outputs a high level (1) signal to the write terminal 659 of the pseudo ROM interface 640.

  The relay CPU 652 of the pseudo ROM device 650 acquires the total capacity value of data that is to be written to the pseudo ROM device 650 from the connected pseudo ROM writer, and then acquires the data based on the program recorded in the relay memory 656. Until a good block corresponding to the total capacity value is secured, discrimination between a good block and a bad block included in the physical data block of the NAND flash memory 660 is performed (step S730). Thereafter, the relay CPU 652 of the pseudo ROM device 650 creates the address correspondence table 720 based on the determination result of the physical data block (step S740). Thereafter, the relay CPU 652 of the pseudo ROM device 650 writes the address correspondence table 720 to the NAND flash memory 660 while holding the created address correspondence table 720 in the relay RAM 654 (step S750). In this embodiment, the address correspondence table 720 is written in the first good block in the NAND flash memory 660.

  After the address correspondence table 720 is written in the NAND flash memory 660 (step S750), the ROM writer connected to the pseudo ROM device 650 sends a write signal instructing writing of the digital image data 730 to the pseudo ROM device 650. The data is output to the pseudo ROM interface 640 (step S760). At this time, in this embodiment, the write terminal 659 of the pseudo ROM interface 640 is maintained at the high level (1) by the ROM writer.

  When a write signal is output from the ROM writer (step S760), the relay CPU 652 of the pseudo ROM device 650 performs the logical block address specified by the write signal received from the pseudo ROM interface 658 in accordance with the write relay process of FIG. To the address correspondence table 720 to identify the physical block address associated with the logical block address (step S770). Thereafter, the relay CPU 652 of the pseudo ROM device 650 writes the digital image data 730 included in the write signal to the physical block address specified by the address correspondence table 720 (step S780). Thereafter, the pseudo ROM device 650 is removed from the ROM writer (step S790), and the pseudo ROM device 650 in which the digital image data 730 is recorded is completed. Thereafter, the pseudo ROM device 650 is mounted on the display control unit 60.

  According to the pachinko machine 10 described above, a series of physical block addresses in which physical block addresses of good blocks in which the digital image data 730 is recorded in the NAND flash memory 660 are arranged are logical block addresses handled by the ROM interface 640. Accordingly, the digital image data 730 can be read from the NAND flash memory 660 via the ROM interface 640. That is, even the NAND flash memory 660 having a different defective block configuration is recognized as a ROM having the same data arrangement from the ROM interface 640 side. Therefore, in the pachinko machine 10, the NAND flash memory 660 can be used as a recording medium for the digital image data 730. Further, according to the method of manufacturing the pseudo ROM device 650 of FIG. 7, the pseudo ROM device 650 that can be handled as a mask ROM in the pachinko machine 10 is manufactured while the digital image data 730 is stored in the NAND flash memory 660. be able to.

  Further, whether or not data can be written to the NAND flash memory 660 from the outside of the pseudo ROM device 650 can be managed by a write signal input to the write terminal 659. The write terminal 659 of the pseudo ROM device 650 mounted on the display control unit 60 is connected to the ground, so that data writing to the NAND flash memory 660 is always prohibited. Accordingly, it is possible to prevent the digital image data 730 written in the NAND flash memory 660 from being modified without performing complicated control on the pseudo ROM device 650.

  Further, since the compressed digital image data is decompressed by switching between the two decompression RAMs 636 and 638, the digital image data can be decompressed by the decompression circuit 632 and the digital image data can be read by the VDP 620 at the same time. Therefore, the processing efficiency in transferring digital image data from the NAND flash memory 660 to the VDP 620 can be improved. Further, since each of the address spaces in the two decompression RAMs 636 and 638 is associated with the same logical block address space, the memory management processing in the VDP 620 can be simplified.

D. Other embodiments:
As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, it can implement with various forms within the range which does not deviate from the meaning of this invention. is there. For example, the NAND flash memory 660 is not limited to one in which digital image data is sequentially recorded by skipping defective blocks, and digital image data is recorded using an alternative block in which the defective block is replaced with another good block. It may be what was done.

  FIG. 8 is an explanatory diagram illustrating an example of the address correspondence table 720 stored in the relay memory 656 according to another embodiment. In the NAND flash memory 660 managed by the address correspondence table 720 in FIG. 8, a part of the good block is prepared as a substitute block, and the digital image data 730 is stored in the NAND flash memory 660 in the order of a series of physical block addresses. If the physical data block that is sequentially recorded and recorded is a defective block, the data to be recorded in the defective block is recorded in the alternative block. In the example shown in FIG. 8, digital image data GD0000 to GD0002 are sequentially recorded in the physical data blocks of physical block addresses PBA0001 to PBA0003 that are good blocks, and are recorded in the physical data block of physical block address PBA0004 that is a defective block. The digital image data GD0003 to be recorded is recorded in the physical data block of the physical block address PBA9999 which is a substitute block, and the subsequent digital image data is sequentially recorded in the same manner. In the example shown in FIG. 8, the series of logical block addresses 722 are sequentially associated with a series of physical block addresses in which the physical block addresses of good blocks in which digital image data is recorded are arranged in the order of storage of the digital image data. For example, the logical block address LBA0003 is associated with a physical block address PBA9999 that is an alternative block corresponding to the defective block of the physical block address PBA0003.

  In this embodiment, the digital image data 730 recorded in the NAND flash memory 660 is compressed data. However, in another embodiment, the digital image data 730 recorded in the NAND flash memory 660 is uncompressed data. It may be. In this embodiment, the prohibition of data writing to the NAND flash memory 660 is realized by an operation based on the software of the relay CPU 652, but the functions of the relay CPU 652 and the like are configured in hardware by an ASIC (Application Specific Integrated Circuit). It may be realized by doing. In addition, prohibition of data writing to the NAND flash memory 660 may be managed by the relay CPU 652 using a write prohibition flag in which whether data can be written to the NAND flash memory 660 is set. In this embodiment, when the write signal input to the write terminal 659 is a high level (1) value, it indicates that data can be written to the NAND flash memory 660 and is a low level (0) value. In this embodiment, it is indicated that data cannot be written to the NAND flash memory 660. However, in another embodiment, when the value is low level (0), data can be written to the NAND flash memory 660 and high level (1 ) May indicate that data cannot be written to the NAND flash memory 660.

1 is a front view showing an overall configuration of a pachinko machine 10. FIG. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 4 is a block diagram mainly showing an electrical configuration of a display control unit 60 in the pachinko machine 10. FIG. 6 is an explanatory diagram illustrating an example of an address correspondence table 720 stored in a relay memory 656. FIG. 15 is a flowchart showing a read relay process executed by the relay CPU 652 of the pseudo ROM device 650. 15 is a flowchart showing a write relay process executed by the relay CPU 652 of the pseudo ROM device 650. 5 is a flowchart showing a method for manufacturing a pseudo ROM device 650. It is explanatory drawing which shows an example of the address corresponding | compatible table 720 memorize | stored in the relay memory 656 in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 20 ... Outer frame 30 ... Inner frame 32 ... Handle 34 ... Speaker 36 ... Production sensor 40 ... Game panel 42 ... LCD
44 ... Winning slot 442 ... Game ball sensor 444 ... Winning slot drive unit 45 ... Direction drive unit 46 ... Electric decoration unit 462 ... LED
47 ... Production sensor 50 ... Glass frame 55 ... Speaker 56 ... Illumination part 562 ... LED
DESCRIPTION OF SYMBOLS 80 ... Card unit 310 ... Discharge control board 410 ... Main control board 420 ... Peripheral control board 430 ... Panel illumination board 440 ... Peripheral distribution board 450 ... Frame illumination board 60 ... Display control part 610 ... Drawing control part 620 ... VDP
632 ... expansion circuit 634 ... bus switch circuit 636, 638 ... expansion RAM
650 ... Pseudo ROM device 652 ... Relay CPU
654 ... Relay RAM
656 ... Relay memory 658 ... Pseudo ROM interface 659 ... Write terminal 710 ... Relay program 720 ... Address correspondence table 722 ... Logical block address 724 ... Physical block address 726 ... Block state 728 ... Stored data 730 ... Digital image data

Claims (8)

A control device for a gaming machine that controls a display mode of a moving image displayed on a display screen of a gaming machine,
A NAND flash memory in which digital image data is recorded;
A sequential interface for sequential access;
A relay unit that relays data transmission between the NAND flash memory and the sequential interface;
A video display processor that generates a video signal for displaying the moving image based on digital image data read from the NAND flash memory through the sequential interface, and
The NAND flash memory has a plurality of physical data blocks each assigned a series of physical block addresses in the order of physical memory arrangement,
The digital image data is recorded in a good block capable of physically recording data, avoiding a defective block that is physically impossible to record data among the plurality of physical data blocks,
The relay unit is
Means for discriminating between the good blocks and the bad blocks included in the plurality of physical data blocks before the digital image data is recorded in the NAND flash memory;
Before the digital image data is recorded in the NAND flash memory, a series of physical block addresses in which physical block addresses of the determined good blocks are arranged are used as a series of logical blocks used by the sequential interface to exchange data. Means for creating an address correspondence table sequentially associated with addresses;
A gaming machine control device comprising: means for writing the created address correspondence table in the good block before the digital image data is recorded in the NAND flash memory. A control device for a gaming machine according to claim 1,
The relay unit further includes:
Means for receiving a write signal instructing writing of the digital image data using the logical block address before the digital image data is recorded in the NAND flash memory;
Means for specifying a physical block address corresponding to a logical block address instructed to be written by the received write signal based on the address correspondence table before the digital image data is recorded in the NAND flash memory;
A gaming machine control device comprising: means for writing digital image data instructed to be written by the accepted write signal into a good block to which the specified physical block address is assigned. A gaming machine control device according to claim 1 or 2,
The relay unit further includes:
Means for receiving a read signal instructing reading of the digital image data using the logical block address;
Means for specifying a physical block address corresponding to a logical block address instructed to be read by the received read signal based on the address correspondence table;
Means for reading the digital image data from the physical data block to which the identified physical block address is assigned;
Means for providing the read digital image data to the sequential interface.   4. The gaming machine control device according to claim 1, wherein the good block to which the address correspondence table is written includes a good block to which a physical block address preceding the good block to which the digital image data is written is assigned. .   The gaming machine control device according to any one of claims 1 to 4, wherein the good block to which the address correspondence table is written includes a leading good block in the NAND flash memory.   The series of physical block addresses associated with the logical block address by the address correspondence table includes an address group in which the defective blocks are skipped and the good blocks are arranged in the physical memory arrangement order. Or a control device for gaming machines.   A series of physical block addresses associated with the logical block address by the address correspondence table replaces the defective block included in the series of physical block addresses arranged in the physical memory array order with another good block. 6. The gaming machine control device according to claim 1, comprising an address group in which good blocks are arranged.   A gaming machine comprising the gaming machine control device according to any one of claims 1 to 7.

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