JP2014155736A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which can improve processing efficiency in video image display using compression data.SOLUTION: A display control section 60 of a pachinko machine 10 has: a pseudo ROM device 650 which has digital image data 730 recorded as compression image data; drawing control section 610 which specifies the digital image data 730 used for a video image; a parallel interface 640 which reads the digital image data 730 from the pseudo ROM device 650; a buffer memory 675 which temporarily stores the read data; an expansion engine 676 which expands the stored data; and an expansion controller 672 which controls temporary stop and restart of reading by the parallel interface 640.

Description

  The present invention relates to a gaming machine having a display screen for displaying a moving image.

  A gaming machine such as a pachinko machine or a slot machine is known that has enhanced the interest of the game by displaying a moving image on an image display device such as a liquid crystal display. Drawing display, which is one of the moving image displays, realizes moving image display by generating a plurality of still images using character data recorded in advance in the built-in storage and continuously displaying the plurality of still images. . In addition, reproduction display, which is one of moving image displays, realizes moving image display by reproducing a plurality of frames from movie data recorded in advance in a built-in storage and continuously displaying the plurality of frames.

  The amount of digital image data such as character data or movie data that is the source of a moving image increases as the preference for moving image display increases. Conventionally, in order to save the data storage area of the internal storage, a gaming machine in which digital moving image data is compressed and stored in the internal storage has been proposed. Patent Document 1 below discloses a gaming machine in which digital image data is compressed and stored in a built-in storage.

Japanese Patent Laid-Open No. 2004-8483

  However, conventionally, moving image display is performed by decompressing large-capacity compressed data into uncompressed data while avoiding a shift between the progress of the game and the display content of the moving image display. There was not enough consideration. For example, if the amount of data that can be read at once from the built-in storage in which the compressed data is recorded differs from the amount of data that can be accepted at one time by the circuit that decompresses the compressed data, the progress of the game and the display content of the moving image display There was a need to process the data transfer so that there was no deviation between the two.

  In view of the above-described problems, an object of the present invention is to provide a gaming machine that can improve processing efficiency in moving image display using compressed data.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
The gaming machine control device of Application Example 1 is a gaming machine control device that outputs a video signal for displaying a moving image on a display screen of the gaming machine, and is a compressed image obtained by compressing digital image data used for the video signal. A memory device that records data, an image designation unit that designates compressed image data recorded in the memory device, and an image read that executes read processing for reading out the compressed image data designated by the image designation unit from the memory device A buffer memory for temporarily storing compressed image data read from the memory device by the image reading unit, and compressing the compressed image data stored in the buffer memory to the digital image data And the image read unit generates a data amount corresponding to the storage capacity of the buffer memory. When the read stop unit temporarily stops the progress of the read process every time it is read from the memory device, and when all of the compressed image data stored in the buffer memory is delivered to the image decompression unit, A read resumption unit for resuming the progress of the read process stopped by the read stop unit. According to the gaming machine control device of the application example 1, since the reading of the digital image data from the memory device is divided and executed according to the storage capacity of the buffer memory, the digital image larger than the storage capacity of the buffer memory Data can be expanded and used for moving image display.

Also, in the gaming machine, when a ball is won at the start winning opening, an electrical lottery is performed, and in the image display device, the lottery result is effect-displayed on the player over several tens of seconds. In recent years, in order to satisfy players who are used to displaying images on large screens and high-resolution displays, techniques such as increasing the screen size, increasing the resolution, and complicating images are also used in gaming machines. From this point of view, according to the gaming machine control device of the application example 1, by expanding a large volume of digital image data and using it for moving image display, the interest of moving image display synchronized with game progress is improved. be able to. In recent years, the power consumption of gaming machines has been increasing due to the effects of moving image display and electrical decoration.
Therefore, if a lottery game is won at a time, the power capacity of the hall in which these game machines are installed may be exceeded, and the power supplied to the game machines may be momentarily stopped. there were. Even for this problem, according to the gaming machine control device of Application Example 1, a moving image synchronized with the progress of the game by displaying a moving image obtained by expanding a large amount of digital image data without relying on an effect by electrical decoration. The interest of image display can be improved.

  Application Example 2 In the gaming machine control device according to Application Example 1, the read stop unit has a data amount within a storage capacity of the buffer memory, and is a data unit that can be read and accessed with respect to the memory device Each time the amount of data obtained by multiplying the number by an integer is read from the memory device by the image read unit, the progress of the read process may be temporarily stopped. According to the gaming machine control device of the application example 2, digital image data is read from the memory device in units of data that can be read and accessed by the memory device, and is divided according to the storage capacity of the buffer memory. Therefore, it is possible to improve the processing efficiency from reading of digital image data to expansion.

  [Application Example 3] The gaming machine control apparatus according to Application Example 1 or 2, which is further read out from the memory device by the buffer memory and a plurality of expansion lines constituting the image expansion unit and the image read unit. A data distribution unit that distributes the compressed image data to each of the buffer memories in the plurality of decompression lines, and the digital image data from the data decompressed by each of the image decompression units in the plurality of decompression lines And a data synthesizing unit. According to the gaming machine control device of the application example 3, since the expansion of the digital image data to the uncompressed data can be distributed to a plurality of expansion lines, the speed of the expansion process of the digital image data can be improved. it can.

  Application Example 4 The game machine control device according to any one of Application Examples 1 to 3, wherein the image read unit includes a parallel interface that exchanges data by parallel transfer, and the memory device includes the compressed image data May be recorded, and a NAND flash memory that exchanges data by serial transfer, and a relay unit that relays data transfer between the NAND flash memory and the parallel interface may be included. According to the gaming machine control device of the application example 4, it is possible to secure a storage area that can handle large-capacity digital image data with the NAND flash memory.

  Note that the aspect of the present invention is not limited to a gaming machine control device, a gaming machine including a gaming machine control device, a method for decompressing compressed data into uncompressed data in a gaming machine, and a gaming machine control device. The present invention can be applied to various modes such as a computer program for controlling. Note that gaming machines to which the present invention is applied include pachinko machines and slot machines.

1 is a front view showing an overall configuration of a pachinko machine 10. FIG. 2 is a block diagram showing an electrical schematic configuration of a pachinko machine 10. FIG. 4 is a block diagram mainly showing an electrical configuration of a display control unit 60 in the pachinko machine 10. FIG. 4 is a block diagram mainly showing a detailed configuration of a pseudo ROM device 650 in a display control unit 60. FIG. 6 is an explanatory diagram illustrating an example of an address correspondence table 720 stored in a relay memory 656. FIG. 10 is a flowchart showing an expansion control process executed by an expansion controller 672 of the display control unit 60. 10 is a flowchart showing a startup process executed by the relay CPU 652 of the pseudo ROM device 650. 15 is a flowchart showing a read relay process executed by the relay CPU 652 of the pseudo ROM device 650. 15 is a flowchart showing a write relay process executed by the relay CPU 652 of the pseudo ROM device 650. 15 is a flowchart showing table update processing executed by the relay CPU 652 of the pseudo ROM device 650. It is a block diagram which mainly shows the detailed structure of the pseudo ROM device 650 in the pachinko machine 10 of a 2nd Example. It is a flowchart which shows the write relay process performed by the relay CPU652 of the pseudo ROM device 650 in a 2nd Example. It is explanatory drawing which shows an example of the address corresponding | compatible table 720 memorize | stored in the relay memory 656 in other embodiment.

  In order to further clarify the configuration and operation of the present invention described above, a pachinko machine to which the present invention is applied will be described below.

A. First embodiment:
A-1. Overall configuration of the pachinko machine 10:
A configuration of the pachinko machine 10 that is one of the embodiments of the present invention will be described. FIG. 1 is a front view showing the overall configuration of the pachinko machine 10. The pachinko machine 10 includes an outer frame 20 fixed to a so-called island facility of a pachinko store, an inner frame 30 fitted into the outer frame 20, and a gaming panel that is fitted near the center of the inner frame 30 to play a game ball. 40, a glass frame 50 having a glass plate covering the front surface of the game panel 40 and pivotally attached to the inner frame 30 so as to be openable and closable, and a card unit 80 for accepting rental of game balls by a prepaid card.

  The gaming panel 40 of the pachinko machine 10 includes a winning opening 44 for receiving a winning game ball, a liquid crystal display (LCD) 42 for displaying video as a game effect, and a light emitting diode (LED) 462 for emitting light as a game effect. A plurality of built-in electric decoration units 46, an effect driving unit 45 that moves a character doll as an effect of the game, and an effect sensor 47 that senses the infrared rays of the hand held by the player in order to allow the player to select an effect mode of the game Is provided. The winning opening 44 includes a gaming ball sensor 442 that detects a game ball that has won the winning opening 44 and a winning opening driver 444 that expands or contracts the introduction path of the gaming ball to the winning opening 44. In the present embodiment, the game ball sensor 442 includes an eddy current type sensor, the winning opening driving unit 444 includes a mechanism that drives a solenoid (not shown) as a power source, and the effect driving unit 45 includes steps. A mechanism for driving a motor (not shown) as a power source is included.

  The glass frame 50 of the pachinko machine 10 includes a speaker 55 that outputs high-frequency sound as a game effect, and an electrical decoration unit 56 that includes a plurality of light emitting diodes (LEDs) 562 that emit light as a game effect. The inner frame 30 of the pachinko machine 10 includes a handle 32 that receives an operation by the player for launching a game ball on the game panel 40, a speaker 34 that outputs a low-frequency sound as a game effect, and a game to the player. In order to select an effect mode, an effect sensor 36 that detects button input from the player is provided.

  FIG. 2 is a block diagram showing an electrical schematic configuration of the pachinko machine 10. The pachinko machine 10 controls the progress of the game based on the input from the game ball sensor 442, and the production of each part according to the progress of the game based on the main command that is an instruction from the main control board 410 A peripheral control board 420 that controls the display, a display control unit 60 that controls a display mode of a moving image displayed on the LCD 42 based on a display command that is an instruction from the peripheral control board 420, and an instruction from the peripheral control board 420 A panel illumination board 430 that controls the luminance gradation of the LED 462 based on a certain gradation command, a peripheral distribution board 440 that distributes various signals from the peripheral control board 420 to each part of the pachinko machine 10, and a peripheral distribution board 440 A frame lighting board 450 for controlling the luminance gradation of the LED 562 based on an instruction from the peripheral control board 420 via the main control board 410 And a dispensing control board 310 for controlling the payout of game balls based on the payout command is shown. The circuit boards of the main control board 410, the peripheral control board 420, the panel lighting board 430, the peripheral distribution board 440, the display control unit 60, the frame lighting board 450, and the payout control board 310 are the inner frame 30 shown in FIG. Are provided on the back side (not shown).

  In this embodiment, the main control board 410, the peripheral control board 420, the display control unit 60, and the payout control board 310 are a read-only memory that stores in advance a CPU that executes various arithmetic processes and a program that defines the arithmetic processes of the CPU. Depending on the function of each circuit board such as a memory (Read Only Memory, hereinafter referred to as “ROM”) and a random access memory (Random Access Memory, hereinafter referred to as “RAM”) that temporarily stores data handled by the CPU An electronic circuit on which electronic components are mounted is provided. In this embodiment, the panel illumination board 430, the peripheral distribution board 440, and the frame illumination board 450 are each a large scale integrated circuit (Large Scale Integration, hereinafter referred to as “LSI”) corresponding to the function of each circuit board. An electronic circuit on which electronic components corresponding to the function of the circuit board are mounted is provided.

  The main command transmitted from the main control board 410 to the peripheral control board 420 includes information for instructing basic effects relating to the game such as so-called “big hit” and “out of play”. The peripheral control board 420 that has received the main command from the main control board 410 determines the effects to be executed by the effect execution units such as the LCD 42, the LED 462, the LED 562, the speaker 34, the speaker 55, and the effect drive unit 45 based on the main command. And various signals according to each production execution part are output. A signal from the peripheral control board 420 to the display control unit 60 includes a display command for instructing the display control unit 60 of the content of the video to be displayed on the LCD 42. The signal from the peripheral control board 420 to the panel illumination board 430 includes a gradation command that specifies the light emission mode of the LED 462.

A-2. Detailed configuration of the display control unit 60 in the pachinko machine 10:
FIG. 3 is a block diagram mainly showing an electrical configuration of the display control unit 60 in the pachinko machine 10. The display control unit 60 includes a gaming machine control device designed exclusively for gaming machines. In this embodiment, the display control unit 60 is configured as an electronic circuit board separate from the peripheral control board 420 and the LCD 42. However, it may be configured integrally with the peripheral control board 420 or may be configured integrally with the LCD 42.

  The display control unit 60 is a ROM that stores a drawing control unit 610 that controls each unit of the display control unit 60 based on display commands from the peripheral control board 420 and digital image data 730 used for moving image display on the LCD 42. Based on a VDP command from the drawing control unit 610, a pseudo ROM device 650 receives a video signal for driving the LCD 42 based on a functioning pseudo ROM device 650, a parallel interface 640 for exchanging data with the pseudo ROM device 650 using a parallel transfer method. And an image display processor (Video Display Processor, VDP) 620 generated from 650 digital image data 730. In the present embodiment, the drawing control unit 610 of the display control unit 60 is a computer including electronic components such as a CPU, a ROM, and a RAM. In this embodiment, the video signal output from the VDP 620 of the display control unit 60 to the LCD 42 includes an RGB (Red Green Blue) signal and a SYNC (synchronization) signal. In this embodiment, the digital image data 730 of the pseudo ROM device 650 includes data that is a source of moving image display such as character data and movie data, and is recorded as compressed compressed image data. Details of the pseudo ROM device 650 of the display control unit 60 will be described later.

  The display control unit 60 includes a decompression controller 672, a data distribution circuit 674, a buffer memory 675, and a decompression engine 676 in order to decompress (decompress and decompress) the digital image data 730 from compressed image data to uncompressed data. And a data synthesis circuit 678. In this embodiment, the expansion controller 672 of the display control unit 60 is a computer including a CPU, a ROM, and a RAM. When the decompression controller 672 receives from the drawing control unit 610 a decompression command including information indicating the head address where the digital image data 730 to be decompressed and the amount of data are stored, the decompression controller 672 reads the data from the pseudo ROM device 650. An instructed read command is transmitted to the parallel interface 640. Details of the operation of the expansion controller 672 will be described later.

  The digital image data 730 read from the pseudo ROM device 650 by the parallel interface 640 is divided into a plurality of data by the data distribution circuit 674 and distributed to the plurality of buffer memories 675. In this embodiment, the expansion lines constituting the buffer memory 675 and the expansion engine 676 are prepared as four circuits, and each of the buffer memories 675 has a recording capacity of 3 kilobytes (KB). As a result, a total buffer capacity of 12 KB in total is formed by the four systems. In this embodiment, the digital image data 730 of the pseudo ROM device 650 is read in units of 12 KB for each read command by the parallel interface 640 under the control of the decompression controller 672, and the read digital image data. The data distribution circuit 674 divides the data 730 into four 3 KB pieces from the head data and distributes them to the four buffer memories 675.

The decompression engine 676 of the display control unit 60 is a dedicated data decompression circuit corresponding to the compression format of the digital image data 730. In this embodiment, the data stored in the buffer memory 675 is transferred to the decompression engine 676 by a FIFO (First In, First Out) method, and sequentially decompressed by the decompression engine 676. In this embodiment, when all of the data stored in the buffer memory 675 is delivered to the decompression engine 676, that fact is notified from each of the buffer memories 675 to the decompression controller 672 by an empty flag.
In this embodiment, when all of the data stored in the buffer memory 675 is decompressed by the decompression engine 676, that fact is notified from each of the decompression engines 676 to the decompression controller 672 by an output completion flag. In this embodiment, a plurality of digital image data 730 decompressed by a plurality of decompression engines 676 is synthesized as a series of digital image data 730 by a data synthesis circuit 678.

  The display control unit 60 stores the decompressed digital image data 730 so as to be usable by the VDP 620, two decompression RAMs 636 and 638 for storing the digital image data 730 synthesized by the data synthesis circuit 678, and the decompression. Each of the RAMs 636 and 638 includes a data switch circuit 634 and a bus switch circuit 634 for switching the memory bus connection with the VDP 620. In this embodiment, the bus switch circuit 634 of the display control unit 60 can simultaneously execute memory access to one of the decompression RAMs 636 and 638 by the data synthesis circuit 678 and memory access to the other of the decompression RAMs 636 and 638 by the VDP 620. Based on an instruction from the drawing control unit 610, the memory bus connection to each of the decompression RAMs 636 and 638 is switched. By switching the memory bus connection by the bus switch circuit 634, each of the address spaces in the expansion RAMs 636 and 638 is associated with the same logical block address space used by the VDP 620 for memory access. Is recognized as a single RAM. As a result, the writing of the digital image data 730 by the data synthesis circuit 678 and the reading of the digital image data 730 by the VDP 620 can be executed simultaneously, and the compressed digital image data 730 is efficiently transferred from the pseudo ROM device 650 to the VDP 620. Can be stretched and transmitted.

A-3. Detailed configuration of pseudo ROM device 650 in display control unit 60:
FIG. 4 is a block diagram mainly showing a detailed configuration of the pseudo ROM device 650 in the display control unit 60. The pseudo ROM device 650 of the display control unit 60 is a gaming device memory device designed exclusively for gaming machines, and is a NAND type flash memory in which digital image data 730 is recorded and exchanged by serial transfer. A serial interface 657 for exchanging data with the NAND flash memory 660 by a serial transfer method, a relay CPU 652 for controlling each part of the pseudo ROM device 650, and a relay program 710 in which the operation of the relay CPU 652 is defined in advance. A relay memory 656 that stores data, a relay RAM 654 that temporarily stores data handled by the relay CPU 652, and a pseudo ROM interface 658 that exchanges data with the parallel interface 640 as a ROM device. In this embodiment, the pseudo ROM device 650 is electrically insulative with the NAND flash memory 660, the relay CPU 652, the relay RAM 654, the relay memory 656, the pseudo ROM interface 658, and the serial interface 657 as a single package. Electronic parts sealed with resin. Details of the operation of the relay CPU 652 of the pseudo ROM device 650 will be described later.

  The pseudo ROM interface 658 of the pseudo ROM device 650 is a write that accepts an input of a write signal indicating whether data can be written to the NAND flash memory 660 as one of various terminals electrically connected to the display control unit 60. A terminal 659 is provided. In the present embodiment, in the pseudo ROM device 650 mounted on the display control unit 60, the write terminal 659 of the pseudo ROM interface 658 is connected to the ground, so that the write signal input to the write terminal 659 is binary. It is always maintained at the “low level (0)” of the signal.

  The NAND flash memory 660 of the pseudo ROM device 650 has a plurality of physical data blocks to which a series of physical block addresses are assigned in the order of physical memory arrangement. In this embodiment, the NAND flash memory 660 has a storage area of 64 pages per physical data block, a user data area of 2048 bytes (that is, 2 KB) per page, and a redundancy area of 64 bytes. Yes. In this embodiment, the NAND flash memory 660 is designed to accept data reading and writing in units of one page (that is, in units of 2 KB). The physical data blocks of the NAND flash memory 660 include “good blocks” in which data can be physically recorded and “bad blocks” in which data cannot be physically recorded. The digital image data 730 is stored in the user data area in the good block. In this embodiment, when a physical block is a defective block, a flag indicating the defective block is written in the redundant area of the physical block. In this embodiment, the digital image data 730 of the pseudo ROM device 650 is transferred by a pseudo ROM writer (not shown) that exchanges data with the pseudo ROM interface 658 of the pseudo ROM device 650 prior to mounting on the display control unit 60. To be recorded.

  In the NAND flash memory 660 of the pseudo ROM device 650, an address correspondence table 720 in which address correspondence between the pseudo ROM interface 658 and the NAND flash memory 660 is defined is recorded in advance. The address correspondence table 720 is data prepared in advance for each NAND flash memory 660 installed in the pseudo ROM device 650 according to the storage state of the digital image data 730 in the NAND flash memory 660. In this embodiment, the address correspondence table 720 is stored in the user data area in the good block to which the physical block address preceding the good block in which the digital image data 730 is recorded is assigned.

  FIG. 5 is an explanatory diagram showing an example of the address correspondence table 720 stored in the relay memory 656. The address correspondence table 720 includes a series of logical block addresses 722 used by the parallel interface 640 for data exchange, a series of physical block addresses 724 in the NAND flash memory 660, and each physical block address is a good block or a bad block. The block status 726 indicating the stored data 728 recorded in each physical block address is shown, and the series of logical block addresses 722 is associated with the physical block address of the good block in which the digital image data 730 is recorded. It has been.

  In this embodiment, the NAND flash memory 660 has 10,000 physical data blocks, and 10,000 physical block addresses from “PBA0000” to “PBA9999” are stored in these physical data blocks. The type flash memory 660 is assigned in order of physical memory arrangement. In this embodiment, the NAND flash memory 660 records digital image data 730 indicated by codes from “GD0000” to “GD9799” corresponding to the data amount of 9800 physical data blocks. In the present embodiment, 9800 logical block addresses from “LBA0000” to “LBA9799” are prepared in accordance with the amount of digital image data 730 recorded in the NAND flash memory 660.

  In this embodiment, the digital image data 730 is sequentially recorded in the NAND flash memory 660 in the order of a series of physical block addresses following the address correspondence table 720, and the physical data block to be recorded is a defective block. In this case, data to be recorded after the defective block is sequentially recorded after the good block following the defective block. In the example shown in FIG. 5, the address correspondence table 720 is recorded in the physical data block of the physical block address PBA0000 which is the first good block. In the example shown in FIG. 5, digital image data GD0000 to GD0002 are sequentially recorded in physical data blocks of physical block addresses PBA0001 to PBA0003, which are good blocks following the good block in which the address correspondence table 720 is recorded. The physical data block of physical block address PBA0004 is skipped, and the digital image data “GD0003” is recorded in the physical data block of physical block address PBA0005, which is a subsequent good block, and the subsequent digital image data is sequentially recorded in the same manner. Has been.

  In this embodiment, the series of logical block addresses 722 are sequentially associated with a series of physical block addresses in which the physical block addresses of good blocks in which the digital image data 730 is recorded are arranged in ascending order. In the example shown in FIG. 5, the logical block address LBA0000 is associated with the physical block address PBA0001, the logical block address LBA0001 is associated with the physical block address PBA0002, and the logical block address LBA0002 is associated with the physical block address PBA0003. The logical block address LBA0003 skips the physical block address PBA0004, which is a bad block, and is associated with the physical block address PBA0005, and the subsequent logical block addresses are sequentially associated with the physical block addresses in the same manner.

A-4. Operation of the pachinko machine 10 in the first embodiment:
FIG. 6 is a flowchart showing an expansion control process executed by the expansion controller 672 of the display control unit 60. When a decompression command is output from the drawing control unit 610, the decompression controller 672 of the display control unit 60 starts the decompression control process illustrated in FIG.

  When the expansion controller 672 starts the expansion control processing shown in FIG. 6, the expansion controller 672 receives an expansion command from the drawing control unit 610 (step S610). In the present embodiment, in the decompression command from the drawing control unit 610, the top address on the pseudo ROM device 650 and the data amount thereof are specified using the logical block address 722, and thereby, the pseudo ROM device 650 is specified. The digital image data 730 to be read and decompressed is specified.

  After receiving the decompression command (step S610), the decompression controller 672 prepares a read command that instructs reading of the digital image data 730 from the pseudo ROM device 650 (step S620). The amount of digital image data 730 that is instructed to be read by this read command is the amount of data within the total buffer capacity of the plurality of buffer memories 675, and is an integer multiple of the page capacity of the NAND flash memory 660 in the pseudo ROM device 650. Specified by the amount of data. In this embodiment, a total buffer capacity of 12 KB is configured by the plurality of buffer memories 675, and the page capacity of the NAND flash memory 660 is 2 KB. Therefore, 12 KB of digital image data 730 obtained by multiplying the page capacity by six is stored in one unit. Reading is instructed by one read command. For example, when 64 KB digital image data 730 is designated in the decompression command, the decompression controller 672 instructs to read out the first 12 KB of the 64 KB with the read command.

  The decompression controller 672 prepares a read command (step S620), and then transmits the read command to the parallel interface 640 (step S630). Thereafter, the decompression controller 672 determines whether or not a read command has been transmitted to the parallel interface 640 for all of the digital image data 730 designated to be read by the decompression command (step S640).

  When the read command is not transmitted for all data, for example, when only the first 12 KB of the 64 KB data amount specified in the decompression command is transmitted (step S640), the decompression controller 672 It is determined whether all of the digital image data 730 read from the pseudo ROM device 650 to the buffer memory 675 has been delivered to the decompression engine 676 (step S650). In this embodiment, the decompression controller 672 determines whether all the data in the buffer memory 675 has been delivered to the decompression engine 676 based on the value output as an empty flag from the buffer memory 675.

  When all the data on the buffer memory 675 has been delivered to the decompression engine 676 (step S650), the decompression controller 672 prepares a read command for the subsequent digital image data 730 that is not instructed to be read by the read command (step S650). S660). For example, when only the read command for the first 12 KB of the 64 KB data amount specified in the decompression command is transmitted, the decompression controller 672 reads the 12 KB subsequent to the data designated by the preceding read command. Prepare the command. The decompression controller 672 prepares a read command for subsequent data (step S660), and then transmits the read command to the parallel interface 640 (step S630). Thereafter, the decompression controller 672 repeats transmission of the read command until it transmits a read command for all of the digital image data 730 designated to be read by the decompression command (step S640). As a result, the data reading process from the pseudo ROM device 650 by the parallel interface 640 proceeds by alternately repeating stop and restart.

  When the expansion controller 672 transmits a read command for all of the digital image data 730 designated to be read by the expansion command (step S640), the expansion controller 672 determines whether or not all the data has been expanded by the expansion engine 676 (step S670). . In the present embodiment, the decompression controller 672 determines whether or not all data read and designated by the decompression command has been decompressed based on the value output as the output completion flag from the decompression engine 676. When all the data designated to be read by the decompression command has been decompressed (step S670), the decompression controller 672 responds to the drawing control unit 610 (step S680).

  FIG. 7 is a flowchart showing a startup process executed by the relay CPU 652 of the pseudo ROM device 650. The relay CPU 652 of the pseudo ROM device 650 starts the startup process shown in FIG. 7 when power is supplied to the pseudo ROM device 650.

  When the activation process shown in FIG. 7 is started, the relay CPU 652 reads the relay program 710 stored in advance in the relay memory 656 from the relay memory 656 to the relay RAM 654, and activates the read relay program 710 (step S310). After the relay program 710 is activated, the relay CPU 652 determines whether or not an initialization signal indicating an instruction to initialize the storage area of the NAND flash memory 660 is input to the pseudo ROM interface 658 (step S315). In this embodiment, the initialization signal is a signal output to the pseudo ROM device 650 from a pseudo ROM writer (not shown) that writes the digital image data 730, and the pseudo ROM device 650 displays the display of the pachinko machine 10. When the controller 60 is mounted, the initialization signal is not input to the pseudo ROM device 650.

  When the initialization signal is not input (step S315), for example, when the pseudo ROM device 650 is mounted on the display control unit 60, or the pseudo ROM writer connected to the pseudo ROM device 650 (not shown). Is not outputting the initialization signal, the relay CPU 652 reads the address correspondence table 720 recorded in the NAND flash memory 660 from the NAND flash memory 660 to the relay RAM 654 via the serial interface 657 (step S320). .

  On the other hand, when an initialization signal is input (step S315), for example, when a pseudo ROM writer (not shown) connected to the pseudo ROM device 650 outputs an initialization signal, the relay CPU 652 performs the NAND flash memory. The storage area in 660 is initialized (step S350). Thereafter, the relay CPU 652 determines good blocks and bad blocks for a plurality of physical data blocks included in the NAND flash memory 660 (step S360), and newly creates an address correspondence table 720. Thereafter, the relay CPU 652 stores the new address correspondence table 720 in the relay RAM 654 (step S380).

  FIG. 8 is a flowchart showing a read relay process executed by the relay CPU 652 of the pseudo ROM device 650. When the data read signal is input to the pseudo ROM interface 658, the relay CPU 652 starts the read relay process shown in FIG. In this embodiment, prior to the read relay process of FIG. 8, when the pachinko machine 10 is powered on, the address correspondence table 720 is stored in the relay RAM 654 (steps S320 and S380 of FIG. 7).

  When the relay CPU 652 starts the read relay process shown in FIG. 8, the relay CPU 652 receives a read signal from the pseudo ROM interface 658 (step S110). Thereafter, the relay CPU 652 refers to the address correspondence table 720 stored in the relay RAM 654 and identifies the physical block address associated with the logical block address specified by the received read signal (step S120). Thereafter, the relay CPU 652 reads the digital image data 730 recorded at the specified physical block address from the NAND flash memory 660 via the serial interface 657 (step S130). Thereafter, the relay CPU 652 provides the read digital image data 730 to the parallel interface 640 of the display control unit 60 that is external to the pseudo ROM device 650 via the pseudo ROM interface 658 (step S140).

  FIG. 9 is a flowchart showing a write relay process executed by the relay CPU 652 of the pseudo ROM device 650. When a data write signal (for example, a signal from the pseudo ROM writer) is input to the pseudo ROM interface 658, the relay CPU 652 starts the write relay process shown in FIG. In this embodiment, prior to the write relay process of FIG. 9, when the pachinko machine 10 is powered on, the address correspondence table 720 is stored in the relay RAM 654 (steps S320 and S380 of FIG. 7).

  When the relay CPU 652 starts the write relay process shown in FIG. 9, the relay CPU 652 receives a write signal from the pseudo ROM interface 658 (step S210). Thereafter, the relay CPU 652 determines whether or not the write signal input to the write terminal 659 of the pseudo ROM interface 658 is at a high level (1) (step S215).

  When the write signal input to the write terminal 659 is at a low level (0), for example, when the pseudo ROM device 650 is mounted on the display control unit 60 (step S215), the relay CPU 652 starts from the pseudo ROM interface 658. The write relay process is terminated without executing data writing based on the received write signal.

  On the other hand, when the write signal input to the write terminal 659 is at a high level (1), for example, the digital image data 730 is recorded in the pseudo ROM device 650 by the pseudo ROM writer prior to mounting on the display control unit 60. In this case (step S215), the relay CPU 652 refers to the address correspondence table 720 stored in the relay RAM 654 and refers to the physical block associated with the logical block address designated for writing by the write signal received from the pseudo ROM interface 658. An address is specified (step S220). Thereafter, the relay CPU 652 writes the digital image data 730 included in the write signal to the physical block address specified by the address correspondence table 720 via the serial interface 657 (step S230).

  Thereafter, the relay CPU 652 reads data from the same physical block address where the writing was performed, and compares the written data with the read data, thereby verifying whether or not the digital image data 730 has been recorded correctly. Execute (Step S240).

  When the writing failure is confirmed by the verification (step S245), the relay CPU 652 corrects the address correspondence table 720 stored in the relay RAM 654 (step S250). In this embodiment, a good block for which a write failure has been confirmed is changed to a defective block by correcting the address correspondence table 720, and a logical data block associated with the physical data block corresponds to another good block. Attached. After the address correspondence table 720 stored in the relay RAM 654 is modified (step S250), the relay CPU 652 refers to the modified address correspondence table 720 and rewrites the digital image data 730 (step S260). Thereafter, the relay CPU 652 re-executes the processing from the verification (step S240).

  On the other hand, if the write failure is not confirmed by the verify (step S245), the relay CPU 652 repeats the processing from the determination of the write signal (step S215) for the subsequent data in order to write all the data specified to be written in the write signal. This is executed (step S247). When all the data designated to be written in the write signal is recorded in the NAND flash memory 660 (step S247), the relay CPU 652 records the address correspondence table 720 stored in the relay RAM 654 in the NAND flash memory 660 ( Step S270).

  FIG. 10 is a flowchart showing table update processing executed by the relay CPU 652 of the pseudo ROM device 650. In this embodiment, the relay CPU 652 of the pseudo ROM device 650 periodically executes the table update process of FIG. When the relay CPU 652 starts the table update process in FIG. 10, the address correspondence table 720 is not initialized at the time of activation (step S410, step S320 in FIG. 7), or data is written after the initialization. When the address correspondence table 720 is recorded in the NAND flash memory 660 (step S420, step S270 in FIG. 9), the address correspondence table 720 recorded in the NAND flash memory 660 is transferred from the NAND flash memory 660 to the serial interface 657. To the relay RAM 654, the address correspondence table 720 of the relay RAM 654 is overwritten (step S430).

  According to the pachinko machine 10 described above, the digital image data 730 is temporarily read from the pseudo ROM device 650 according to the storage capacity of the buffer memory 675 by the expansion control processing of FIG. 6 executed by the expansion controller 672. Therefore, digital image data larger than the storage capacity of the buffer memory 675 can be expanded and used for moving image display. Also, reading of the digital image data 730 from the pseudo ROM device 650 is performed in units of pages of the NAND flash memory 660, which is a data unit that can be read and accessed to the pseudo ROM device 650, according to the storage capacity of the buffer memory 675. Since the processing is executed in a divided manner, the processing efficiency from the reading of the digital image data 730 to the expansion can be improved. In addition, since the expansion of the digital image data 730 to the uncompressed data can be distributed over a plurality of lines constituting the buffer memory 675 and the expansion engine 676, the speed of the expansion process of the digital image data 730 can be improved. it can.

  Since a series of physical block addresses in which physical block addresses of good blocks in which the digital image data 730 is recorded in the NAND flash memory 660 are arranged are associated with logical block addresses handled by the parallel interface 640, the parallel interface 640 The digital image data 730 can be read out from the NAND flash memory 660 via. Therefore, in the pachinko machine 10, the NAND flash memory 660 can be used as a recording medium for the digital image data 730.

  Further, the pseudo ROM device 650 includes the NAND flash memory 660, the relay CPU 652, the relay RAM 654, the relay memory 656, the pseudo ROM interface 658, and the serial interface 657 as a single package. The NAND flash memory 660 in which the data 730 is recorded can be handled in the same manner as a mask ROM that can access data by the parallel interface 640. In the case of a NOR type flash memory, if the storage capacity changes, the number of address lines changes as the number of storage elements increases. However, in the case of a NAND type flash memory, the address lines and data lines are combined. Therefore, since the number of signal lines does not change, it can be understood that it is better to provide the serial interface 657 on the VDP side. However, the memory for storing the character image in the pachinko machine is inspected by a third party at the application stage for the pachinko machine. Therefore, it is necessary to be able to confirm the data contents using a ROM checker or the like in a state of being removed from the pachinko machine. For this reason, a memory in which a bat block may occur, such as a NAND-type flash memory, does not have a function for managing a normal memory area other than the bat block (such as the relay CPU 652) on the memory side. It becomes impossible to confirm the data contents of. Therefore, it is useful that the relay CPU 652 and the like are integrated with the NAND flash memory.

  In addition, since address conversion between the parallel interface 640 and the NAND flash memory 660 is performed based on the address correspondence table 720 read from the NAND flash memory 660 to the relay RAM 654, the address conversion on the NAND flash memory 660 is performed. Therefore, it is possible to improve the reading speed of the digital image data 730 from the NAND flash memory 720 rather than performing address conversion with reference to the address correspondence table 720. As a result, the NAND flash memory 660 in which the digital image data 730 is recorded can be handled as a mask ROM that allows data access from the parallel interface 640.

  Further, since the address conversion between the parallel interface 640 and the NAND flash memory 660 is executed based on the address correspondence table 720 stored in the relay RAM 654, the writing speed of the digital image data to the NAND flash memory 660 is increased. Can be improved.

  When the digital image data 730 is written to the NAND flash memory 660, the written data is verified (step S240). If a write failure is detected, the address correspondence table 720 is corrected and the data is rewritten. Is executed (step S260), it is possible to prevent recording failure of the digital image data 730 in the NAND flash memory 660.

  Further, whether or not data can be written to the NAND flash memory 660 from the outside of the pseudo ROM device 650 can be managed by a write signal input to the write terminal 659. The write terminal 659 of the pseudo ROM device 650 mounted on the display control unit 60 is connected to the ground, so that data writing to the NAND flash memory 660 is always prohibited. Thus, it is possible to prevent the digital image data 730 written in the NAND flash memory 660 from being altered without performing complicated control on the pseudo ROM device 650.

  Further, since the address correspondence table 720 stored in the relay RAM 654 is periodically overwritten (step S430), even if the address correspondence table 720 on the relay RAM 654 is damaged by noise such as static electricity or radio waves, Since the address correspondence table 720 is periodically updated, reading errors of the digital image data 730 can be suppressed. Conventionally, the interface for connecting the character ROM to the VDP is a parallel interface in which the address bus and the data bus are independent, and is configured as a random access interface capable of randomly accessing the character ROM. In recent years, in gaming machines, the amount of image information handled by gaming machines tends to increase. The present invention provides a technique using a flash memory as one means corresponding to the increase in the amount of image information. There are two types of flash memory: NOR type and NAND type. The NOR type flash memory can perform random access faster than the NAND type, and if the NOR type flash memory is used in a gaming machine, it can be easily connected to an existing interface in the gaming machine. NAND flash memory is more advantageous than NOR type in terms of capacity increase and miniaturization, and is superior in cost performance per storage capacity. However, the NAND flash memory is compatible with a serial interface that uses both the address bus and the data bus to exchange data continuously, so it is not easy to connect to an existing interface in a gaming machine. . Conventionally, there is a gaming machine that uses a sequential ROM that can be connected to a serial interface to store image information in the gaming machine, but it is inferior to a flash memory in terms of access speed. In the pachinko machine, an image is displayed on the liquid crystal display device in a timely manner based on the progress of the game, and the result of the internal lottery in the pachinko machine is shown funny and invites the player's interest. Therefore, the image may be suddenly changed, and in that case, it is important how quickly necessary image information can be read out. In that respect, it is desirable to employ a flash memory rather than a sequential ROM, and it is desirable to employ a NAND flash memory from the viewpoint of storage capacity. However, in the case of a NAND flash memory, it is necessary to manage the bat block, which is inconvenient to use. In this respect, device manufacturers have been researching about increasing the capacity of the NOR type, and if the capacity increases, it can be replaced with a NOR type flash memory as it is, I can say that.

B. Second embodiment:
The configuration of the pachinko machine 10 in the second embodiment is a pseudo ROM instead of the write terminal 659 of the pseudo ROM interface 658 or together with the write terminal 659 in order to manage prohibition of data writing to the NAND flash memory 660. Except for having a write flag 715 set inside the device 650, it is the same as in the first embodiment.

  FIG. 11 is a block diagram mainly showing a detailed configuration of the pseudo ROM device 650 in the pachinko machine 10 of the second embodiment. In addition to the address correspondence table 720 and the digital image data 730, the NAND flash memory 660 of the pseudo ROM device 650 mounted on the display control unit 60 in the second embodiment writes data to the NAND flash memory 660. A write flag 715 indicating availability is recorded in advance in the same good block as the address correspondence table 720. In this embodiment, the write flag 715 is binary data represented by “0” and “1”. When “0”, the write flag 715 indicates that data can be written to the NAND flash memory 660, Indicates that data cannot be written to the data NAND flash memory 660. In this embodiment, the write flag 715 is preset with a value of “1” in the NAND flash memory 660 of the pseudo ROM device 650 mounted on the display control unit 60.

  In this embodiment, the write flag 715 of the pseudo ROM device 650 is received from a pseudo ROM writer (not shown) that exchanges data with the pseudo ROM interface 658 of the pseudo ROM device 650 prior to mounting on the display control unit 60. Recorded based on the flag change signal. In this embodiment, the relay CPU 652 of the pseudo ROM device 650 acquires the total capacity value of data that is to be written to the pseudo ROM device 650 from the connected pseudo ROM writer (not shown), and then acquires the acquired total capacity value. Until a good block corresponding to the above is secured, a defective block of the NAND flash memory 660 is detected, an address correspondence table 720 is created based on the detection result of the defective block, and the address correspondence table 720 is created for the first good block. Write. In this embodiment, the relay CPU 652 sets the write flag 715 to “0” based on the flag change signal from the pseudo ROM writer (not shown) and then the digital image data 730 from the pseudo ROM writer (not shown). According to the write signal, the digital image data 730 is recorded in the NAND flash memory 660 while avoiding the defective block. Thereafter, the relay CPU 652 sets the write flag 715 to “1” based on a flag change signal from a pseudo ROM writer (not shown). Thereafter, the pseudo ROM device 650 is mounted on the display control unit 60.

  The operation of the pachinko machine 10 in the second embodiment is performed except that the write relay process is performed based on the write flag 715 set inside the pseudo ROM device 650 instead of the write terminal 659 of the pseudo ROM interface 658. The operation is the same as that of the first embodiment.

  FIG. 12 is a flowchart showing the write relay process executed by the relay CPU 652 of the pseudo ROM device 650 in the second embodiment. When a data write signal is input to the pseudo ROM interface 658, the relay CPU 652 starts the write relay process shown in FIG. In this embodiment, prior to the write relay process of FIG. 12, when the pachinko machine 10 is powered on, the address correspondence table 720 is stored in the relay RAM 654 (steps S320 and S380 of FIG. 7).

  When the relay CPU 652 starts the write relay process shown in FIG. 12, the relay CPU 652 receives a write signal from the pseudo ROM interface 658 (step S510). Thereafter, the relay CPU 652 determines whether or not the write flag 715 is at a high level (1) (step S515).

  When the write flag 715 is at the high level (1), for example, when the pseudo ROM device 650 is mounted on the display control unit 60 (step S515), the relay CPU 652 is based on the write signal received from the pseudo ROM interface 658. The write relay process is terminated without executing data writing.

  On the other hand, when the write flag 715 is at the low level (0), for example, when the digital image data 730 is recorded in the pseudo ROM device 650 prior to mounting on the display control unit 60 (step S515), the relay CPU 652 With reference to the address correspondence table 720 stored in the relay RAM 654, the physical block address associated with the logical block address designated for writing by the write signal received from the pseudo ROM interface 658 is specified (step S220). Thereafter, the relay CPU 652 executes the writing of the digital image data 730 as in the write relay process of FIG.

  According to the pachinko machine 10 in the second embodiment described above, as in the first embodiment, the NAND type is more effective than the address conversion by referring to the address correspondence table 720 on the NAND flash memory 660. The reading speed of the digital image data 730 from the flash memory 720 can be improved. Further, whether or not data can be written to the NAND flash memory 660 from the outside of the pseudo ROM device 650 can be managed by a write flag 715 set inside the pseudo ROM device 650. The write flag 715 of the pseudo ROM device 650 mounted on the display control unit 60 is set to a value of “1” in advance, so that data writing to the NAND flash memory 660 is always prohibited. Thus, it is possible to prevent the digital image data 730 written in the NAND flash memory 660 from being altered without performing complicated control on the pseudo ROM device 650.

C. Other embodiments:
Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and can of course be implemented in various forms without departing from the spirit of the present invention. is there. For example, the lines constituting the buffer memory 675 and the decompression engine 676 are not limited to a plurality, and may be a single line.

  The NAND flash memory 660 is not limited to the one in which digital image data is sequentially recorded by skipping defective blocks, and the digital image data is recorded using an alternative block in which the defective block is replaced with another good block. It may be what was done.

FIG. 13 is an explanatory diagram illustrating an example of the address correspondence table 720 stored in the relay memory 656 according to another embodiment. In the NAND flash memory 660 managed by the address correspondence table 720 in FIG. 13, a part of the good block is prepared as a substitute block, and the digital image data 730 is stored in the NAND flash memory 660 in the order of a series of physical block addresses. If the physical data block that is sequentially recorded and recorded is a defective block, the data to be recorded in the defective block is recorded in the alternative block.
In the example shown in FIG. 13, digital image data GD0000 to GD0002 are sequentially recorded in the physical data blocks of physical block addresses PBA0001 to PBA0003 that are good blocks, and are recorded in the physical data block of physical block address PBA0004 that is a defective block. The digital image data GD0003 to be recorded is recorded in the physical data block of the physical block address PBA9999 which is a substitute block, and the subsequent digital image data is sequentially recorded in the same manner. In the example illustrated in FIG. 13, the series of logical block addresses 722 are sequentially associated with a series of physical block addresses in which physical block addresses of good blocks in which digital image data is recorded are arranged in the storage order of the digital image data. For example, the logical block address LBA0003 is associated with a physical block address PBA9999 that is an alternative block corresponding to the defective block of the physical block address PBA0003.

  In this embodiment, the digital image data 730 recorded in the NAND flash memory 660 is compressed data. However, in another embodiment, the digital image data 730 recorded in the NAND flash memory 660 is uncompressed data. It may be. In this embodiment, the prohibition of data writing to the NAND flash memory 660 is realized by an operation based on the software of the relay CPU 652, but the functions of the relay CPU 652 and the like are configured in hardware by an ASIC (Application Specific Integrated Circuit). It may be realized by doing. In this embodiment, when the write signal input to the write terminal 659 is a high level (1) value, it indicates that data can be written to the NAND flash memory 660 and is a low level (0) value. In this embodiment, it is indicated that data cannot be written to the NAND flash memory 660. However, in another embodiment, when the value is low level (0), data can be written to the NAND flash memory 660 and high level (1 ) May indicate that data cannot be written to the NAND flash memory 660. In this embodiment, the write flag 715 set in the pseudo ROM device 650 indicates that data can be written to the NAND flash memory 660 when the low level (0) value, and the high level (1) value. In this case, it is indicated that data cannot be written to the NAND flash memory 660. However, in another embodiment, when the value is high level (1), the data can be written to the NAND flash memory 660 and low level is indicated. A value of (0) may indicate that data cannot be written to the NAND flash memory 660.

  In this embodiment, the logical block address is directly associated with the physical block address in the address correspondence table 720 of FIGS. 5 and 13. However, as another embodiment, individual logical block addresses are used. May be associated as an offset value indicating a difference from the value of the corresponding logical block address. For example, in the correspondence relationship shown in FIG. 13, in the address correspondence table 720, the logical block address LBA0000 is associated with an offset value “1” indicating the difference between the physical block address PBA0001 and the logical block address LBA0003. And an offset value “9996” indicating a difference in address value from the physical block address PBA9999.

DESCRIPTION OF SYMBOLS 10 ... Pachinko machine 20 ... Outer frame 30 ... Inner frame 32 ... Handle 34 ... Speaker 36 ... Production sensor 40 ... Game panel 42 ... LCD
44 ... Winning slot 442 ... Game ball sensor 444 ... Winning slot drive unit 45 ... Direction drive unit 46 ... Electric decoration unit 462 ... LED
47 ... Production sensor 50 ... Glass frame 55 ... Speaker 56 ... Illumination part 562 ... LED
DESCRIPTION OF SYMBOLS 80 ... Card unit 310 ... Discharge control board 410 ... Main control board 420 ... Peripheral control board 430 ... Panel lighting board 440 ... Peripheral distribution board 450 ... Frame lighting board 60 ... Display control part 610 ... Drawing control part 620 ... VDP
634 ... bus switch circuit 636, 638 ... expansion RAM
640 ... Parallel interface 650 ... Pseudo ROM device 652 ... Relay CPU
654 ... Relay RAM
656 ... Relay memory 657 ... Serial interface 658 ... Pseudo ROM interface 659 ... Write terminal 660 ... NAND flash memory 672 ... Expansion controller 674 ... Data distribution circuit 675 ... Buffer memory 676 ... Expansion engine 678 ... Data composition circuit 710 ... Relay program 715 ... write flag 720 ... address correspondence table 722 ... logical block address 724 ... physical block address 726 ... block state 728 ... stored data 730 ... digital image data

Claims (5)

A control device for a gaming machine that outputs a video signal for displaying a moving image on a display screen of a gaming machine,
A memory device that records compressed image data obtained by compressing digital image data used for the video signal;
An image designating unit for designating compressed image data recorded in the memory device;
An image read unit that executes a read process of reading compressed image data designated by the image designation unit from the memory device;
A buffer memory for temporarily storing compressed image data read from the memory device by the image read unit;
An image decompression unit for decompressing the compressed image data stored in the buffer memory into the digital image data;
A read stop unit that temporarily stops the progress of the read process each time a data amount corresponding to the storage capacity of the buffer memory is read from the memory device by the image read unit;
A game machine control comprising: a read resumption unit that resumes the progress of the read process stopped by the read stop unit when all of the compressed image data stored in the buffer memory is delivered to the image expansion unit apparatus.   The read stop unit has a data amount within the storage capacity of the buffer memory, and a data amount obtained by multiplying a data unit accessible to the memory device by an integer is read from the memory device by the image read unit. The gaming machine control device according to claim 1, wherein the progress of the read process is temporarily stopped every time the game is executed. The gaming machine control device according to claim 1, further comprising:
A plurality of expansion lines constituting the buffer memory and the image expansion unit;
A data distribution unit that distributes compressed image data read from the memory device by the image read unit to each of the buffer memories in the plurality of decompression lines;
A game machine control device comprising: a data synthesis unit that synthesizes the digital image data from data decompressed by each of the image decompression units in the plurality of decompression lines. A control device for a gaming machine according to any one of claims 1 to 3,
The image read unit includes a parallel interface for exchanging data by parallel transfer,
The memory device is
NAND type flash memory in which the compressed image data is recorded and data is exchanged by serial transfer;
A gaming machine control device comprising: a relay unit that relays data transfer between the NAND flash memory and the parallel interface.   A gaming machine comprising the gaming machine control device according to any one of claims 1 to 4.