JP6262296B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that performs a lottery process resulting from a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image effect.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP2012-095836A JP 2012-125332 A

  In this type of gaming machine, high image quality and advanced image production are particularly desired. However, in the conventional configuration, a computer circuit that receives a control command from another control unit and a VDP circuit that outputs an image signal to the display device are separate configurations, and there is a limit in executing advanced image effects. .

  Although it is known that the computer circuit and the VDP circuit are integrated into a single electronic element (Patent Document 1, Patent Document 2), the computer circuit and the VDP circuit smoothly cooperate to produce an image effect smoothly. There is no known configuration to proceed to.

  This invention is made in view of said subject, Comprising: It aims at providing the gaming machine which can implement | achieve the clear image production of high image quality.

In order to achieve the above object, the present invention is a gaming machine that executes an image effect corresponding to a lottery result of a predetermined lottery process, an image effect control means for centrally controlling the image effect, and an image effect. Data storage means for storing compressed data as constituent elements of still images and / or moving pictures constituting the image, and image data generated based on the compressed data instructed by the image effect control means to the display device The image generation control means is provided with a list generation means for generating a drawing list for specifying a display screen of the display device for each predetermined operation cycle. The image generation means refers to the drawing list generated by the image effect control means, acquires necessary compressed data from the data storage means and stores it in the buffer area. And preload means for changing the drawing list to identify the, operates intermittently for each of the operation period, with reference to the modified draw list, obtains the necessary data from the buffer area, corresponding to the drawing list The image data to be generated is generated in either one of the pair of frame buffers, and the image data is generated intermittently in each of the operation cycles, and the drawing device generates in one of the pair of frame buffers in the preceding operation cycle . Output means for outputting image data to a display device, and the preload means compresses the display screen for one frame or a plurality of frames when the compressed data required for the drawing means does not exist in the buffer area. Data is read from the data storage means and temporarily stored in the buffer area.

  According to the gaming machine of the present invention described above, it is possible to realize a clear image effect with high image quality.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of 1st Example. FIG. 4 is a block diagram illustrating a circuit configuration of an effect control unit and an image control unit. 2 is a diagram illustrating a configuration of a timepiece IC. It is a block diagram which shows the internal structure of the composite chip in charge of the image production of 1st Example. It is a block diagram which shows the internal structure of a HSS controller. It is drawing explaining the HSS controller which is a host side, and the operation procedure on the device side. 5 is a flowchart for explaining the internal operation of the composite chip and a drawing for explaining the operation of the display circuit. It is drawing explaining the operation | movement content of each part of a composite chip. It is a block diagram which shows the whole structure of the pachinko machine of 2nd Example. It is a block diagram which shows a part of FIG. 11 in detail. It is drawing explaining the internal structure of the composite chip | tip in 2nd Example. It is drawing explaining the internal operation | movement content of the composite chip | tip in 3rd Example. It is drawing explaining the internal operation | movement content of the composite chip | tip in 4th Example.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A main display device DS1 composed of a large liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is disposed on the right side of the main display device DS1. DS2 is arranged. The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  The sub display device DS2 normally displays the image information in a stationary state in which the display screen is inclined at an angle that is easy for the player to see. However, at the time of a predetermined notice effect, while moving to the left side of the figure while changing the inclination angle to an angle that is easy for the player to see, a predetermined notice image is displayed.

  That is, the sub display device DS2 of the embodiment functions not only as a display device but also as a movable effect body that executes a notice effect. Here, the announcement effect by the sub display device DS2 is set with high reliability, and the player pays attention to the moving operation of the sub display device DS2 with a great sense of expectation.

  By the way, in the game area where the game ball falls and moves, the first symbol starting port 15a, the second symbol starting port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18 are used. Is arranged. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  That is, when a game ball is won at the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. After that, when the predetermined big hit symbol is aligned with the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., which game value is given based on the lottery result according to the winning timing of the game ball in advance It is determined.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. A main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD received from the effect control board 22 The image control board 23 that drives the two display devices DS1 and DS2 based on 'and the payout control board 24 that controls the payout motor M based on the control command CMD "received from the main control board 21 to pay out the game ball. And a launch control board 25 that launches a game ball in response to the player's operation.

  As illustrated, the control command CMD output from the main control board 21 is transmitted to the effect control board 22. The control command CMD ″ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every two 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel with a 16-bit length. Even when such control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  As shown in the figure, in this embodiment, a liquid crystal interface board 28 accessible from the image control board 23 and the effect control board 22 is provided. The liquid crystal interface board 28 is equipped with a clock circuit (real time clock) RTC capable of measuring the current time and a memory element (Static Random Access Memory) SRAM for storing game performance information.

  In this embodiment, the image control board 23 drives the main display device DS1 and the sub display device DS2 via the liquid crystal interface board 28 on which an LVDS receiving circuit and the like are mounted. Here, the liquid crystal interface board 28 and the image control board 23 are directly connected to the male connector and the female connector without going through a wiring cable. Similarly, for the effect control board 23 and the liquid crystal interface board 28, the male connector and the female connector are directly connected without going through the wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  A computer circuit such as a one-chip microcomputer is mounted on each of the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24. Therefore, the control board 21 to 24 and the circuit mounted on the liquid crystal interface board 28 and the operations realized by the circuit are collectively referred to as a function. 22, image control unit 23, and payout control unit 24. Note that, with respect to the main control unit 21, all or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 become sub-control units.

  This pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display devices DS1 and DS2 and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as they are. Then, the effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputer 40 and the image control section of the effect control unit 22 by this power supply reset signal. The built-in CPU circuit 23 is reset with a power supply together with other circuit elements and internal circuits including VDP.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The effect control unit 22 and the image control unit 23 execute the effect operation in a dependent manner based on the control command from the main control unit 21, so that the output from the power supply board 20 is avoided in order to avoid complication of the circuit configuration. The system reset signal SYS is used.

  The reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and each CPU is provided unless a regular clear pulse is received from the CPU of each control unit 21, 24. Is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22, the image control board 23, and the liquid crystal interface board 28 are integrated by connector connection, and the effect control unit 22 is connected to the power supply board 20 via the power relay board 33. The DC voltage (5V, 12V, 32V) of each level and the system reset signal SYS are received (see FIGS. 3 and 4A).

  The effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive signal SDATA to the driver ICs mounted on the lamp drive board 36, the lamp drive board 29, and the motor lamp drive board 30 in synchronization with the clock signal CK. A lamp group composed of a large number of LED lamps and electric lamps is driven to realize a lamp effect based on the control command CMD.

  In the case of this embodiment, the lamp effect is executed by the three lamp groups CH0 to CH2, and the lamp driving board 36 receives the CH0 lamp driving signal SDATA0 via the frame relay boards 34 and 35 as a clock. It is received in synchronization with the signal CK0 (clock synchronous serial communication). Note that a series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, so that the lighting state is updated all at once.

  The same applies to the lamp drive board 29. The driver IC of the lamp drive board 29 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. The lighting state of the lamp group CH1 is updated all at the same time.

  On the other hand, the driver IC mounted on the motor lamp driving board 30 receives the lamp driving signal transmitted in a clock synchronous manner to drive the lamp group CH2, and receives the motor driving signal transmitted in a clock synchronous manner, The effect motor groups M1 to Mn composed of a plurality of stepping motors are driven. The lamp driving signal and the motor driving signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives the signals transmits the timing at which the operation control signal ENABLE2 changes to the active level. Thus, the driving states of the lamp group CH2 and the motor groups M1 to Mn are updated.

  In addition, the effect control unit 22 sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). Is output. The image control unit 23 drives the display devices DS1 and DS2 based on the control command CMD 'to execute various image effects. As shown in FIGS. 3 and 4A, the image control unit 23 includes a built-in CPU circuit (image production control device) 51 having an internal configuration equivalent to that of a general-purpose one-chip microcomputer, a VDP (Video Display Processor) 52, It is comprised centering on the composite chip | tip 50 which incorporated. In addition, a control memory (PROM) 53 that stores a control program for the built-in CPU, a DRAM (Dynamic Random Access Memory) 54 that can access a large amount of data at a high speed, and a CGROM 55 that stores a large amount of CG data necessary for image control. And are installed.

  The CGROM 55 is composed of a SATA module that transmits and receives ATA commands using a protocol compliant with Serial Advanced Technology Attachment (hereinafter sometimes referred to as SATA). This point will be further described later.

  Then, the image data generated by the VDP 52 based on the CG data read from the CGROM 55 is passed through the liquid crystal interface board 28 as first and second LVDS (low voltage differential signaling) signals. The data is transmitted to the main display device DS1 and the sub display device DS2. The display device DS1 has a built-in LVDS receiver that converts LVDS signals into RGB signals. The display device DS1 includes five pairs of LVDS signals from the liquid crystal interface substrate 28 and a direct current including an LED backlight power source. It is driven by receiving power supply voltage. On the other hand, the sub display device DS1 is driven by receiving the digital RGB signal converted by the liquid crystal interface substrate 28 and the DC power supply voltage including the LED backlight power supply. Note that the display screens of the main display device DS1 and the sub display device DS2 are updated by the VDP 52 every 1/60 seconds.

  Next, the configuration of the effect control unit 22 will be described in more detail based on FIG. As shown in FIG. 4A, the effect control unit 22 includes a one-chip microcomputer 40 (effect control CPU 40) that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and effect control CPU 40. A control memory (flash memory) 41 for storing the control program and various effect data EN, and a sound processor 42 for reproducing and outputting a sound signal based on the instructions of the effect control CPU 40 set in the built-in registers RG0 to RGn The audio memory 43 stores compressed audio data that is the original data of the audio signal to be reproduced, and the digital amplifier 46 receives the audio signal output from the audio processor 42.

  In the case of the present embodiment, the effect data EN stored in the control memory 41 includes scenario data for managing the effect progress of the lamp effect and the sound effect, lamp drive data for determining the blinking mode of the LED, and motor rotation. Motor drive data for determining the mode. The lamp driving data and the motor driving data are sequentially output bit by bit to become a lamp driving serial signal and a motor driving serial signal.

  The one-chip microcomputer 40 includes a plurality of serial input / output ports SIO and a plurality of parallel input / output ports PIO. The serial input / output port SIO includes a serial output port Soi that outputs a lamp driving signal of CHi or a motor driving signal SDATAi in synchronization with the clock signal CKi, and origin sensor signals (serial signals) of the motor groups M1 to Mn. And a serial port Si that receives the signal in synchronization with the clock signal CK3. Note that i = 0 to 2, and corresponds to the three groups of lamp groups CH0 to CH2 and the motor groups M1 to Mn driven together with the lamp groups of CH2.

  On the other hand, the parallel input / output port PIO is divided into output ports Po and Po 'and an input port Pi. A control command CMD and a strobe signal STB from the main control unit 21 are input to the input port Pi. On the other hand, operation control signals ENABLE0 to ENABLE2 are output from the output port Po ', and a control command CMD' and a strobe signal STB 'are output from the output port Po. Specifically, after the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are stepped down to a logic level corresponding to the power supply voltage 3.3 V of the one-chip microcomputer 40 in the buffer 44. , And supplied to the input port Pi twice in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the effect control CPU 40, and the effect control unit 22 is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 includes (1) an abnormality notification and other notification control commands, and (2) a control command for specifying an outline of various effect operations resulting from winning at the symbol start opening. (Variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the effect control unit 22 acquires the variation pattern command, the effect lottery is subsequently performed, and the effect outline specified by the acquired variation pattern command is further specified. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking the LED group and a sound effect preparation operation by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker. The control command CMD ′ relating to the performed image effect is output.

  In order to realize an image effect synchronized with such an effect operation, the effect control unit 22 sends a 16-bit control command CMD ′ along with a strobe signal (interrupt signal) STB ′ to the image control unit 23 through the output port Po. Output. In addition, when receiving the symbol designation command, the abnormality notification control command, and other control commands, the effect control unit 22 collects the 8-bit unit control commands in a 16-bit length, It is output to the image control unit 23 together with STB ′.

  As described above, the audio processor 42 according to the present embodiment accesses the audio memory 43 based on an instruction (set value by the audio command SND) received from the effect control CPU 40 to the built-in registers (audio control registers) RG0 to RGn. The necessary audio signal is played back and output. As shown in the figure, the audio processor 42 and the audio memory 43 are connected to each other by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, data of 1 Gbit (= 226 * 16) can be stored in the audio memory 43. In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) having a 13-bit length, and is a sequence of background music. (BGM), a group of effect sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 213), each corresponding to a phrase number. The phrase number is specified by the set value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

  The voice command SND is a plurality (2 or 3) bytes long, and is used for a write purpose of transmitting a predetermined set value to any one of the many voice control registers RG0 to RGn built in the voice processor 42. The However, the voice command SND of the present embodiment is used not only for a write application for writing a set value such as a phrase number, but also for a read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined audio control register RGi to be accessed is specified by a 1-byte register address.

  The setting (Write) of the set value to the sound control register RGi is not necessarily executed individually for each sound control register, and a group of sound control is performed by designating the SAC data stored in the sound memory 43. A series of setting operations for the registers RGi to RGj can be completed. Here, the SAC data is an aggregate of a maximum of 512 pieces (up to 1024 bytes) in which the register address (1 byte) of the voice control register RGi is associated with the set value (multiple bytes) in the voice control register RGi. Means. In the present embodiment, only a necessary set of such SAC data is stored in the audio memory 43 in advance, and a set of SAC data is specified by a SAC number of about 13 bits that is a single ID information. It is like that.

  Therefore, in the case of the present embodiment, the voice command SND for write use specifies a SAC number and specifies a set of SAC data, or specifies a set value and a register address individually.

  As shown in FIG. 4 (b), the connection control main part describes the effect control CPU 40 and the audio processor 42 with parallel signal lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and operation management data. Chip that selects 2-bit operation control data lines (address bus) A0 to A1 that can be transmitted, 2-bit control signal lines WR and RD that can control read / write operations, and a voice processor 42 It is connected to a select signal line CS.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the effect control CPU 40, and the operation management data lines A0 to A1 are realized by the address bus of the effect control CPU 40, and are connected to the effect control CPU 40, respectively. Yes. Then, when the production control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS are appropriately changed, and the audio specified by the parallel signal lines CD0 to CD7. A read / write (R / W) operation with the control register RGi is realized.

  Specifically, as shown in the time chart of FIG. 4B ', the register address of the audio control register RGi and the write data to the audio control register RGi are transmitted in parallel through the parallel signal lines CD0 to CD7, respectively. Is done. Whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

  Accordingly, as shown in FIG. 4B, the operation management data (address data A0 to A1) is changed from [00] to [01], while 1-byte data on the data bus is changed to [voice control register RGi. A predetermined voice command SND is transmitted by transiting from “register address” → [write data to voice control register RGi]. When the write data is a plurality of bytes long as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] are changed from [00] → [01] → [01]. → Send the data of multiple bytes while repeating [01].

  The voice command transmitted in this way is subsequently validated as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, the error flag of the voice control register RGn is set. This error flag (status information STS) is produced by changing the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive it by the Read operation.

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness that the sound effect suddenly stops.

  In the configuration of FIG. 4B, the effect control CPU 40 receives the status information STS including error information in parallel from the audio processor 42, but the configuration is not limited to this configuration. That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the effect control CPU 40 when the sound processor 42 recognizes a communication error. In this case, the sound in which the communication error has occurred in the interrupt processing program of the effect control CPU 40. You can resend the command. If such a configuration is adopted, an error flag (status information STS) acquisition process that is a useless process in most cases, that is, a process of transitioning the operation management data A0 to A1 to [10] may be omitted. it can.

  As shown in FIGS. 3 and 4A, in this embodiment, the left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, it is necessary for the audio processor 42 to generate a 3-channel audio signal. If this is transmitted in parallel, the wiring between the audio processor 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the sound processor 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. Are suppressed to a total of 4-bit signal lines including the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SD1 and SD2.

  Here, SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SD2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The audio processor 42 transmits the audio signal L of the left channel while maintaining the channel control signal LRCLK at the L level, and outputs the audio signal R of the right channel while maintaining the channel control signal LRCLK at the H level. Transmit (see FIG. 4C). Since there is one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  4A, a buffer circuit 47 that transfers serial data SDATAi output from the serial output port Soi of the serial input / output port SIO of the one-chip microcomputer 40 and the clock signal CKi to the effect control board 22. -49 are provided (i = 0-2).

  Here, the output buffer 47 transfers the lamp drive signal SDATA0 and the clock signal CK0 output from the serial output port So0 to the shift register circuit (driver IC) of the lamp drive substrate 36. The output buffer 48 transfers the lamp drive signal SDATA1 and the clock signal CK1 output from the serial output port So1 to the driver IC of the lamp drive substrate 29. As described above, the driver ICs mounted on the lamp driving substrates 29 and 36 drive and drive the lamp groups CH0 and CH1.

  On the other hand, the buffer circuit 49 functions as an input / output buffer, and transfers the serial signal SDATA2 output from the serial output port So2 to the motor lamp driving substrate 30 together with the clock signal CK2. Further, an origin sensor signal (serial signal) indicating the origin position of the group of effect motors M1 to Mn is transferred to the serial input port Si of the one-chip microcomputer 40 in synchronization with the clock signal CK3.

  In this embodiment, the serial signal SDATA2 transferred by the buffer circuit 49 includes a lamp drive signal (serial signal) for lighting the lamp group CH2 and a motor drive signal (serial signal) for rotating the effect motors M1 to Mn. ) Are continuous. The motor lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  Next, as shown on the left side of FIG. 4A, in this embodiment, the data bus and the address bus of the effect control CPU 40 extend to the liquid crystal interface board 28. For convenience of explanation, this relationship is illustrated on the left side of FIG. 4A, but the clock circuit RTC is connected to the CPU by the lower 4 bits of the address bus of the effect control CPU 40 and the lower 4 bits of the data bus. It is configured to be arbitrarily accessible. In addition, the memory element SRAM for storing game performance information enables the effect control CPU 40 to randomly access the 16 bits of the address bus of the effect control CPU 40 and the lower 16 bits of the data bus.

  The clock circuit RTC is a clock IC (real-time clock) that measures the current date and time, and operates permanently with the secondary battery BT charged with the power supply voltage received from the effect control board 22 together with the memory element SRAM. doing. That is, while the gaming machine is powered on, the secondary battery BT (FIG. 5) is charged, and after the gaming machine is powered off, based on the charged secondary battery BT, The timekeeping operation of the clock circuit RTC is continued, and the effect data is also permanently stored (backup operation).

  As shown in FIG. 5, the clock circuit RTC of the embodiment is connected to the effect control CPU 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for Read / Write operation. Then, the effect control CPU 40 adds important game information and abnormality information related to the game operation to the memory element SRAM by adding the year / month / day information, day information and time information acquired from the clock circuit RTC. .

  This clock circuit RTC has two types of chip select terminals, CS1 and CS0 bars, and permits access from the effect control CPU 40 on condition that the input voltage to each terminal is at a normal level. It has become. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detecting unit ER, and when the CS1 terminal receives the abnormal level output Vo, the abnormality detection flag Fos of the clock circuit RTC is automatically set. To be set.

  In the case of the present embodiment, this abnormality detection flag Fos is determined by the effect control CPU 40 together with other abnormality detection flags TEMP when the power is turned on. If the abnormality detection flag Fos is set, the date and time at that time and The time is reported. Therefore, if an abnormality in the clock function is recognized, it can be dealt with quickly.

  Even if the voltage of the secondary battery BT drops when the power is shut down, the voltage level of the secondary battery BT is quickly recovered by power recovery and the CS1 terminal returns to the normal level, so access from the effect control CPU 40 is permitted. Will be. Therefore, if the configuration of the present embodiment in which the determination process for the abnormality detection flag Fos is not employed, the abnormality of the clock circuit RTC may not be detected permanently.

  Further, the clock circuit RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, every Friday at 21:50. In the effect control CPU 40 that receives the interrupt signal IRQ, The game information and abnormality information accumulated in the memory element SRAM so far are appropriately tabulated.

  The game information to be aggregated is a summary of history information related to the big hit state. For example, (1) the number of winnings to the symbol start opening required to become the big hit state, (2) the symbol of the big hit state, Total value and statistical value of jackpot state whether or not it is probable, (3) type of notice effect or reach effect that reached the big hit state, (4) number of consecutive chants, (5) number of balls thrown out by consecutive chans Increasing trends are included. And these total information and statistical information are alert | reported suitably according to a player's request | requirement. The player's instruction is specified by, for example, pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS.

  On the other hand, the abnormal information to be tabulated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detection times and the detection time of the detection sensor for detecting illegal activities, This includes the number of detections, detection frequency, detection time, etc. of an act of forcibly opening the winning opening 16 with a wire or the like. The total information is displayed on the main display device DS1 in response to a special operation by an attendant.

  As shown in FIG. 5A, the clock circuit RTC according to the embodiment is configured by incorporating three internal register tables Bank0 to Bank2. However, since the bank 2 register table relates to time setting and date setting, only the bank 0 and bank 1 register tables are shown in FIGS. 5 (b) and 5 (c). In any case, each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the Bank0 register table (FIG. 5B). It is configured to be.

  As shown in FIG. 5B, in the bank 0 register table, bit 3 of the first register is an abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. This is a temperature abnormality flag TEMP shown. In this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined, thereby preventing the abnormal timekeeping operation from continuing. In addition, the clock circuit RTC is disposed close to the effect control CPU 40, and the temperature abnormality of the effect control CPU 40 is quickly detected by repeatedly determining the value of the temperature abnormality flag TEMP at appropriate time intervals.

  In the register table of Bank0, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. In this embodiment, the current date and time are acquired from the register table of Bank 0 on the condition that the Busy flag is in a non-Busy state (update completion). For this reason, in this embodiment, there is no possibility of acquiring halfway during the updating operation or irrational clock information, and the validity of the clock information stored in the memory element SRAM is ensured. For example, if clock information that is being updated from 1:59:59 to 2: 00: 00: 00 is acquired, there is a possibility that the clock information of 1: 0: 0 is acquired.

  Further, the register table of Bank 1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, an interrupt generation is instructed by setting 1 to bit 0 of the register No. 1 of Bank 1 (Interrupt Enable), and the day of the week of Friday is designated in the registers 0 to 8 of Bank 1. Time information of 30:30 hours is set.

  Next, the image control unit 23 will be described in detail with reference to FIG. FIG. 6A is a circuit block diagram illustrating the composite chip 50 constituting the image control unit 23 including related circuit elements. As illustrated, the composite chip 50 of the embodiment includes a built-in CPU circuit 51 and a VDP circuit 52. The built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays mutual transmission / reception data. The CPUIF circuit 56 is connected to a control memory (PROGRAM_ROM) 53 for storing a control program and necessary control data in a nonvolatile manner and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes. The built-in CPU circuit 51 can be accessed.

  As shown in the figure, in this embodiment, the built-in CPU circuit 51 is configured to receive a VBLANK interrupt signal from the VDP circuit 52. Here, the VBLANK (vertical blanking) interrupt signal indicates that the screen update processing (output processing of image data for each frame) of the display devices DS1 and DS2 executed at 1/60 second intervals is completed. . That is, in the case of the present embodiment, the built-in CPU circuit 51 can grasp that the screen update of each display device is completed by the VBLANK interrupt signal.

  As will be described later, in this embodiment, since the two display circuits A and B operate substantially simultaneously, the VDP circuit 52 is configured to receive a VBLANK interrupt signal indicating the start of VBLANK of the display circuit A. Various sequence operations are started based on the VBLANK interrupt signal. As described above, in this embodiment, since each unit operates starting from the start of VBLANK of the display circuit A, there is a time zone in which the sub display device DS2 is turned off for production and the display circuit B does not function. But no problem arises.

  The built-in CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer. The built-in CPU circuit 51 controls the image control CPU 63 that controls the overall image rendering based on the control program in the control memory 53, and the CPU when the program goes into a runaway state. A watchdog timer (WDT) 58 forcibly resetting, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area of the CPU, and a DMAC (Direct Memory Access Controller) for realizing data transfer without going through the CPU 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and output ports Po. Has been.

  For convenience, the expression “input / output port” is used. In the image control unit 23, the input / output port includes an input port and an output port that operate independently. This also applies to the input / output circuit 64p and the input / output circuit 64s described below.

  The parallel input / output port 62 is connected to an external device (production control board 22) through the input / output circuit 64p. The control command CMD ′ and the interrupt signal STB ′ to be received are received. On the other hand, in this embodiment, the serial input / output port 61 and the DMAC 60 are not used.

  Next, the VDP circuit 52 will be described. The VDP circuit 52 has a CGROM (SATA module) 55 for storing compressed data, which is a constituent element of still images and moving images constituting an image effect, and a storage capacity of about 4 Gbits. An external DRAM (Dynamic Random Access Memory) 54, a main display device DS1, and a sub display device DS2 are connected.

  Although not particularly limited, in this embodiment, the CGROM (SATA module) 55 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbit, and serial transmission. Is used to obtain the necessary compressed data. Therefore, the problem of skew (difference in transmission speed for each bit data) inevitably generated in parallel transmission is solved, and an extremely high-speed transmission operation becomes possible. As described with reference to FIG. 3, in this embodiment, the CGROM 55 is accessed at a high speed by the HSS (High Speed Serial) system compliant with SerialATA.

  Note that, regardless of whether or not the HSS method conforming to SerialATA is adopted, the NAND flash memory is mechanically more stable than a hard disk and can be accessed at high speed, but is a sequential access memory. As compared with DRAM and SRAM (Static Random Access Memory), there is a problem in random accessibility. Therefore, in this embodiment, by executing a preload operation for reading a group of compressed data (CG data) to the DRAM 54 prior to the drawing operation, smooth random access of the CG data during the drawing operation is realized. ing. Incidentally, the access speed decreases in the order of built-in VRAM> external DRAM> CGROM.

  Specifically, the VDP circuit 52 is a register group 70 in which various operation parameters (setting values) that define the operation of the VDP are set, and 48M used when generating image data to be displayed on the display devices DS1 and DS2. A VRAM (video RAM) 71 of about bytes, a data transfer circuit 72 that controls data transmission / reception between each part inside the chip and data transmission / reception outside the chip, a preloader 73 that executes the above-described preloading operation, and image data of the VRAM 71 3 (A / B / C) display circuit 74 for executing appropriate image processing in parallel, graphics decoder 75 for decoding compressed data read from CGROM 55, and still image data after decoding And image data for each frame of the display devices DS1 and DS2 is generated by appropriately combining video data and video data As a part of the operation of the drawing circuit 76, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion, an SMC unit 78 that can transmit and receive serial data, and three systems (A / B / C) An output selection unit 79 that appropriately selects and outputs the output of the display circuit 74, an LVDS unit 80 that converts image data output from the output selection unit 79 into an LVDS signal, and a CPUIF unit that relays data transmission and reception with the CPUIF circuit 56 81, a CG bus IF unit 82 for relaying data reception from the CGROM 55, a DRAMIF unit 83 for relaying data transmission / reception with the external DRAM 54, and a VRAMIF unit 84 for relaying data transmission / reception with the VRAM 71. It is configured.

  FIG. 6B illustrates the relationship among the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84, and the register group 70, CGROM 55, DRAM 54, and VRAM 71. As described above, the CGROM 55 of the embodiment is a SATA module configured by a flash SSD, and incorporates a SATA device control unit SAd that implements a Serial ATA-compliant HSS (High Speed Serial) protocol. Correspondingly, the CG bus IF unit 82 includes a SATA host control unit SAh.

  Then, the SATA host control unit SAh issues an FIS (Frame Instruction Structure) type 27H ATA command Tx (for example, READ Multiple) to the SATA device control unit SAd that specifies address information and data amount for a group of CG data. In response to this, the SATA device control unit SAd returns the necessary group of CG data to the SATA host control unit SAh as the FIS type 46H data ATA command Rx. In the present embodiment, the received CG data is transferred to the external DRAM 54 via the DRAM IF unit 83 as preload data. Note that the preload operation is not essential, and when the preload operation is not executed, the CG data is transferred to the VRAM 71 via the VRAMIF unit 84. Further, the data transfer destination of the preload operation is not limited to the external DRAM 54, and may be, for example, the VRAM 71.

  Returning to FIG. 6A, the description will be continued. The data transfer circuit 72 uses a resource (storage medium) in the VDP circuit and an external storage medium as a transfer source port or a transfer destination port, and performs a data transfer operation between them. Is a circuit for executing In addition to the VRAM 71, the transfer source port includes a storage medium (resource) connected to the CPU bus, CG bus, and external DRAM bus. Similarly, the transfer destination port includes a storage medium connected to the CPU bus, CG bus, and external DRAM bus in addition to the VRAM 71. The data transfer circuit 72 is also in charge of the operation of transmitting the display list DL for specifying the display image for one frame to the preloader 73 and the drawing circuit 76 by a group of drawing commands.

  The display list DL includes a group of drawing commands described in the drawing order. The drawing command includes a command that defines what image is to be drawn at which position in one frame, and the storage position (source address) of the image to be drawn, such as CGROM, is also specified. In this embodiment, since two display devices DS1 and DS2 are used, it is necessary to generate image data for one frame in the frame buffers FBa and FBb for the display devices DS1 and DS2 secured in the VRAM 71, respectively. Yes (see FIG. 9B), the drawing positions of the frame buffers FBa and FBb are specified by a predetermined drawing command.

  The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers the CG data on the CGROM 55 referred to in the display list DL to a preload area of the DRAM 54 designated in advance. At this time, the preloader 73 outputs the display list DL in which the reference destination of the CG data is rewritten to the address after transfer. Note that the rewritten display list DL is transmitted to the drawing circuit 76 by the data transfer circuit 72.

  In the present embodiment, a sufficient storage area capable of setting a preload area in the external DRAM 54 based on a set value in a preloader register (see FIG. 6B), which will be described later, and supporting a number of preload processes. Is secured. In this embodiment, unless the storage area set as the preload area is used up, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data.

  Therefore, in the preload process, the CGROM 55 is accessed only when necessary compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, no problem occurs even if CG data for a plurality of frames is preloaded at once.

  The drawing circuit 76 sequentially analyzes the drawing commands of the display list DL transmitted by the data transfer circuit 72 and cooperates with the graphics decoder 75, the geometry engine 77, and the like in the frame buffer formed in the VRAM 71. This is a circuit for drawing an image for one frame of each of the display devices DS1 and DS2. The graphics decoder 75 is divided into a still picture decoder and a moving picture decoder, and decodes (decompresses) still pictures and moving pictures encoded (compressed) by a predetermined compression algorithm using a corresponding decompression algorithm. That is, in the case of the embodiment, the still image is compressed by a predetermined algorithm for each image data constituting one still image, and the moving image includes a plurality of still image data for realizing a series of moving images between frames. Compressed based on data difference value.

  As described above, in this embodiment, since the preloader 73 is functioning, the reference destination of the CG data of the display list DL is not the CGROM 55 but the preload area set in the DRAM 54 or the VRAM 71. Therefore, random access to CG data generated during the execution of drawing by the drawing circuit 76 can be executed quickly, and high-resolution moving images with intense movement can be drawn without any problem. That is, according to the present embodiment, it is possible to execute complex and advanced image effects while using an inexpensive SATA module as the CGROM 55.

  The frame buffer FB formed in the VRAM 71 is a double buffer divided into a drawing area (drawing bank) and a display area (display bank), and uses the two areas by alternately switching the usage. In the present embodiment, since the two display devices DS1 and DS2 are connected, the two-division frame buffers FBa / FBb are secured. Accordingly, the drawing circuit 76 draws one frame of image data in the drawing bank of the frame buffer FBa for the display device DS1, and also draws one frame of image data in the drawing bank of the frame buffer FBa for the display device DS2. Will be drawn. When image data is written in the drawing bank, the display circuit 74 reads out the image data in the display bank and outputs it to the display devices DS1 and DS2.

  By the way, in this embodiment, the display circuit 74 reads out and outputs the image data of the display bank every 1/60 seconds, while the switching cycle between the display bank and the drawing bank is 1/30 seconds. The display screen is actually switched every 1/30 seconds. Since the present embodiment dares to adopt such a configuration, a processing time of up to 1/30 second can be secured for the preloading operation by the preloader 73 and the drawing operation of the drawing circuit 76, and a complicated and advanced image effect can be achieved. It becomes possible. And it has been confirmed that there is no problem in the effect even if the screen update period of the display device is set to 1/30 seconds. Note that switching between the drawing bank and the display bank is instructed to the display circuit 74 by the image control CPU 63 writing a predetermined set value in a predetermined display register (FIG. 6B).

  The display circuit 74 is a circuit that reads out the image data from the frame buffers FBa and FBb, performs final image processing, and outputs the image data (see FIG. 9E). The final image processing includes, for example, scaling processing for enlarging / reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. After these image processes, a digital RGB signal (24 bits in total) is output together with a horizontal synchronization signal and a vertical synchronization signal. As shown in FIG. 9 (e), in this embodiment, there are provided three systems of display circuits A / B / C that execute the above-mentioned operations in parallel. The image data in the frame buffer FBa / FBb / FBc corresponding to is read, and the final image processing described above is executed. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured, and the display circuit C does not function.

  In relation to this operation, the output selection unit 79 of this embodiment transmits the output signal of the display circuit A to the LVDS unit 80a, and transmits the output signal of the display circuit B to the LVDS unit 80b (see FIG. 9 (e)). Then, the LVDS unit 80a converts the image data (24-bit digital RGB signal in total) into an LVDS signal, adds a pair for transmitting a clock signal, and outputs it to the main display device DS1 as all five pairs of differential signals. doing. The main display device DS1 incorporates a conversion receiver RV for the LVDS signal, restores the RGB signal from the LVDS signal, and displays an image corresponding to the output of the display circuit A.

On the other hand, the LVDS unit 80b adds a pair for transmitting a clock signal to each of the 6 bits (18 bits in total) excluding the lower 2 bits of each 8-bit digital RGB signal, and converts and receives the signals as all four pairs of differential signals. The image display by the RGB signal of a total of 18 bits which is output to the unit RV and received by the sub display device DS2 from the conversion receiving unit RV (THCV214) is realized. This is because the sub display device DS2 does not require a resolution of 2 ⁸ * 2 ⁸ * 2 ^{8 and a} resolution of 2 ⁶ * 2 ⁶ * 2 ⁶ is sufficient. However, there is no particular limitation, and a resolution of 2 ⁸ * 2 ⁸ * 2 ⁸ may be realized by transmitting all five pairs of differential signals.

  In addition, it is not always necessary to use the LVDS signal. For example, when the transmission distance is short, the digital RGB signal is directly transmitted to the display device via the digital RGB unit 80c, or when the transmission distance is long. In the conversion transmission unit TR ′, the digital RGB signal is converted into a V-By-one (registered trademark) signal, transmitted to the conversion reception unit RV ′, and then converted back to the digital RGB signal in the conversion reception unit RV ′. Is also suitable. Note that the broken line in FIG. 9E shows this operation mode, but any output signal of the display circuit A / B / C can be obtained by appropriately setting the operation of the output selection unit 79. The above operation is possible.

  Next, the SMC unit 78 (Serial Management Controller) is a composite controller that incorporates an LED controller and a Motor controller. Then, an LED / motor driver (driver IC with a built-in shift register) mounted on an external board outputs an LED drive signal and a motor drive signal in synchronization with the clock signal, while at the appropriate timing, a latch pulse is output. It is configured to allow output.

  Regarding the internal circuit of the VDP circuit 52 and its operation, the operation content to be executed by the internal circuit is defined by the operation parameter (setting value) set in the register group 70 by the image control CPU 63, and the execution state of the VDP circuit 52. Can be specified by reading the operation status value of the register group 70. The register group 70 means a large number of registers mapped in a memory space (0 to FFFFFH) of about 1 Mbytes on the memory map of the image control CPU 63. The image control CPU 63 passes operation parameters of the operation parameter via the CPUIF unit 81. The WRITE (setting) operation and the READ operation of the operation status value are executed (see FIG. 6B).

  In the register group 70, a “system control register” in which initial setting values related to system operations such as an interrupt operation are written, and settings related to data transfer processing by the data transfer circuit 72 between the image control CPU 63 and the internal circuit of the VDP circuit 52 are set. A “data transfer register” in which a value and the like are written, a “GDEC register” that can specify an execution status including an error occurrence of the graphics decoder 75, and a “drawing command” and a setting value related to the drawing circuit 76 are written A “register”, a “preloader register” in which setting values relating to the operation of the preloader 73 are written, a “display register” in which setting values relating to the operations of the three divided display circuits A / B / C are written, and LEDs “LED control register” in which setting values related to the controller (SMC unit 78) are written, and Moto Controller settings related (SMC unit 78) includes and a "motor control register" to be written is, these control registers is composed each of a plurality of bytes long.

  More specifically, in the “preloader register”, (1) the preload area is set in the DRAM 54 or the VRAM 84, (2) the start address of the preload area, (3) the preload data area, The number of frames used is set. (4) The data size per frame is set. Further, the data transfer source and data transfer destination are set in the “data transfer register”, and the “display register” stores the frame buffer FBa / FBb / FBc to be output for each display circuit A / B / C. The start position, the buffer size of the frame buffers FBa / FBb / FBc, and the like are set.

  In addition, the “drawing register”, “preloader register”, and “data transfer register” are instructed to start execution of the drawing operation, the preload operation, and the data transfer operation. As described above, in the double buffer structure frame buffer FBa / FBb / FBc, switching between the drawing bank and the display bank is realized by writing a predetermined set value in a predetermined “display register”. It is.

  In any case, the internal operation of the VDP circuit 52 is realized by the image control CPU 63 writing an appropriate set value in any of the register groups 70. Therefore, the image control CPU 63 realizes an image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set value in the register constituting the register group 70 described above.

  In this embodiment, the lamp effect and the motor effect are handled by the effect control CPU 40 of the effect control board 22, so that the setting value is written in the LED control register and the motor control register without using the SMC unit 78. It will never happen.

  Next, the SATA module 55 (CGROM) and the CG bus IF unit will be further described based on FIG. 7 and FIG. FIG. 7A shows the SATA host control unit (HSS controller) SAh built in the CG bus IF unit and the SATA device control unit SAd built in the SATA module 55 together with storage media related to them. It is.

  As shown in the figure, the SATA host control unit SAh is a RAM serving as a work area including a SATA host CPU, a ROM, a DMAC (DMA controller), and a Shadow TFR (Task File Register) for realizing the operation of the application layer (command layer). And a SATAIF unit for realizing the operations of the transport layer and the link layer, and a SATAPHY unit for realizing the physical layer (PHY Layer).

  Here, the SATA host control unit SAh is configured to be accessible to the DRAM 54, the VRAM 71, and the register group 70. Then, the SATA host controller SAh that has received the data ATA command (FIS type 46H) in the Shadow TFR transfers the CG data extracted from the data ATA command Rx to the external DRAM 54 through the data transfer circuit 72 and stores it. It is configured as follows. Further, when the DMAC of the SATA host control unit SAh is made to function, the CG data is transferred to the DRAM 54 without going through the Shadow TFR. However, as described above, the storage destination of the CG data may be the VRAM 71. When no preload operation is involved, the CG data extracted from the data ATA command Rx is stored in the VRAM 71.

  Corresponding to such a configuration, the SATA module 55 includes a NAND flash memory and a flash controller that controls read / write operations with respect to the storage main body Flash... Flash and the storage main body Flash. And a SATA device control unit SAd that communicates with the SATA host control unit SAh by the HSS method according to SerialATA. In FIG. 7A, the SATA device controller SAd and the Flash controller are collectively regarded as an SSD controller.

  The storage main body Flash... Flash is sequentially accessed based on read control by the Flash controller and read in page units (for example, 512 + 16 byte units). The read CG data is generated in the FATA type 46H data ATA command Rx in the SATA device control unit SAd and returned to the SATA host control unit SAh.

  In order to realize such an operation, the SATA device control unit SAd basically has the same configuration as the SATA host control unit SAh, and the SATA device CPU and ROM that realize the operation of the application layer (command layer), and the SSD. It has a RAM that is a work area including a TFR (Task File Register), a SATAIF unit that realizes operations of the transport layer and the link layer, and a SATAPHY unit that realizes a physical layer (PHY Layer). Yes.

  The ATA commands used in the HSS controller (SATA host controller) of the embodiment include (1) RegHD (register-Host to Device) of FIS type 27H issued from Shadow TFR to SSD TFR, and (2) SSD. FIS type 34H RegDH (register-Device to Host), which is a status response transmitted from TFR to Shadow TFR, (3) FIS type 46H DATA used bidirectionally during data transfer, and (4) Device access For example, every 8 kbytes of data transfer, FIO type 5FH PIOSetup, (5) DMA active response (DMASetup), (6) FIS type A1H Set Device Bit used for SSD TFR to Shadow TFR, (7) DMA Active of FIS type 39H and (8) BIST Active are included.

  Here, in RegHD (register-Host to Device), in accordance with SerialATA, IDENTIFY DEVICE (ECH), READ DMA (C8H), READ MULTIPLE (C4H), READ SECTOR (S) (20H), READ VERIFY SECTOR ( S) (40H), READ DMA EXT (25H), READ MULTIPLE EXT (29H), READ SECTOR (S) EXT (24H), and READ VERIFY SECTOR EXT (42H). The hexadecimal number in parentheses means the command code of each ATA command.

  7 shows the FIS structure (FIG. 7B) of the IDENTIFY DEVICE of the command code ECH issued by the SATA host control unit SAh to acquire the device information of the SATA module 55, and acquisition of a group of CG data. The FIS structure of READ MULTIPLE EXT (FIG. 7C) of command code 29H issued for this purpose is shown. All of them are 32 × 5 bits in length, but the IDENTIFY DEVICE command is issued with the device field set to the slave mode, and the READ MULTIPLE EXT command is address information LBA (logical) of data to be read from the CGROM 55. Block addressing) and the number of data pages (Sector Count) are specified and issued.

  FIG. 7 also shows that the SATA device control unit SAd can be used bidirectionally with the FIS structure of the status response command (FIG. 7D) that identifies its own operating state and returns it to the SATA host control unit SAh. The FIS structure of the DATA command (FIG. 7 (e)) is shown. For example, the SATA device controller SAd that has received the ATA command READ SECTOR (S) (20H) returns a DATA command preceded by the PIOSetup command to the SATA host controller SAh.

  The DATA command can contain up to 2048 Dword (= 2048 * 4 = 8 kbytes) of CGROM data. For example, the DATA command receives an ATA command such as READ DMA (C8H) or READ MULTIPLE EXT (29H). The SATA device control unit SAd repeatedly returns the necessary number of DATA commands to the SATA host control unit SAh without preceding the PIOSetup command.

  FIG. 8A illustrates an operation procedure of the SATA host control unit SAh and the SATA device control unit SAd. Here, a case where there is no DMA transfer is shown, but when the DMAC of the SATA host control unit SAh is functioned, the CG data extracted in the transport layer of the SATA host control unit SAh passes through the Shadow TFR. Without being transferred to the DRAM 54 or the like.

  In any case, the SATA host CPU of the SATA host controller SAh first writes necessary parameters of the ATA command to be issued (for example, Device column, LBA column, Sector Count column, etc.) to the Shadow TFR as the operation of the application layer. Then write the ATA command code.

  Then, the transport layer of the SATAIF unit of the SATA host control unit SAh and its lower layer execute a series of operations by a sequence operation. That is, the transport layer generates an FIS body from the Shadow TFR data and outputs it to the lower layer. Next, in the link upper layer, a 4-byte CRC (Cyclic Redundancy Check) is added to the rear part of the FIS main body received from the transport layer, and all data is scrambled. A byte-length SOF primitive (start information) and a 4-byte length EOF primitive (end information) are added to complete the frame data structure.

  Next, the link lower layer executes 8B / 10B conversion processing for converting 8-bit data into 10-bit D character or K character, and the physical layer (PHY Layer) generates LVDS signal Tx by serialization processing. Then, the LVDS signal Tx is serially transmitted by a predetermined method using a pair of differential signal lines.

  On the other hand, in the physical layer (PHY Layer) of the SATA device control unit SAd that has received the LVDS signal Tx, 10-bit parallel data of D character or K character is restored in order by deserialization processing, and in the link lower layer, 8B / The original 8-bit data is restored from the 10-bit data by the 10B reverse conversion process. The upper layer of the link removes the SOF primitive, the EOF primitive, and the CRC, extracts the FIS main body, and transmits it to the transport layer. In the transport layer, the FIS body is transferred to the SDD TFR.

  The subsequent processing is performed by the SATA device CPU, which is the application layer of the SATA device control unit SAd, and analyzes the received FIS main body and executes necessary processing corresponding to the received ATA command. For example, when a memory read ATA command such as READ SECTOR (S) (20H) is received, preparation for the memory read operation is started, and the ATA command (RegDH) of the preparation response (PIOSetup, etc.) is controlled by the SATA device control. After returning from the unit SAd to the SATA host control unit SAh, a DATA command (FIG. 7E) is returned.

  On the other hand, when a ATA command for memory read such as READ DMA (C8H) or READ MULTIPLE EXT (29H) is received, the SATA device control unit SAd immediately sends a DATA command (FIG. 8D) to 2048 Dword. For each CG data (= 8 kbytes), it is returned as many times as necessary. Finally, a status response command (FIG. 8E) is returned. FIG. 8 (c) illustrates this group of operations. FIGS. 8 (b), 8 (d), and 8 (e) are respectively illustrated in FIGS. 7 (b) and 7 (b). ) And FIG. 7B are reprinted.

  Subsequently, with reference to the flowcharts of FIGS. 9 (a) to 9 (d) and the time chart of FIG. 10 (a) regarding the control operation of the image effect performed using the two display devices DS1 and DS2. I will explain. The image effect is realized by an image control CPU 63 that receives a control command CMD 'from the effect control CPU 40, and a VDP circuit 52 that functions as instructed by the image control CPU 63. As described above, an instruction from the image control CPU 63 to the VDP circuit 52 is specified by an operation parameter written in the register group 70.

  As shown in FIG. 9, the image effect operation is performed based on the display list update process (FIG. 9A) executed every predetermined time by the image control CPU 63 and the display list received from the image control CPU 63. This is realized by each sequence operation of the drawing circuit 76 and the display circuit 74 (FIG. 9B to FIG. 9D). It should be noted that the image control CPU 63 performs necessary setting values (operation parameters) at the time of resetting the power supply or at a necessary timing thereafter so that the preloader 73, the drawing circuit 76, and the display circuit 74 realize the sequence operation described below. ) Is set in the register group 70.

  If it demonstrates based on the above, the image control CPU63 of an Example will start the operation | movement of Fig.9 (a) every 1/30 second which receives VBLANK interruption | blocking (refer Fig.6 (a)) twice (ST1), The sequence operation of the preloader 73 and the drawing circuit 76 is started based on setting appropriate operation parameters in the preloader register and the drawing register (operation start process ST2). Further, the display bank and the drawing bank in the frame buffer FB are switched based on setting appropriate operation parameters in the display register (bank switching process ST2).

  FIG. 10A schematically shows these operations. The display circuit 74 reads the image data of the display bank every 1/60 seconds and outputs it to the display devices DS1 and DS2. The display screen of the display device is updated. Each time the image data output operation for one frame is completed, a VBLANK interrupt signal is output.

  On the other hand, the image control CPU 63, the preloader 73, and the drawing circuit 76 execute their own operations in parallel every 1/30 seconds (δ) in response to receiving the VBLANK interrupt twice. Yes. FIG. 10B schematically shows the contents of each memory of the built-in RAM 59 of the CPU circuit, the built-in VRAM 71 of the VDP circuit, the external DRAM 54, and the CGROM 55.

  Continuing the description of the operation of the image control CPU 63, following the processing of step ST2, the image control CPU 63 updates the display list DL based on the effect scenario (ST3). Here, the effect scenario embodies an image effect specified by the control command CMD ′ received from the effect control CPU 40. In other words, the production scenario includes (1) a series of videos for a series of videos that are continued for a certain period of time, and still images (including background images and preview images) where the drawing position, orientation, and scaling ratio are appropriately defined. The start time and end time of the video effect, and (2) which still image is to be drawn, at what time, in what position, and so on are defined.

  Even if it is a video effect, the drawn image on the display device only changes quickly and smoothly, and still images are drawn in that the same or different next image data is drawn on the display device at regular intervals. Is the same. In this embodiment, since different images are displayed on the two display devices DS1 and DS2, the effect scenario is divided into two according to this configuration.

  Then, the image control CPU 63 refers to the effect scenario having such a configuration, and at each timing (T1, T1 + δ, T1 + 2δ,...), Outputs a group of drawing commands for specifying the display images of the display devices DS1, DS2. The listed display list DL is generated. The display list DL specifies, for moving images, which part of the moving image that progresses in time by specifying the storage location of the CGROM, and where the still image such as a sprite image is stored in the CGROM. It defines how and where the displayed image is drawn on which position of the display device.

  Next, the display list DL configured in this way is transferred to the prescribed area of the external DRAM 54 and waits until the next list update timing is reached (ST4). FIGS. 10A and 10B show that the display list DL1 is generated as a result of the operation of the image control CPU 63 started from the timing T1, and is transferred to the external DRAM 54 at the timing T1 ′. Has been.

  In this embodiment, the display list DL1 is rewritten by the preloader 73 at a timing T1 + δ delayed by one timing, and further drawn by the drawing circuit 76 based on the rewritten display list DL1 at a timing T1 + 2δ delayed by one timing. Processed. A display screen specified by the display list DL1 appears on the display devices DS1 and DS2 based on the display operation of the display circuit 74 executed after the timing T1 + 3δ further delayed by one timing.

  As described above, in this embodiment, the operation start of the preloader 73, the drawing circuit 76, and the display circuit 74 is configured to be delayed by about one timing (δ). Therefore, the preloader 73 started from the timing T1 processes the oldest display list that has not been processed by the external DRAM 54, and specifically processes the display list generated at the previous timing. become. In other words, the display list DL1 generated by the image control CPU 63 at the timing T1 is processed as follows based on the operation of the preloader 73 starting from the timing T1 + δ.

  Hereinafter, the timing after timing T1 + δ will be described. The preloader 73 analyzes the display list DL1, which is the unprocessed and oldest display list, stored in the specified area of the external DRAM 54. When a drawing command that requires CGROM CG data is detected in the display list DL1, necessary information is acquired in the CG bus IF unit to acquire the group of CG data in the CG data area of the external DRAM 54. 82 SATA host controller SAh. In addition, the storage location of the CG data in the drawing command related to the prefetching (preload) processing is rewritten from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (SS10).

  In parallel with the operation of the preloader 73, the SATA host control unit SAh that has obtained the necessary information, for example, the memory read ATA command such as READ MULTIPLE EXT (29H), the address information LBA (logical block addressing), The data amount (Sector Count) is specified and issued.

  Then, a DATA command is returned from the SATA device control unit SAd of the CGROM 55 in the procedure of FIG. 8C, and necessary data (CG data) extracted from the DATA command is sequentially transferred to the external DRAM 54. The compressed state is stored (SS11).

  The above operation is repeatedly executed every time a drawing command requiring CGROM CG data is detected, and all the CG data (compressed data) for constructing one frame of the display device DS1 and the display device DS2 is The data is secured from the CGROM 55 to the CG data area of the DRAM 54. Since the CG data secured once in the CG data area of the DRAM 54 is managed so as to be usable thereafter, the preload process (SS11) is skipped when the CG data secured at the previous timing is used. Then (see the broken line in FIG. 9B), only the process (SS10) of rewriting the storage location of the CG data from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 is executed.

  Then, for the display list DL1 that specifies each frame of the display device DS1 and the display device DS2, for all the drawing commands described therein, transfer processing of necessary CG data to the DRAM 54 and rewriting processing of the display list are performed. If completed, the system waits for the next preload operation that starts intermittently (SS12). In FIG. 10B, a state in which necessary CG data is transferred from the CGROM 55 to the external DRAM 54 at the timing T1 + δ is indicated by an arrow. Note that the transferred CG data remains in a compressed state.

  Next, a drawing operation executed in cooperation by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, and the like will be described with reference to FIG. As shown in FIG. 10A, this drawing operation is repeated every fixed time (δ). For convenience, in the following description, the drawing operation after timing T1 + 2δ, which is executed based on the display list DL1 after rewriting. Will be explained.

  The drawing circuit 76 sequentially analyzes drawing commands described in the display list DL1, which is an unprocessed and oldest display list, among the display lists stored in the external DRAM 54 (SS20). The graphics decoder 75 and the geometry engine 77 are caused to function with respect to the still image or moving image specified by the. Since the drawing circuit 76 processes the display list DL1 after rewriting, the external DRAM 54 is the reference destination of CG data related to still images and moving images.

  Then, the still image data and the moving image data decoded by the graphics decoder 75 are expanded and developed in the still image decoding area and the moving image decoding area secured in the built-in VRAM 71 (SS22 to SS23). Next, drawing processing is executed by writing the decoded still image data and moving image data in a drawing mode defined by the drawing command to a predetermined position in the frame buffer FB of the VRAM 71 (SS24). Note that the drawing mode includes the drawing position in the frame buffer FB. However, in the case of a sprite image or the like, the drawing posture or the enlargement / reduction ratio may be further defined, and the geometry engine 77 functions.

  As shown in FIG. 9E, in this embodiment, the first frame buffer FBa and the second frame buffer FBb are secured in the frame buffer FB in correspondence with the two display devices DS1 and DS2. A drawing operation is realized by writing still image or moving image decode data at a predetermined position of the frame buffer FBa / FBb specified by the command (SS24). As described above, each of the frame buffers FBa / FBb has a double buffer structure divided into a drawing bank and a display bank. In the drawing operation (SS24), more precisely, the drawing buffer of the frame buffer FBa / FBb. Decode data is written at a predetermined position in FIG. Although different from the embodiment, if the third frame buffer FBc is secured in the frame buffer FB, the image of the third display device can be drawn in parallel.

  In any case, after the processing in step SS22 or SS23, a necessary image is drawn at a predetermined position of a predetermined frame buffer FBa / FBb based on the decoded data (moving image / still image) (SS24). This process is executed from the beginning to the end of the display list DL1 in the order in which the drawing commands are written, so that the previously drawn image is subsequently overwritten by the image drawn in the same area. .

  When the drawing process for all the drawing commands is completed, the process waits until the next drawing operation that is started intermittently (SS25). In FIG. 10B, an arrow indicates that a necessary image is drawn in the frame buffer FB (FBa + FBb) at the timing T1 + 2δ.

  Finally, the operation of the display circuit 74 will be described with reference to FIG. This display operation is also repeated at regular time intervals (δ), but for the sake of convenience, the following description will be made on display operations after timing T1 + 3δ shown in FIG. As described above, at this timing, image data based on the display list DL1 is secured in the drawing bank of the frame buffer FBa / FBb. Then, based on the bank switching process (ST2) shown in FIG. 9A, in the display operation after the timing T1 + 3δ, the drawing bank in which the image data by the display list DL1 is described functions as the display bank.

  As shown in FIG. 9E, the VDP circuit 52 is provided with three display circuits A / B / C that are executed in parallel. In this embodiment, two display circuits A / B are provided. Only is set to work. Then, the display circuit A / B reads out the image data stored in the display bank of the corresponding frame buffer FBa / FBb and outputs it to the output selection unit 79 (SS30).

  Thereafter, based on the operation of the output selection unit 79, the image data of the frame buffer FBa output from the display circuit A is transmitted to the main display device DS1 via the LVDS unit 80a as described above. . As described above, the image data of the frame buffer FBb output from the display circuit B is transmitted to the sub display device DS2 via the LVDS unit 80b. When the display circuit A finishes the output processing of the image data for one frame, a VBLANK interrupt signal is output. In this embodiment, since the two display devices A / B operate in parallel, the display circuit B also finishes the output process at this timing. In FIG. 10B, an arrow indicates that the image data of the display bank of the frame buffer FB (FBa + FBb) is output slightly after the timing T1 + 3δ.

  As described above, in this embodiment, since the preloader 73, the drawing circuit 76, and the display circuit 74 perform a series of operations in parallel with each other in parallel, the image processing is performed at high speed with high image quality. It is possible to realize a changing large-screen image production without any trouble. In particular, in the present invention, since two display devices are used, the control burden of image production is large, so the parallel operation of this embodiment is highly valuable.

  In addition, in the present invention, the preloader 73 is operated prior to the drawing circuit 76 to pre-read (preload) the CG data into the RAM. Therefore, it is necessary to use a random access memory (such as a mask ROM) as the CGROM 55. In addition, a sequential access memory can be used, and the manufacturing cost can be reduced. Since the CGROM 55 is accessed at high speed for preloading CG data by the HSS method according to serial ATA, there is no problem even if the image data constituting one frame is enormous in a large high-quality display device. In addition, since the CG data is serially transmitted, wiring with the CGROM can be simplified.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. For example, in the above embodiment, as shown in FIG. 6A, the composite chip 50 including the built-in CPU circuit 51 and the VDP circuit 52 is used. However, such a composite chip 50 is used. It is also preferable to use a one-chip microcomputer having a configuration different from that of the VDP circuit 52 instead of the built-in CPU circuit 51.

  In the embodiment shown in FIG. 6A, a SATA module incorporating a NAND flash memory is used as the CGROM 55. However, the present invention is not particularly limited. For example, another sequential access memory such as an XtraROM may be used. . However, use of a NOR flash memory that can be accessed randomly or a normal mask ROM is not prohibited.

  In the embodiment shown in FIG. 6B, the NAND flash memory and the VDP circuit 52 (CG bus IF unit 82) are connected by a serial transmission path using a differential signal line. However, the present invention is not limited to serial transmission. A parallel transmission system including a normal mask ROM and accessed through a data bus and an address bus may be employed.

  In the above embodiment, as shown in FIG. 3, the image effect is controlled by the image control CPU 63 that receives the control command CMD ′ from the effect control CPU 40 that controls the sound effect and the lamp (motor) effect. It is also preferable that the image control CPU 63 directly controls the sound effect, the lamp effect, the motor effect, and the image effect by receiving the control command CMD of the main control unit 21 directly without using the CPU 40. It is.

  FIG. 11 shows a configuration in which the image control CPU 63 built in the composite chip 50 controls all the rendering operations. In the case of such a configuration, the transmission / reception process of the control command CMD ′ is not necessary, so that the circuit configuration of the effect interface board 22 and the image control board 23 is simplified and the transmission / reception of the control command CMD ′ is performed. In addition to reducing the control burden, there is an advantage that the transmission error of the control command CMD ′ and the problem of synchronization deviation between the image effect and other effects are solved. In FIG. 11, the composite chip 50 is used. Instead of using the VDP circuit 52 and the image control CPU 63 built in the composite chip 50, a higher performance one-chip microcomputer and a dedicated VDP circuit are used. It is also preferred to use

  FIG. 12 illustrates in detail the main part of FIG. 11 and shows a case where the image control CPU 63 built in the composite chip 50 controls the sound effect, the lamp effect, the motor effect, and the image effect. . FIG. 13 shows the composite chip 50 of FIG. 12 together with other circuit components.

  As shown in FIG. 13, in this embodiment, the control command CMD from the main control unit 21 is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. Further, the strobe signal STB is supplied to the interrupt terminal of the image control CPU 63 via the input / output circuit 64p, thereby starting the reception interrupt process. Therefore, the image control CPU 63 that has grasped the control command CMD based on the reception interrupt process integrally controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD through the effect lottery. Will do.

  By the way, in the Example of FIGS. 11-13, the SMC part (Serial Management Controller) 78 of the VDP circuit 52 is used for a lamp effect and a motor effect. As described above, the SMC unit 78 incorporates an LED controller and a Motor controller, and is configured to output a serial signal in a clock synchronous manner. The Motor controller is configured to be able to output a latch pulse at an arbitrary timing based on a set value in a predetermined register 70, and to be able to input a serial signal in a clock synchronous manner.

  Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. . The origin sensor signals SN0 to SNn from the production motor groups M1 to Mn are serially input in a clock synchronous manner.

  As shown in FIG. 12, the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 are driven through the output buffers 47, 48, and 49, and the lamp drive substrates 36 and 29 and the lamp motor are driven. It is transmitted to the substrate 30. Further, the sensor signals SN0 to SNn are serially input from the motor lamp driving substrate 30 to the SMC unit 78 via the input buffer 49.

  In addition, in the structure of FIGS. 11-13, it is not essential to use the SMC part 78. FIG. That is, since the built-in CPU circuit 51 includes a general-purpose serial input / output port SIO, the lamp effect and the motor effect can be executed using these. In FIG. 13, clock signals CK0 to CK2 and drive signals SDATA0 to SDATA2 are output via an input / output circuit 64s internally connected to the serial input / output port SIO, and operation control is performed via the input / output circuit 64p. A configuration in which signals ENABLE0 to ENABLE2 are output is indicated by a broken line. In addition, although expressed as an input / output port or an input / output circuit for the sake of convenience, an output port or an output circuit actually functions.

  Incidentally, as shown in FIG. 13A, a thick data bus line is shown. In this embodiment, a normal mask ROM is used as the CGROM 55, and the CG data of the CGROM 55 is converted into parallel data as a DRAM 54 (or VRAM 84). (See FIG. 13B). Of course, also in this embodiment, a SATA module may be used for the CGROM 55.

  Note that the preload operation can be changed as appropriate, including whether or not it is used. FIG. 14 shows an embodiment in which the preload operation is omitted. The display list update process by the image control CPU (FIG. 14A), the drawing operation by the drawing circuit 76 (FIG. 14B), and the display circuit are shown. 74 shows an operation mode in which the display operation by 74 (FIG. 14C) is repeated at regular intervals. In this configuration, necessary CG data is read from the CGROM 55 during the decoding process (SS22, SS23).

In the case of such an embodiment, for example, the display list updated at timing T1 is activated at the subsequent timing, and a display screen corresponding to the display list is displayed on the display devices DS1 and DS2. . When using a randomly accessible memory such as a normal mask ROM, the preloading operation by the preloader 73 is not particularly necessary, and it is preferable to adopt the configuration as shown in FIG.

  On the contrary, when using the sequential access memory, the preloader 73 is preferably used, but it is not always necessary to preload every CG data for one frame. FIG. 15 shows a display list update process by the image control CPU (FIG. 15A) and a multiple preload process by the preloader 73 (FIG. 15B) when preloading a plurality of frames on the display screen. Is shown. Note that the drawing operation by the drawing circuit 76 and the like and the display operation by the display circuit 74 are omitted, but as in the case of FIGS. 9 and 10, every predetermined time δ (for example, 1/30 second). It is executed repeatedly.

  Hereinafter, the list update process will be described. The image control CPU activates the drawing operation by the drawing circuit 76 and the display operation by the display circuit 74 every predetermined time (ST11). Wait without updating the list DL (ST12). When the update timing is reached, a plurality of n display lists DL1 to DLn are collectively generated (ST13), and these are transferred to, for example, the external DRAM 54 and the preloader 73 is activated (ST14).

  Then, in response to this processing, the preloader 73 starts operation, and among the plurality of display lists stored in the external DRAM 54, analysis processing is started in order from the unprocessed and oldest display list, The display list is rewritten with respect to the address value of CGROM (SS10). When necessary, the CGROM CG data is pre-read (preloaded) (SS11).

  In this embodiment, the above processing (SS10 to SS11) is not limited to a single display list DL, and all the n display lists DL1 to DLn are in order as long as other operations are not hindered. (SS12 ′, SS12). The case where the other operation is hindered is, for example, a case where the preload area (see FIG. 10B) secured in the external DRAM 54 is filled with unused CG data. In such a case, in order to avoid overwriting of CG data, it waits for a space to be generated in the preload area (SS12 ′). In the list update process, it is also preferable to eliminate the process of step SS12 'by setting the number of display lists DL1 to DLn to be generated to an appropriate value.

  In any case, the above operation is repeated until the processing for all the display lists DL1 to DLn is completed (SS12). According to this embodiment, the problem that the READ access of a large amount of CG data is concentrated at a certain timing which can occur in the embodiment of FIG. 9 is solved, and the access load to the CGROM can be smoothed. Note that the list update process in FIG. 9 and the multiple list process in FIG. 15 may be mixed, and the process may be shifted to the multiple list process in FIG. 15 only when READ access is concentrated.

  As described above, in each of the above-described embodiments, the bullet ball game machine has been described. However, it is needless to say that the present invention can also be suitably used in other game machines with image effects such as a swing game machine.

GM gaming machine 23 Sub-control means DS1, DS2 Display device 51 Image effect control means (built-in CPU circuit)
55 Data storage means 52 Image generation means ST1 to ST4 List generation means SS10 to SS12 Preload means SS20 to SS25 Drawing means

Claims (1)

A gaming machine that executes an image effect corresponding to a lottery result of a predetermined lottery process,
Image production control means for centrally controlling image production;
Data storage means for storing compressed data which is a constituent element of a still image and / or a moving image constituting an image effect;
Image generating means for realizing image effects by outputting image data generated based on the compressed data instructed by the image effect control means to a display device,
While the image production control means is provided with a list generation means for generating a drawing list for specifying a display screen of the display device for each predetermined operation cycle ,
In the image generating means,
With reference to the drawing list generated by the image effect control means, preload means for acquiring necessary compressed data from the data storage means and storing it in the buffer area, and changing the drawing position to specify the storage position;
Operates intermittently at each operation cycle, refers to the changed drawing list, obtains necessary data from the buffer area, and sends image data corresponding to the drawing list to one of a pair of frame buffers Drawing means to be generated on one side ;
An output unit that operates intermittently for each operation cycle and outputs image data generated by the drawing unit in any of the pair of frame buffers in the preceding operation cycle to a display device;
Said preloading means, the compressed data necessary for rendering means, if not present in the buffer area, the compressed data of the display screen one frame or plural frames, reading from said data storage means, temporarily stored in the buffer area A gaming machine characterized by being configured to perform.

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