JP6532437B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine which performs lottery processing caused by gaming operations and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine capable of smoothly executing high-quality moving image.

  A ball game machine such as a pachinko machine is provided with a symbol starting port provided on a game board, a symbol display unit for displaying a series of symbol variation modes by a plurality of display symbols, and a special winning opening with an open / close plate. Is configured. Then, when the detection switch provided in the symbol starting port detects the passage of the game ball, it becomes a winning state, and after the game ball is paid out as a prize ball, the display symbol is fluctuated for a predetermined time in the symbol display portion. Thereafter, when the symbol is stopped in a predetermined manner such as 7/7/7, the jackpot is in a big hit state, the big winning opening is repeatedly opened, and a game state advantageous to the player is generated.

  Whether or not such a game state is to be generated is determined by a big hit lottery that is executed on the condition that the gaming ball has won the symbol starting opening, and the above-mentioned symbol fluctuation operation is based on this lottery result It has become a thing. For example, when the lottery result is in the winning state, the rendering operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, even in the case of the lost state, the same reach action may be executed, and in this case, the player pays attention to the transition of the rendering operation while strongly reassuring being in the big hit state. When the predetermined symbol is aligned with the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

JP 2005-130950 A

  In this type of gaming machine, conventionally, the display screen in the image effect is configured by pasting a plurality of sprite images in a suitable place on a still image of one frame serving as a base. Then, a display screen with motion is formed by changing the pasting position, pasting posture, enlargement / reduction ratio, and the like of the sprite image with the passage of time (Patent Document 1).

  However, in such a configuration, it is virtually impossible to realize irregular and violent movements. That is, for example, when it is intended to change the image irregularly every cycle (1/60 second) of the vertical synchronization signal of the display device or every cycle thereof, the pasting position or pasting position of the sprite image, or Changes such as scaling factors can not be dealt with at all.

  Therefore, in general, by preparing moving image data corresponding to the rendering time from the start time to the end time in the CGROM, the motion that changes violently and complicatedly is expressed. In this case, in the case where the total number of frames is M (for example, ΔT * 60) corresponding to the presentation time ΔT of the moving image effect, the M pieces of image data respectively constitute one frame of the display device. In addition, in order to prevent the total amount of image data from being voluntarily increased, it is stored in the CGROM as compressed data after appropriate compression processing. Then, at the time of use, for example, the decoder is made to function every 1/60 seconds to restore the original moving image data (one frame).

  However, the display image of the display device has been enlarged and the image quality has been improved. However, although the data is in a compressed state, the stored data in the CGROM has become enormous, which is a burden on access processing and decoding processing of CG data. The In addition, a device configuration capable of smoothly executing high-quality and powerful image effects is desired.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of smoothly realizing powerful image effects without consuming the memory space silently.

  In order to achieve the above-mentioned object, the inventor examined various compression algorithms in order to suppress the storage data amount of moving image data etc. in consideration of the limit of the storage capacity of a storage device (CGROM). And, in general, it is thought that the compression ratio is reversely influenced by the large influence of the difference between the temporally adjacent data, and the difference between the original image data such as moving image data and the basic image with a small difference value The present invention has been completed, in which the data is decomposed into high-value effect images and compressed.

  That is, in the present invention, one unit of image data for realizing a series of moving image effects is divided into basic image data and one type or multiple types of effect image data constituting an effect image overlapping the basic image. Ru.

More specifically, according to the present invention, in a gaming machine capable of performing an image effect by displaying a still image and / or a moving image on a display device, an image of one frame, which is a unit of a predetermined moving image effect, is The image to be executed is constructed by overlapping one frame of the basic image in which the outline of the image changes fixedly or smoothly and one frame of one or more types of effect images in which the outline of the image changes irregularly The basic image maintaining the specified number of vertical and horizontal pixels corresponding to the effect, and the effect image having the number of vertical pixels and / or horizontal pixels smaller than the predetermined number of pixels are each stored in the storage device in a compressed state, At the image display timing, the basic image and the effect image read from the storage device are each decompressed from the compressed state, and the effect image further includes the number of vertical pixels and / or horizontal pixels. The enlargement process is performed on the number of cells to restore to the specified number of vertical and horizontal pixels, and the effect image in the restored state and the basic image in the restored state are configured to be displayed in an overlapping manner. The compression rate (1 / B) of the basic image is stored in the storage device in a compressed state (B> C) higher than the compression rate (1 / C) of the effect image before the enlargement processing. In addition, it is typical that a basic image includes a presentation main character.

  FIG. 17 is a diagram for explaining the principle of the present invention, in which X pieces of original image data D0 for achieving an image effect of X frames changing with time are N (N pieces of) basic image data d1. The state is shown divided into M (M frames) effect image data d2. Each data is also in the non-compressed state at the top of the drawing, and for convenience, the state of N = M = X is illustrated.

  Here, since the outline of the image smoothly changes in the basic image data d1, the difference between adjacent data is small and can be compressed at a large compression rate (1 / B). On the other hand, since the effect image data d2 changes violently and the difference is large, the compression ratio (1 / C) is not high, and this point is the same for the compression ratio (1 / A) of the original image data D0. (B >> A, C).

  Therefore, in the present invention, the number N of frames of the basic image data d1 is reduced from the number X of frames of the original image, or the vertical dimension (number of pixels in the vertical direction) and / or the horizontal dimension (horizontal direction) of the effect image data d2 The number of pixels of is reduced to be smaller than the specified pixel product D. Here, the prescribed pixel product D is the product of the optimally designed prescribed number of horizontal pixels W and the prescribed number of longitudinal pixels H (D = H × W), and the image data amount of one image is calculated. Proportional.

  In the former case where the number N of basic images is reduced, the data amount of the basic image data d1 before compression is suppressed by N <X, and this is compressed at a large compression ratio (1 / B). Significant data suppression effect is exhibited. Even in the case of 1 / C ≒ 1 / A, if the number M of frames of the effect image is appropriately decreased (M <X), ND / B + MD / C <XD when the total amount of data after compression is compared The relationship of / A is established.

  On the other hand, in the latter case where the vertical dimension (vertical pixel number) and / or the horizontal dimension (horizontal pixel number) of the effect image is reduced from the prescribed vertical and horizontal dimensions, the frame number M of the effect image is not reduced M = X), effect image data d2 can be suppressed by the reduction of vertical and horizontal dimensions (1 / K) (= d2 / K), and by further compressing this, XD / B + XD / C / The relationship of K <XD / A is established.

  In this case, since the vertical and horizontal dimensions of the effect image are reduced from the specified dimensions, the image quality is degraded if the vertical and horizontal dimensions are restored to the original vertical dimensions, but the image quality is changed drastically since the effect image is originally changed drastically. Deterioration of is not a problem in practice.

As a typical embodiment of the present invention, each of the X frames is a single or small number of basic images ( N << M ) and N effect images ( M = X) which are constantly changing and different from one another. It consists of In the case of such a configuration, the contour of the image represented by the basic image is always in a fixed state or for a fixed time.

  FIG. 18 shows a state in which 64 image data are divided into a single basic image (a monster with an open mouth) and 64 effect images (EF_0001 to EF_0064). As illustrated, the effect image changes discontinuously at a level whose contour can not be expressed by a mathematical expression. Here, a change that can not be expressed by a mathematical expression means a change that can not be traced by coordinate conversion using orthogonal coordinates or polar coordinates (circular coordinates, cylindrical coordinates, spherical coordinates), etc. -It means that movement can not cope. Therefore, an image configured by combining sprite images is not included in the effect image of the present invention. A typical effect image includes an image expressing sparks, lightning, explosions, flames, bursts and the like, and the illustrated example represents a lightning pattern.

  In any case, when one basic image shown in FIG. 18 and 64 effect images are combined, 64 images in which lightning patterns appear around a monster with an open mouth are completed, and the 64 images are continuous. If it displays, a staging effect can be heightened more by a lightning pattern changing complicatedly. In addition, it is confirmed that there is no problem in the rendering effect even if the 64 effect image data are irreversibly reduced to 1/2 in length and height and stored in the memory and the image data with low image quality is enlarged at the time of reproduction There is.

  As another embodiment, X pieces of image data are configured by appropriately combining M pieces of effect image data (M ≦ X) different from each other and N pieces of effect image data (N ≦ M) different from each other It can also be done. In this case, the outline of the image represented by the basic image data changes smoothly in accordance with the progress of the image effect. On the other hand, the M effect images change discontinuously at a level that their contours can not be expressed by mathematical expressions.

  In a preferred embodiment, the basic image is stored in storage in a compressed state, maintaining a defined number of vertical and horizontal pixels corresponding to the image rendition to be performed, while the effect image comprises the number of vertical pixels and / or the vertical image. After reducing the number of horizontal pixels from the specified number of pixels, it is stored in the storage device in a compressed state, and at the image display timing, the basic image data and the effect image data read from the storage device correspond to the compression algorithm. After being decompressed by the decompression algorithm, the effect image is further subjected to an enlargement process on the number of vertical pixels and / or the number of horizontal pixels to restore the number of vertical and horizontal pixels. Also, the basic image and the effect image are simply stored in the storage device in a compressed state using the same compression algorithm.

  In any case, according to the compression algorithm, the total amount of data of basic image data in a compressed state and the total amount of data of effect image data in a compressed state are image data for realizing the predetermined moving image effect. The image data that achieves the same moving-image effect, and is less than the total amount of compressed image data of a group after the basic image and the effect image in the uncompressed state are overlapped while maintaining the specified number of vertical and horizontal pixels Design is preferred.

  Further, it is preferable that the predetermined moving image effect is realized by N basic image data and M effect image data, and the number of them is set to N ≦ M, and all of the predetermined moving image effects are It is also preferable that the common single basic image data and the different effect image data are overlapped with each other.

  After the effect image data is read out from the storage device and subjected to enlargement processing corresponding to a prescribed number of vertical and horizontal pixels, it is displayed on the screen without further image processing such as enlargement / reduction / rotation. It is preferable that an image effect for temporally shifting a completed still image by appropriately changing one or a plurality of sprite images stored in the storage device in advance is provided separately from the predetermined moving image effect. It is preferred that

  According to the above-described gaming machine of the present invention, powerful image effects can be smoothly realized while suppressing consumption of memory space.

It is a perspective view of a pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the whole structure of the pachinko machine of 1st Example. It is a block diagram which illustrates the circuit composition of a production control part and an image control part. It is drawing explaining the structure of timepiece IC. It is a block diagram which shows the internal structure of the compound chip which takes charge of the image production of 1st Example. It is a figure explaining the structure and operation procedure of CGROM. It is a figure explaining the operation | movement procedure which improved the access speed of CGROM. They are a flowchart explaining the internal operation of a compound chip, and a drawing explaining operation of a display circuit. It is drawing explaining operation content of each part of a compound chip. It is a block diagram which shows the whole structure of the pachinko machine of 2nd Example. It is a block diagram which shows a part of FIG. 11 in detail. It is drawing explaining the example of utilization of a compound chip. It is drawing explaining an operation example without pre-loading processing. It is drawing explaining the operation example of a multiple pre-load process. It is a figure explaining another Example about the structure of CGROM. It is drawing explaining the principle of the present invention. It is drawing explaining the relationship between an effect image, a basic image, and an original image.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. The pachinko machine GM has a rectangular frame-shaped wooden outer frame 1 detachably mounted on the island structure, and a front frame 3 pivotally mounted so as to be openable and closable through a hinge 2 fixed to the outer frame 1. It is configured. In the front frame 3, the game board 5 is detachably mounted not from the back side but from the front side, and on the front side, the glass door 6 and the front plate 7 are pivotally connected so as to be openable and closable.

  On the outer periphery of the glass door 6, the electric decoration lamp by LED lamp etc. is arrange | positioned in substantially C shape. On the other hand, a total of three speakers are disposed at the upper left and right positions and the lower side of the glass door 6. The two speakers disposed at the top output the sound of the left and right channels R and L, respectively, and the lower speakers output a deep bass.

  An upper plate 8 for storing game balls for firing is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowed or removed from the upper plate 8 at a lower portion of the front frame 3, and a firing handle And 10 are provided. The firing handle 10 is interlocked with the firing motor, and the game ball is fired by a striking rod operating according to the rotation angle of the firing handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the launch handle 10. Although the chance button 11 does not function normally, the built-in lamp is turned on to be operable when the game state is the button chance state. The button chance state is a game state provided as necessary.

  The right side of the upper plate 8 is provided with an operation panel 12 for ball lending operation to a card-type ball lending machine, and a number display section for displaying the remaining amount of card with a 3-digit number and balls for gaming balls for a predetermined amount A ball lending switch instructing lending and a return switch instructing return of the card at the end of the game are provided.

  As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 consisting of an outer rail and an inner rail made of metal is annularly provided, and a central opening HO is provided substantially at the center thereof. And under the central opening HO, the movable effect body (not shown) is stored in the concealed state, and at the time of the movable advance notice effect, the movable effect body rises and becomes the exposed state, so that it has a predetermined reliability. We have achieved a preview effect. Here, the notice effect is an effect that indefinitely notifies that the jackpot state advantageous to the player is brought in, and the reliability of the notice effect means the probability that the jackpot state is brought.

  In the central opening HO, the main display device DS1 formed of a large liquid crystal color display (LCD) is disposed, and on the right of the main display device DS1, a movable sub-display device formed of a small liquid crystal color display DS2 is arranged. The main display device DS1 is a device that variably displays a specific symbol related to a big hit state and also displays a background image, various characters, and the like in an animation. The display device DS1 has a special symbol display portion Da to Dc at the central portion and a normal symbol display portion 19 at the upper right portion. Then, in the special symbol display portions Da to Dc, a reach effect may be performed which expects a jackpot state to be invited, and in the special symbol display portions Da to Dc and the periphery thereof, appropriate notice effects and the like are performed.

  At a normal time, the sub display device DS2 displays the image information in a stationary state in which the display screen is inclined at an angle that is easy for the player to view. However, at the time of the predetermined advance notice effect, while moving to the left side in the figure while changing the inclination angle to an angle easy for the player to view, a predetermined advance notice image is displayed.

  That is, the sub-display device DS2 of the embodiment functions not only as a simple display device but also as a movable effecter that executes advance notice effects. Here, the notice effect by the sub-display device DS2 is set to a high degree of reliability, and the player pays attention to the movement operation of the sub-display device DS2 with a high degree of expectation.

  By the way, in the game area where the game balls fall and move, the first symbol start port 15a, the second symbol start port 15b, the first large winning opening 16a, the second large winning opening 16b, the normal winning opening 17, and the gate 18 Is provided. Each of these winning openings 15 to 18 has a detection switch inside, so that the passage of the game ball can be detected.

  At the upper part of the first symbol start opening 15a, after the gaming ball entering from the introduction opening IN moves in a seesaw-like or roulette-like manner, the effect stage 14 configured to be winning possible is arranged in the first symbol start opening 15 There is. Then, when the game ball is won in the first symbol start opening 15, the variation operation of the special symbol display portions Da to Dc is started.

  The second symbol start port 15b is configured to be opened and closed by a motorized tulip provided with a pair of left and right opening / closing claws, and when the stop symbol after variation of the normal symbol display portion 19 hits and the symbol is displayed, predetermined The opening and closing claws are opened only for a time or until a predetermined number of gaming balls are detected.

  It should be noted that the normal symbol display unit 19 is for displaying a normal symbol, and when the gaming ball having passed the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and is extracted at the passage of the gate 18 of the gaming ball The stop symbol determined by the selected random number for lottery is displayed and stopped.

  The first large winning opening 16a is configured to have a slide board advancing and retracting in the front and rear direction, and the second large winning opening 16b is configured to have an opening and closing plate whose lower end is pivotally supported and opened forward. . The operations of the first large winning opening 16a and the second large winning opening 16b are not particularly limited, but in this embodiment, the first large winning opening 16a corresponds to the first symbol starting opening 15a, and the second large winning opening 16 b is configured to correspond to the first symbol start port 15 b.

  That is, when the game ball is won in the first symbol start opening 15a, the variation operation of the special symbol display portions Da to Dc is started, and thereafter, when the predetermined big hit symbols are aligned to the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of the game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuation operation started by the winning of the game ball to the second symbol start opening 15b, the second big hit special game is started. The opening and closing plate of 2 large winning a prize mouth 16b is opened, the winning a prize of game sphere is facilitated. The game value of the special game (big hit state) is variously different corresponding to the big hit symbol etc. which are aligned, but which game value is to be awarded is previously based on the lottery result according to the winning timing of the game ball It is determined.

  In a typical big hit state, after the opening / closing plate of the big winning opening 16 is opened, the opening / closing plate closes when a predetermined time passes or a predetermined number (for example, 10) of game balls win. Such an operation is continued up to, for example, 15 times, and controlled in a state advantageous to the player. In addition, when the stop symbol after the change of special symbol display part Da-Dc is a specific symbol among special symbols, the privilege that the game after the end of the special game will be in the high probability state (probable change state) is Granted.

  FIG. 3 is a block diagram showing the entire circuit configuration of the pachinko machine GM for realizing each of the above-described operations, and FIG. 4 illustrates a part of the circuit in detail. As shown in FIG. 3, the pachinko machine GM receives power of AC 24 V and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, and a system reset signal (power reset signal) SYS etc. The main control board 21 which takes charge of overall control, the effect control board 22 which executes lamp effects and voice effects based on the control command CMD received from the main control board 21, and the control command CMD received from the effect control board 22 Image control board 23 for driving the two display devices DS1 and DS2 based on the above and a payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 to pay out the game balls. And a launch control board 25 for launching game balls in response to the operation of the player.

  As illustrated, the control command CMD output from the main control board 21 is transmitted to the effect control board 22. The control command CMD ′ ′ output from the main control board 21 is transmitted to the payout control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′ and CMD ′ ′ are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are divided into two 8-bit lengths and sent in parallel. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits long in parallel and transmitted in parallel. Even in the case where the control command of (1) is continuously transmitted and received, the process can be completed promptly, and other control operations are not disturbed.

  As illustrated, in the present embodiment, a liquid crystal interface substrate 28 accessible from the image control substrate 23 and the effect control substrate 22 is provided. The liquid crystal interface substrate 28 is mounted with a clock circuit (real time clock) RTC capable of measuring the current time, and a memory element (Static Random Access Memory) SRAM storing game performance information.

  Further, in the present embodiment, the image control board 23 drives the main display device DS1 and the sub display device DS2 via the liquid crystal interface board 28 on which the LVDS reception circuit and the like are mounted. Here, the male connector and the female connector are directly connected to the liquid crystal interface substrate 28 and the image control substrate 23 without passing through the wiring cable. Similarly, with regard to the effect control board 23 and the liquid crystal interface board 28, the male connector and the female connector are directly connected without passing through the wiring cable. Therefore, the storage space of the whole substrate can be minimized even if the circuit configuration of each electronic circuit is complicated and advanced, and the noise resistance can be improved by shortening the connection line.

  A computer circuit such as a one-chip microcomputer is mounted on each of the main control board 21, the effect control board 22, the image control board 23 and the payout control board 24. Therefore, in the present specification, the main control unit 21 and the effect control unit collectively refer to the circuits mounted on the control boards 21 to 24 and the liquid crystal interface board 28 and the operations realized by the circuits. 22 may be referred to as an image control unit 23 and a payout control unit 24. In addition, with respect to the main control unit 21, all or part of the effect control unit 22, the image control unit 23, and the payout control unit 24 serves as a sub control unit.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes the front frame 3 to which the glass door 6 and the front plate 7 are pivotally attached, and the wooden outer frame 1 outside the frame 3. Fixedly installed. On the other hand, the panel side member GM2 is replaced in response to the model change, and a new panel side member GM2 is attached to the frame side member GM1 instead of the original panel side member. In addition, all except the frame side member 1 are board side members GM2.

  As shown by the broken line frame in FIG. 3, the frame side member GM1 includes the power supply substrate 20, the dispensing control substrate 24, the emission control substrate 25, and the frame relay substrate 35, and these circuit substrates are Each is fixed at the appropriate position of the front frame 3. On the other hand, on the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display devices DS1 and DS2 and other circuit boards. And frame side member GM1 and board side member GM2 are electrically connected by connection connectors C1-C4 concentratedly arranged by one place.

  The power supply substrate 20 is connected to the main substrate relay substrate 32 through the connection connector C2, and is connected to the power supply relay substrate 33 through the connection connector C3. The power supply substrate 20 is provided with a power supply monitoring unit MNT that monitors the turning on and off of AC power. When the power supply monitor unit MNT detects that the AC power supply is turned on, it maintains the system reset signal SYS at the L level for a predetermined time, and then makes it transition to the H level.

  Further, when the power supply monitoring unit MNT detects that the AC power supply is shut off, it immediately causes the power supply abnormality signals ABN1 and ABN2 to transition to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  By the way, the system reset signal of the present embodiment is generated by the DC power supply based on the AC power supply. Therefore, after detecting the turning on of the AC power (normally, turning on the power switch) and increasing it to H level, the H level is maintained unless the DC power supply voltage decreases to an abnormal level. Therefore, the system reset signal SYS does not reset the CPU even if the AC power supply is momentarily interrupted while the DC power supply voltage is maintained. The power supply abnormality signals ABN1 and ABN2 are output even in the momentary interruption of the AC power supply.

  The main board relay board 32 outputs the power supply abnormality signal ABN1 output from the power supply board 20, the backup power supply BAK, and DC5V, DC12V, and DC32V to the main control unit 21 as it is. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as it is. Then, the effect control unit 22 outputs the received system reset signal SYS to the image control unit 23 as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without passing through the relay board, and the power supply abnormality signal ABN2 similar to that received by the main control unit 21 and the backup power supply BAK are directly connected with other power supply voltages. In the form of

  The system reset signal SYS output from the power supply substrate 20 is a power supply reset signal indicating that the AC power supply 24V is applied to the power supply substrate 20, and the one-chip microcomputer 40 of the effect control unit 22 and the image control unit The 23 built-in CPU circuits are designed to be reset with other circuit elements and internal circuits including VDP.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattling or noise is superimposed on the wiring cable, there is no possibility that the CPUs of the main control unit 21 and the payout control unit 24 are abnormally reset. Since the effect control unit 22 and the image control unit 23 execute the effect operation in a subordinate manner based on the control command from the main control unit 21, the output from the power supply substrate 20 is performed to avoid the complication of the circuit configuration. Using a system reset signal SYS.

  Each of the reset circuits RST provided in the main control unit 21 and the payout control unit 24 has a built-in watchdog timer, and each CPU unless it receives a regular clear pulse from the CPU of each control unit 21, 24. Is forcibly reset.

  Further, in this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the main control unit 21 and the one-chip microcomputer of the payout control unit 24. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each of the control units 21 and 24, and it is ON of the initialization switch SW operated by the clerk. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply substrate 20 to start necessary termination processing prior to the power failure or the end of business. The backup power supply BAK is a DC 5 V DC power supply that holds data of the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business closing or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before the power is turned off (power supply backup function). In this pachinko machine, the memory contents of the RAM of each one-chip microcomputer are designed to be held for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ′ ′ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a payout operation of the gaming ball. It receives a ball counting signal, a status signal CON related to an abnormality in the dispensing operation, and an operation start signal BGN The status signal CON includes, for example, an out-of-refilling signal, an insufficient payout error signal, and a lower balance full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 is completed after the power is turned on.

  Further, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch incorporated in each winning a prize mouth 16-18 on a game board, solenoids, such as an electrically driven tulip, are driven. The solenoids and the detection switch are configured to operate at the power supply voltage VB (12 V) distributed from the main control unit 21. Also, each switch signal indicating a winning state etc. to the symbol starting port 15 is converted to a TTL level or CMOS level switch signal by an interface IC operated with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). Then, it is transmitted to the main control unit 21.

  As described above, the effect control board 22, the image control board 23, and the liquid crystal interface board 28 are integrated by connector connection, and the effect control unit 22 is connected to the power supply board 20 via the power relay board 33. , And the system reset signal SYS (see FIG. 3 and FIG. 4A).

  The effect control unit 22 also receives a control command CMD and a strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive signal SDATA in synchronization with the clock signal CK to the driver ICs mounted on the lamp drive board 36, the lamp drive board 29, and the motor lamp drive board 30. A lamp group constituted by a large number of LED lamps and illumination lamps is driven to realize a lamp effect based on the control command CMD.

  In the case of the present embodiment, the lamp effect is performed by the three lamp groups CH0 to CH2, and the lamp drive board 36 clocks the lamp drive signal SDATA0 of CH0 via the frame relay boards 34 and 35. It is received in synchronization with the signal CK0 (clock synchronous serial communication). The lighting state of the series of lamp drive signals SDATA0 transmitted as serial signals is simultaneously updated by being output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level.

  The above points are the same for the lamp drive substrate 29, and the driver IC of the lamp drive substrate 29 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and the operation control signal ENABLE1 is at the active level. The lighting state of the lamp group CH1 is simultaneously updated at the timing when it changes to.

  On the other hand, the driver IC mounted on the motor lamp drive substrate 30 receives the lamp drive signal transmitted in the clock synchronous manner to drive the lamp group CH2, and receives the motor drive signal transmitted in the clock synchronous manner. The effect motor groups M1 to Mn configured of a plurality of stepping motors are driven. The lamp drive signal and the motor drive signal are a series of serial signals SDATA2 and are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives this is the timing when the operation control signal ENABLE2 changes to the active level. Then, the drive states of the lamp group CH2 and the motor groups M1 to Mn are updated.

  Further, the effect control unit 22 sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23, a system reset signal SYS received from the power supply substrate 20, and two types of DC voltages (12 V and 5 V). Is output. Then, the image control unit 23 drives the display devices DS1 and DS2 based on the control command CMD 'to execute various image effects. As shown in FIGS. 3 and 4A, the image control unit 23 has a composite chip 50 in which a built-in CPU circuit 51 having an internal configuration equivalent to a general purpose one-chip microcomputer and a VDP (Video Display Processor) 52 are built. It is composed mainly of Also, a control memory (PROM) 53 for storing control programs of the built-in CPU, a dynamic random access memory (DRAM) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 for storing a large amount of CG data necessary for image control. And is mounted.

  The CGROM 55 stores a large number of image data for realizing still images and moving images in a compressed state. Specifically, the compressed image data is divided into moving image compressed data and still image compressed data. A still image is a so-called sprite image, and is a single image that realizes a background image, a special symbol, a character, and the like. Then, each frame is drawn at a predetermined position of the display devices DS1 and DS2 in a predetermined posture. On the other hand, a moving image means a set of a plurality of (several frames of) still images that continuously change, and a plurality of still images are drawn continuously on the display device DS1, thereby achieving smooth movement. The behavior is reproduced.

  Here, the still image is compressed in a state in which the predetermined number of appropriately designed pixels is maintained in both the vertical direction and the horizontal direction. On the other hand, a moving image (see FIG. 18) with an effect image that changes rapidly is data constituting a basic image including a presentation main character, and the basic image data in which the outline of the image is fixed or smoothly changes, and the basic image. It is data that composes an overlapping effect image, and is managed by being divided into effect image data in which the contour of the image changes irregularly at a level that can not be expressed by a mathematical expression.

  That is, X pieces of original image data D0 for realizing X-frame image effects are divided into N (N frames) basic image data d1 and M (M frames) effect image data d2. . Here, N ≦ M ≦ X, and by appropriately combining N basic image data d1 and M effect image data d2, X image data is completed. Then, the N basic image data d1 is compressed while maintaining the appropriately designed prescribed pixel number, but for the M effect image data d2, the prescribed pixel number in the design is set to the vertical direction and the horizontal direction. Both directions are compressed, for example, after being reduced to 1/2.

  Therefore, the data amount of the M pieces of effect image data d2 is already reduced to 1⁄4 before the compression processing, and M pieces of data are compared with the compression rate for the N pieces of basic image data d1. Although the compression rate for the effect image data d2 is low, the overall compression effect can be enhanced. That is, assuming that the compression rates for X original image data D0, N basic image data d1, and M effect image data d2 are 1 / A, 1 / B, and 1 / C, respectively. , B >> A, the relationship of ND / B + MD / C / 4 <XD / A is established with respect to the prescribed pixel product D with certainty. The prescribed pixel product D is the product (D = H × W) of the prescribed pixel number W in the horizontal direction and the prescribed pixel number H in the longitudinal direction, and is proportional to the image data amount.

  The compressed data (moving image compressed data) of the basic image data d1 and the effect image data d2 separated and compressed are read out from the CGROM 55 as necessary, and are respectively decoded by the internal circuit of the VDP 52. Then, after the effect image data d2 after decoding is enlarged four times, it is overlapped with the basic image data d1 after decoding for each frame and stored in the frame buffer secured in the built-in VRAM 84, and this is stored in the display device DS1. It is output. On the other hand, moving image data not separated and compressed is read from the CGROM 55 and decoded by the internal circuit of the VDP 52, and then stored in a frame buffer secured in the built-in VRAM 84 and output to the display device DS1. For still images, the decoded sprite image is stored in the frame buffer based on the pasting position, the pasting posture, and the enlargement / reduction ratio designated by the display list, and output to the display devices DS1 and DS2. The display list will be described later.

  In any case, the image data generated by the VDP 52 is transmitted as the first and second LVDS (Low Voltage Differential Signaling) signals via the liquid crystal interface substrate 28 to the main display device DS1 and the sub It is transmitted to the display device DS2. The display device DS1 incorporates an LVDS reception unit for converting an LVDS signal into an RGB signal, and the display device DS1 is a DC signal including five pairs of LVDS signals from the liquid crystal interface substrate 28 and an LED backlight power supply. It is driven in response to the power supply voltage. On the other hand, the sub display device DS1 is driven by receiving the digital RGB signals converted by the liquid crystal interface substrate 28 and the DC power supply voltage including the LED backlight power.

  Subsequently, the configuration of the effect control unit 22 will be described in more detail based on FIG. 4 (a). As shown in FIG. 4A, the effect control unit 22 executes a process such as a sound effect, a lamp effect, a notice effect by the effect movable body, a data transfer and the like, and a one-chip microcomputer 40 (effect control CPU 40). A control memory (flash memory) 41 for storing various control programs EN and various effect data EN, and an audio processor 42 for reproducing and outputting an audio signal based on an instruction of the effect control CPU 40 set in the built-in registers RG0 to RGn An audio memory 43 for storing compressed audio data, which is original data of an audio signal to be reproduced, and a digital amplifier 46 for receiving an audio signal output from the audio processor 42 are configured.

  In the case of the present embodiment, the effect data EN stored in the control memory 41 includes scenario data for managing the progression of lamp effects and sound effects, lamp drive data for determining the blinking mode of the LEDs, and rotation of the motor. And motor drive data for determining the mode. The lamp drive data and the motor drive data are sequentially output one bit at a time to become a lamp drive serial signal and a motor drive serial signal.

  The one-chip microcomputer 40 incorporates a plurality of serial input / output ports SIO and a plurality of parallel input / output ports PIO. Here, serial output port Soi outputting the lamp drive signal of CHi or motor drive signal SDATAi in synchronization with clock signal CKi, and the origin sensor signal (serial signal) of motor groups M1 to Mn, to serial input / output port SIO And a serial port Si receiving the signal in synchronization with the clock signal CK3. Note that i is 0 to 2, and corresponds to three lamp groups CH0 to CH2 and motor groups M1 to Mn driven together with the CH2 lamp group.

  On the other hand, the parallel input / output port PIO is divided into output ports Po and Po 'and an input port Pi, and a control command CMD and a strobe signal STB from the main control unit 21 are input to the input port Pi. On the other hand, operation control signals ENABLE0 to ENABLE2 are outputted from the output port Po ', and a control command CMD' and a strobe signal STB 'are outputted from the output port Po. Specifically, after the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are stepped down in the buffer 44 to the logic level corresponding to the power supply voltage 3.3 V of the one-chip microcomputer 40 , And is supplied to the input port Pi twice in 8-bit units. Further, the interrupt signal STB is supplied to the interrupt terminal of the effect control CPU 40, and the effect control unit 22 is configured to obtain the control command CMD by the reception interrupt process.

  In addition to (1) abnormality notification and other notification control commands, the control command CMD acquired by the effect control unit 22 is (2) a control command for specifying an outline of various effect operations caused by winning in the symbol starting opening. (Variation pattern command) and a control command (design specification command) for specifying a symbol type are included. Here, the outline of the rendering operation specified by the fluctuation pattern command includes the total rendering time from the start of the rendering to the end of the rendering, and the result of the jackpot lottery.

  In addition, according to the result of the jackpot lottery, the symbol specification command includes information for identifying the jackpot type (15R positive variation, 2R positive variation, 15R normal, 2R normal, etc.) in the case of big hit, and it is lost In the case, it contains information identifying the loss. The outline of the rendering operation specified by the variation pattern command includes the total rendering time from the start of the rendering to the end of the rendering and the result of the jackpot lottery. In addition to these, it may be specified by the fluctuation pattern command including the presence or absence of reach effect or advance notice effect, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the variation control command is acquired, the effect control unit 22 subsequently performs an effect lottery, and further embodies the summary of the demonstration specified by the acquired variation pattern command. For example, the specific contents of the reach effect and the advance effect are determined. Then, according to the determined specific game content, the lamp effects by flashing of the LED group and the like, and the preparation operation of the sound effect by the speaker are performed, and the image control unit 23 is synchronized with the effect operation by the lamp and the speaker The control command CMD 'relating to the displayed image effect is output.

  In order to realize an image effect synchronized with such an effect operation, the effect control unit 22 controls the 16-bit control command CMD ′ together with the strobe signal (interrupt signal) STB ′ for the image control unit 23 through the output port Po. It is outputting. When the effect control unit 22 receives a symbol designation command, an error notification control command, or any other control command, the interrupt signal is generated in a state in which the 8-bit control command is combined into a 16-bit length. The signal is output to the image control unit 23 together with STB '.

As described above, the voice processor 42 of this embodiment accesses the voice memory 43 based on the instruction (set value by the voice command SND) received from the effect control CPU 40 to the built-in registers (voice control registers) RG0 to RGn. , And reproduces and outputs necessary audio signals. As illustrated, the voice processor 42 and the voice memory 43 are connected by a 26-bit voice address bus and a 16-bit voice data bus. Therefore, data of 1 Gbit (= 2 ²⁶ * 16) can be stored in the audio memory 43. In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) of 13 bit length, and is for one track of a series of background music A maximum of 8192 types (= 213) of (BGM) and a group of effect sounds (preliminary sounds) are stored corresponding to the phrase numbers. The phrase number is specified by the setting value of the voice command SND transmitted from the effect control CPU 40 to the voice control registers RG0 to RGn of the voice processor 42.

  The voice command SND has a plurality (2 or 3) bytes in length and is used in a Write application for transmitting a predetermined set value to any one of a large number of voice control registers RG0 to RGn built in the voice processor 42. Ru. However, the voice command SND of this embodiment is used not only for the Write application for writing a set value such as a phrase number but also for a Read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined voice control register RGi to be accessed is identified by a 1-byte register address.

  The setting (Write) of the setting value to the voice control register RGi does not necessarily need to be executed individually for each voice control register, and the SAC data stored in the voice memory 43 is designated to perform a group of voice control A series of setting operations for the registers RGi to RGj can also be completed. Here, SAC data refers to an aggregate of up to 512 pieces (maximum 1024 bytes) in which the register address (1 byte) of the voice control register RGi corresponds to the setting value (multiple bytes) to the voice control register RGi. Means In the present embodiment, such SAC data is stored in advance in the voice memory 43 as a necessary set, and one set of SAC data is specified by a SAC number of about 13 bits which is single ID information. It is supposed to be.

  Therefore, in the case of the present embodiment, the voice command SND for the Write application specifies a SAC number to specify one set of SAC data, or separately specifies a set value and a register address.

  As described in FIG. 4 (b), the effect control CPU 40 and the audio processor 42 execute parallel control data lines (data buses) CD0 to CD7 capable of transmitting and receiving 1-byte data, and operation management data. A chip for selecting an operation management data line (address bus) A0 to A1 of a 2-bit length that can be transmitted, a control signal line WR or RD of a 2-bit length that can control read / write operation, and an audio processor 42 It is connected by the select signal line CS.

  The parallel signal lines CD0 to CD7 are realized by the data bus of the effect control CPU 40, and the operation management data lines A0 to A1 are realized by the address bus of the effect control CPU 40, and are each connected to the effect control CPU 40 There is. Then, when the effect control CPU 40 executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS appropriately change, and the sound specified by the parallel signal lines CD0 to CD7 The read / write (R / W) operation with the control register RGi is realized.

  Specifically, as shown in the time chart of FIG. 4 (b '), the register address of the voice control register RGi and the write data to the voice control register RGi are respectively transmitted in parallel through parallel signal lines CD0 to CD7. Be done. Then, it is specified by the operation management data A0 to A1 whether one byte transmitted in parallel is a register address or write data (write data).

  Therefore, as shown in FIG. 4 (b), while changing the operation management data (address data A0 to A1) from [00] to [01], 1 byte data of the data bus is selected from [voice control register RGi A predetermined voice command SND is transmitted by transitioning from [register address] to [write data to voice control register RGi]. As in the case of transmitting the SAC number (13 bits), when the write data has a plurality of bytes, the operation management data A0 to A1 of [01] is changed to [00] → [01] → [01]. → Send multi-byte write data while repeating [01].

  The voice command transmitted in this manner is then effective as long as there is no communication error. However, when a communication error is recognized, such as when data of a plurality of bytes do not match each other, the voice command SND is not made effective. Then, the error flag of the voice control register RGn is set, but this error flag (status information STS) is produced by shifting the operation management data A0 to A1 of the address bus from [01] to [10]. The control CPU 40 can receive data by the read operation.

  As described above, in this embodiment, error information with a plurality of bit lengths (abnormality in the final cycle of causing the operation management data A0 to A1 to transition from [00] → [01] → ... [01] → [10] Time can get FFH). Then, by retransmitting the voice command SND that could not be properly parallel-transmitted, the voice presentation can be appropriately progressed. Therefore, according to the configuration of the present embodiment, it is possible to reliably eliminate the unnaturalness in which the sound effect suddenly and discontinuously occurs.

  Although the effect control CPU 40 receives status information STS including error information in parallel from the audio processor 42 in the configuration of FIG. 4B, the present invention is not limited to this configuration. That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the effect control CPU 40 when the audio processor 42 recognizes a communication error. In this case, in the interrupt processing program of the effect control CPU 40, a voice in which a communication error has occurred. You just have to resend the command. If such a configuration is adopted, the process of acquiring an error flag (status information STS), which is an unnecessary process in most cases, that is, the process of transitioning operation management data A0 to A1 to [10] may be omitted. it can.

  As shown in FIGS. 3 and 4A, in the present embodiment, the left and right speakers at the top of the gaming machine and the speakers at the bottom of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the audio processor 42 needs to generate three channels of audio signals, and parallel transmission of this generates complex wiring between the audio processor 42 and the digital amplifier 46.

  Therefore, in the present embodiment, in order to prevent the deterioration of the sound quality and to prevent the wiring from becoming complicated, the audio processor 42 and the digital amplifier 46 are connected by four signal lines, and specifically, Is suppressed to a total of 4 bit signal lines of the transfer clock signal SCLK, the channel control signal LRCLK, and the serial signals SD1 and SD2 of 2 bit length.

  Here, SD1 is a serial signal of PCM data specifying stereo signals R and L of left and right speakers disposed in the upper part of the gaming machine, and SD2 is a monaural signal of heavy bass speakers disposed in the lower part of the gaming machine. It is a serial signal of PCM data to be identified. Then, the audio processor 42 transmits the audio signal L of the left channel in a state in which the channel control signal LRCLK is maintained at the L level and the audio signal R in the right channel in a state in which the channel control signal LRCLK is maintained at the H level. It transmits (refer FIG.4 (c)). A monaural sound signal is transmitted because there is only one deep bass speaker in this embodiment, but it goes without saying that a stereo sound signal can be transmitted.

  In any case, in the present embodiment, since four types of audio signals can be transmitted by four cables, signal transmission without voice deterioration due to noise becomes possible with the minimum number of cables. That is, since serial transmission is performed, the number of cables is overwhelmingly smaller than parallel transmission.

  Such serial signals SD1 and SD2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. Then, in the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  4A, the buffer circuit 47 transfers the serial data SDATAi and the clock signal CKi output from the serial output port Soi of the serial input / output port SIO of the one-chip microcomputer 40 to the effect control board 22. To 49 are provided (i = 0 to 2).

  Here, the output buffer 47 transfers the ramp drive signal SDATA0 output from the serial output port So0 and the clock signal CK0 to the shift register circuit (driver IC) of the ramp drive board 36. The output buffer 48 transfers the lamp drive signal SDATA1 output from the serial output port So1 and the clock signal CK1 to the driver IC of the lamp drive substrate 29. As described above, the driver ICs mounted on the lamp drive boards 29 and 36 drive and drive the lamp groups CH0 and CH1.

  On the other hand, the buffer circuit 49 functions as an input / output buffer, and transfers the serial signal SDATA2 output from the serial output port So2 to the motor lamp drive substrate 30 together with the clock signal CK2. Further, an origin sensor signal (serial signal) indicating the origin position of the group of effect motors M1 to Mn is transferred to the serial input port Si of the one-chip microcomputer 40 in synchronization with the clock signal CK3.

  In the case of this embodiment, the serial signal SDATA2 transferred by the buffer circuit 49 is a lamp drive signal (serial signal) for lighting the lamp group CH2 and a motor drive signal (serial signal for rotating the effect motors M1 to Mn. And is configured to be continuous. The motor lamp driving board 30 divides the series of serial signals into 16-bit lengths, converts each 16-bit length into parallel signals, and executes a lamp effect and a movable announcement effect. Specifically, a series of lamp effects are executed as the effect operation selected by lottery in response to the control command CMD, and when the motor drive signal is received, the effect motors M1 to Mn are rotated to be appropriate. Movable notice effect is being performed.

  Next, as shown on the left side of FIG. 4A, in the present embodiment, the data bus and the address bus of the effect control CPU 40 extend to the liquid crystal interface substrate 28. This relationship is illustrated on the left side of FIG. 4A for convenience of explanation, but the clock circuit RTC is connected to the CPU by the lower 4 bits of the address bus of the effect control CPU 40 and the lower 4 bits of the data bus. It is configured to be arbitrarily accessible. Further, the memory element SRAM storing the game performance information enables random access of the effect control CPU 40 by 16 bits of the address bus of the effect control CPU 40 and lower 16 bits of the data bus.

  The clock circuit RTC is a clock IC (real time clock) for clocking the current date and time, and operates permanently with the memory element SRAM and the secondary battery BT charged with the power supply voltage received from the effect control board 22 doing. That is, while power is supplied to the gaming machine, the secondary battery BT (FIG. 5) is charged, and after the gaming machine is powered off, based on the charged secondary battery BT, The clocking operation of the clock circuit RTC is continued, and the effect data is also permanently stored and held (backup operation).

  As shown in FIG. 5, the clock circuit RTC of the embodiment is connected to the effect control CPU 40 through a 4-bit data bus, a 4-bit data bus, and a control bus RD + WR for a read / write operation. Then, the effect control CPU 40 adds important date information and day information and time information acquired from the clock circuit RTC and stores important game information and abnormality information regarding the game operation in the memory element SRAM. .

  This clock circuit RTC has two types of chip select terminals, CS1 and CS0, and allows access from the effect control CPU 40 on condition that the input voltage to each terminal is at a normal level. It has become. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detection unit ER, and when the CS1 terminal receives the output Vo at the abnormal level, the abnormality detection flag Fos of the clock circuit RTC is automatically It is supposed to be set to

  In the case of the present embodiment, this abnormality detection flag Fos is determined by the effect control CPU 40 when the power is turned on, together with other abnormality detection flags TEMP. If the abnormality detection flag Fos is in the set state, the date and time The time is to be notified. Therefore, if an abnormality in the clock function is recognized, this can be dealt with quickly.

  It should be noted that even if the voltage of the secondary battery BT drops when the power is shut off, the voltage level of the secondary battery BT quickly recovers upon power recovery and the CS1 terminal returns to the normal level, so access from the effect control CPU 40 is permitted. It will be done. Therefore, when the configuration of the present embodiment in which the determination processing of the abnormality detection flag Fos is provided is not adopted, there is a possibility that the abnormality of the clock circuit RTC can not be detected permanently.

  The clock circuit RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, at 21:50 every Friday, and the effect control CPU 40 that has received the interrupt signal IRQ The game information and the abnormality information accumulated in the memory element SRAM up to the present are appropriately counted.

  In addition, the game information to be totaled is the history information on the big hit state, and, for example, (1) the number of winnings on the symbol starting port required until the big hit state, (2) the symbol of the big hit state, Total value and statistical value of the big hit state whether or not it is a definite change, (3) Types of notice effects and reach effects that have reached the big hit state, (4) the number of consecutive chan, (5) the temporal number of balls paid out by consecutive chan The increase trend etc. are included. Then, the totalized information and the statistical information are appropriately notified according to the request of the player. The instruction of the player is specified, for example, by pressing the chance button 11 during demonstration effect, and the notification content is displayed on the display device DS.

  On the other hand, the abnormality information to be collected includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detections, and the detection time of the detection sensor that detects illegal activity. It includes the number of times of detection, the frequency of detection, the time of detection, and the like of an attempt to forcibly open the winning opening 16 with a wire or the like. Then, the totalized information is displayed on the main display device DS1 in response to the special operation by the attendant.

  As shown in FIG. 5A, the timepiece circuit RTC of the embodiment is configured by incorporating three internal register tables of Bank0 to Bank2. However, since the register table of Bank 2 relates to time setting and date setting, only the register tables of Bank 0 and Bank 1 are described in FIG. 5 (b) and FIG. 5 (c). In any case, each register table is composed of 4 bytes × 16 registers, and the current date and time counted by the internal circuit are written in the register table of Bank 0 (FIG. 5 (b)). Are configured to

  As shown in FIG. 5B, in the register table of Bank 0, bit 3 of the first register is the abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. It is a temperature abnormality flag TEMP shown. Then, in the present embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined to prevent the continuation of the abnormal time counting operation. Further, the clock circuit RTC is disposed close to the effect control CPU 40, and the temperature abnormality flag TEMP is repeatedly determined at an appropriate time interval to quickly detect the temperature abnormality of the effect control CPU 40.

  Further, in the register table of Bank 0, bit 0 of the fifteenth register is a Busy flag indicating that the register table is being updated. Then, in the present embodiment, the current date and the current time are acquired from the register table of Bank 0 under the condition that the Busy flag is in the non-Busy state (update completion). Therefore, in the present embodiment, there is no possibility of acquiring halfway or unreasonable clock information during the update operation, and the legitimacy of the clock information stored in the memory element SRAM is secured. For example, if the clock information being updated is updated from 1:59:59 to 2:00:00, there is a possibility that the clock information of 1: 0: 00 may be acquired.

  Also, the register table of Bank 1 is configured to be able to set the generation time of the interrupt signal IRQ. Therefore, in the present embodiment, the occurrence of an interrupt is instructed by setting 1 in bit 1 of register 1 of Bank 1 (Interrupt Enable), and day 0 of Friday is designated in registers 0 to 8 of Bank 1; The time information of 30 minutes 00 seconds is set.

  Subsequently, the image control unit 23 will be described in detail with reference to FIG. FIG. 6A is a circuit block diagram illustrating the composite chip 50 constituting the image control unit 23 including the related circuit elements. As shown in the figure, a built-in CPU circuit 51 and a VDP circuit 52 are built in the composite chip 50 of the embodiment. The built-in CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 which relays transmission and reception data of each other. A control memory (PROGRAM_ROM) 53 for storing control programs and necessary control data in a non-volatile manner and a work memory (RAM) 57 having a storage capacity of about 2 M bytes are connected to the CPUIF circuit 56. It is configured to be accessible from the built-in CPU circuit 51.

  The built-in CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer, and an image control CPU 63 that comprehensively controls image rendering based on the control program of the control memory 53, and the CPU when the program is out of control. A watchdog timer (WDT) 58 that resets forcibly, a RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area for the CPU, and a DMAC (Direct Memory Access Controller) that realizes data transfer without going through the CPU 60, a serial input / output port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel input / output port (PIO) 62 having a plurality of input ports Pi and output ports Po It is done.

  Although the expression “input / output port” is used for convenience, in the image control unit 23 as well, the input / output port includes an input port and an output port which operate independently. This point also applies to the input / output circuit 64p and the input / output circuit 64s described below.

  The parallel input / output port 62 is connected to an external device (effect control board 22) through the input / output circuit 64p, and the image control CPU 63 outputs the effect control unit 22 via the input circuit 64p and the parallel input port Pi. The control command CMD 'and the interrupt signal STB' are received. On the other hand, in this embodiment, the serial input / output port 61 and the DMAC 60 are not used.

  Next, the VDP circuit 52 will be described. The VDP circuit 52 includes an CGROM 55 for storing compressed data which is a component of still and moving images constituting image effects, and an external DRAM (Dynamic) having a storage capacity of about 4 Gbit. A Random Access Memory (DRAM) 54, a main display DS1 and a sub display DS2 are connected.

  Although not particularly limited, the CGROM 55 secures a storage capacity of 64 Gbits as a whole by using two memory elements MR (storage capacity 32 Gbits) shown in FIG. 7A. This memory element MR is divided into four block storage areas (H1, H0, L1, L0), and four sets of CE terminals (Chip Enable) and OE terminals (Output Enable) are provided correspondingly. .

Then, by asserting (activation) the CE terminal and the OE terminal of each group (H1, H0, L1, L0) in this order, the address data A0 in each storage area (H1, H0, L1, L0) is obtained. The 32-bit data selected in -A27 is configured to be able to memory READ at a stretch. That is, in the memory device MR, from 4 × 32 × ^{2 28} bits of relationship, the storage capacity is 32G bits.

  However, in the present embodiment, in order to speed up the read operation (memory READ), the storage areas (H1, H0, L1, L0) of four blocks are combined into two blocks. Specifically, as shown in FIG. 7A, the CEH0 terminal and the CEL0 terminal are connected directly and connected to the G_CE0 (Chip Enable) terminal of the VDP circuit 52, and the OEH0 terminal and the OEL0 terminal are connected directly. By connecting to the G_OE0 (Output Enable) terminal of the VDP circuit 52, a 64-bit storage bank # 0 (see shaded portion) combining the storage area H0 and the storage area L0 is configured. The CEH1 terminal and the CEL1 terminal are connected directly to each other to be connected to the G_CE1 terminal of the VDP circuit 52, and the OEH1 terminal and the OEL1 terminal are connected directly to each other to be connected to the G_OE1 terminal of the VDP circuit 52. A 64-bit storage bank # 1 which constitutes L1 is configured.

  The storage bank # 0 and the storage bank # 1 are connected to the CG bus IF portion of the VDP circuit 52 (see FIGS. 6 (a) and 6 (b)). Specifically, among the 31-bit address buses G_MA30 to G_MA0 in the CG bus IF section, 28-bit address buses G_MA30 to G_MA3 excluding the lower 3 bits are connected to the address terminals A0 to A27 of the memory element MR. The 28-bit address data is internally connected to all the storage areas (H1, H0, L1, L0).

  Further, since the address values of the address buses G_MA30 to G_MA3 increase or decrease by 8 units, when the VDP circuit 52 reads CG data, storage bank # 0 and storage bank # 1 are each for 8 addresses (1 page). 64-bit length data will be accessed collectively. The address space is as shown in FIG. 7B, and when the 28-bit data on the address buses G_MA30 to G_MA3 has the minimum value (all bits are 0), the G_CE0 and G_OE0 terminals are asserted in this order. As a result (see FIG. 7C), 64-bit data corresponding to addresses 0 to 7 (one page) of the storage bank # 0 is read.

  Next, when the address values of the address buses G_MA30 to G_MA3 are incremented, the G_CE0 terminal and the G_OE0 terminal are asserted to read 64-bit data at addresses 8 to 15 of the storage bank # 0. When the G_CE1 and G_OE1 terminals are asserted while the 28-bit address buses G_MA30 to G_MA3 are at the minimum value, 64-bit data in the storage bank # 1 is read, and the values on the address buses G_MA30 to G_MA3 are incremented. After that, when the G_CE1 terminal and the G_OE1 terminal are asserted, the next 64-bit data of the storage bank # 1 is read.

  However, when performing high-quality moving image effects on a large screen, it is often desirable to sequentially access the series of CG data stored in the CGROM 55 at a higher speed. Therefore, in this embodiment, the memory interleaving method shown in FIG. 8 is employed, and a series of CG data are stored across the storage banks by switching the storage bank # 0 and the storage bank # 1 every 64 bits. There is.

  Therefore, at the time of memory READ, after 28 bits of address data of address buses G_MA30 to G_MA3 are determined, first, G_CE0 and G_OE0 terminals are asserted to read 64 bits of storage bank # 0, and then the same address data On the other hand, the 64 bits of the storage bank # 1 are read by asserting the G_CE1 terminal and the G_OE1 terminal. As described above, in the present embodiment, by taking the memory READ operation in units of 128 bits, the waste caused by the address access time Tacc for every 64 bits is eliminated, and high-speed sequential access operation is realized. It is also possible to randomly access a group including an arbitrary address by specifying a storage bank and executing a memory READ operation.

  By the way, instead of the memory interleaving method, it is also preferable to adopt a page read method shown in FIG. In this case, a series of CG data is divided into storage bank # 0 and storage bank # 1 and stored continuously. Then, the address value 28 bits of the address buses G_MA30 to G_MA3 are determined, and for example, after the G_CE0 terminal and the G_OE0 terminal are asserted to cause the memory READ of the memory bank # 0 to be 64 bits, the memory bank # 0 remains selected. By incrementing the lower 4-bit address values in order, it is possible to perform high-speed memory READ (sequential access) of CG data (64 × 16 bits) of up to 16 pages.

  In parallel transmission, the problem of skew due to the difference in transmission rate for each bit data inevitably arises, but the skew of 4-bit data (G_MA3 to G_MA7) is not as problematic as the skew of 28-bit data (G_MA30 to G_MA3) By rapidly incrementing 4-bit address data, a series of CG data can be read at high speed by memory READ.

  In the present invention, although the data amount of CG data for realizing moving image effects is effectively suppressed, the memory interleave method and the page read method can be used without using a particularly expensive memory element. It is possible to realize high-quality animation effects. In addition, since the memory READ process is completed quickly, it is possible to secure a sufficient processing time for the decoding process after the memory READ and other drawing processes.

  The CGROM 55 has been described above in detail, so that the internal configuration of the VDP circuit 52 will be described by returning to FIG. As shown in FIG. 6, the VDP circuit 52 has a group of registers 70 in which various operation parameters defining the operation of VDP are set, and about 48 M bytes used when generating image data to be displayed on the display devices DS1 and DS2. VRAM (video RAM) 71, a data transfer circuit 72 that controls data transmission and reception between each part inside the chip and data transmission from outside the chip, a preloader 73 that executes the above-described preload operation, and image data read from the VRAM 71 Three lines (A / B / C) of display circuits 74 that execute appropriate image processing in parallel, a graphics decoder 75 that decodes (decodes and decompresses) compressed data read from CGROM 55, and a still after decoding Image data for one frame of each of the display devices DS1 and DS2 by appropriately combining image data and moving image data , A geometry engine 77 that generates a stereoscopic image by appropriate coordinate transformation as part of the operation of the drawing circuit 76, an SMC unit 78 capable of transmitting and receiving serial data, and three systems (A / B / Relaying data transmission / reception between an output selection unit 79 appropriately selecting and outputting the output of the display circuit 74 C), an LVDS unit 80 converting image data output from the output selection unit 79 into an LVDS signal, and the CPUIF circuit 56 The CPUIF unit 81, the CG bus IF unit 82 for relaying data reception from the CGROM 55, the DRAM IF unit 83 for relaying data transmission and reception with the external DRAM 54, and the VRAMIF unit 84 for relaying data transmission and reception with the VRAM 71 are provided. Is configured.

  FIG. 6B shows the relationship among the CPU IF unit 81, the CG bus IF unit 82, the DRAM IF unit 83, and the VRAM IF unit 84, the register group 70, the CGROM 55, the DRAM 54, and the VRAM 71. As described above, the CGROM 55 of the embodiment has a storage capacity of 64 Gbits as a whole, and functions of the memory interleave system or the page read system by the function of the CG bus IF unit 82. Then, CG data acquired by the CG bus IF unit 82 is transferred to the external DRAM 54 as preload data via the DRAM IF unit 83 in the present embodiment. The preload operation is not essential, and the data transfer destination is not limited to the external DRAM 54, and may be the VRAM 71. For example, when the preload operation is not performed, the CG data is transferred to the VRAM 71 via the VRAM IF unit 84.

  The data transfer circuit 72 shown in FIG. 6A is a circuit that executes a data transfer operation between a resource (storage medium) in the VDP circuit and an external storage medium as a transfer source port or a transfer destination port. . The transfer source port includes, in addition to the VRAM 71, a storage medium (resource) connected to the CPU bus, the CG bus, and the external DRAM bus. Similarly, the transfer destination port includes, in addition to the VRAM 71, storage media connected to the CPU bus, the CG bus, and the external DRAM bus. The data transfer circuit 72 is also in charge of transmitting the display list DL for specifying a display image for one frame by a group of drawing commands to the preloader 73 and the drawing circuit 76.

  The display list DL is composed of a group of drawing commands described in the order of drawing. The drawing command includes a command that defines what kind of image is drawn at which position of one frame, and a storage position (source address) such as a CGROM of an image to be drawn is also specified. When the original image data D0 is moving image data divided into the basic image data d1 and the effect image data d2, the effect image data d2 after decoding is doubled in the vertical and horizontal directions, and the basic after decoding is performed. It is specified in the display list to be overwritten on the image data.

  Further, in the present embodiment, since two display devices DS1 and DS2 are used, it is necessary to respectively generate one frame of image data in the frame buffers FBa and FBb for the display devices DS1 and DS2 secured in the VRAM 71. Yes (see FIG. 9B), the drawing positions of the frame buffers FBa and FBb are specified by a predetermined drawing command. In addition, although it does not specifically limit, a moving-image effect is performed only by display apparatus DS1 in a present Example.

  The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers CG data on the CGROM 55 referenced therein to the preload area of the DRAM 54 specified in advance. . At this time, the preloader 73 outputs the display list DL in which the CG data reference destination is rewritten to the address after transfer. The rewritten display list DL is transmitted by the data transfer circuit 72 to the drawing circuit 76. In the present embodiment, a sufficient storage area is secured by setting the preload area in the external DRAM 54. For example, even if CG data for a plurality of frames are preloaded at once, no problem occurs. . However, in the present embodiment where CG data of one frame is read ahead, in place of the external DRAM 54, a preload area can be set in the built-in VRAM 71.

  The drawing circuit 76 analyzes the drawing commands of the display list DL sent by the data transfer circuit 72 in order, and cooperates with the graphics decoder 75, the geometry engine 77, etc., in a frame buffer formed in the VRAM 71. It is a circuit which draws the image for one frame of each display apparatus DS1 and DS2.

  As described above, in the present embodiment, since the preloader 73 is made to function, the reference destination of CG data in the display list DL is not the CGROM 55 but the preload area set in the DRAM 54 or VRAM 71. Therefore, random access to CG data generated during execution of drawing by the drawing circuit 76 can be performed quickly, and high-resolution moving pictures with high motion can be drawn without any problem. That is, according to the present embodiment, complex and sophisticated image effects can be performed without using a special expensive element as the CGROM 55.

  The frame buffer FB formed in the VRAM 71 is a double buffer divided into a drawing area and a display area, and uses two areas alternately by switching applications. Further, in the present embodiment, since two display devices DS1 and DS2 are connected, frame buffers FBa / FBb of two sections are secured. Therefore, the drawing circuit 76 draws image data of one frame in the drawing area of the frame buffer FBa for the display device DS1, and also draws image data of one frame in the drawing area of the frame buffer FBa for the display device DS2. Will draw. When image data is written in the drawing area, the display circuit 74 reads the image data of the display area and outputs the image data to the display devices DS1 and DS2.

  The display circuit 74 is a circuit that reads out the image data of the frame buffers FBa and FBb, performs final image processing, and outputs the image data (see FIG. 9E). The final image processing includes, for example, scaling processing for enlarging / reducing the image, subtle color correction processing, and dithering processing for minimizing the quantization error of the entire image. After these image processings, digital RGB signals (24 bits in total) are output together with the horizontal synchronization signal and the vertical synchronization signal. As shown in FIG. 9E, in the present embodiment, three display circuits A / B / C for executing the above operation in parallel are provided, and each display circuit A / B / C The image data of the frame buffer FBa / FBb / FBc corresponding to is read out, and the above-mentioned final image processing is executed. However, in the present embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit C does not function.

  In relation to this operation, the output selection unit 79 of this embodiment transmits the output signal of the display circuit A to the LVDS unit 80a, and transmits the output signal of the display circuit B to the LVDS unit 80b (see FIG. 9 (e)). Then, the LVDS unit 80a converts the image data (digital RGB signal of 24 bits in total) into an LVDS signal, adds a pair for transmitting a clock signal, and outputs it to the main display device DS1 as all five pairs of differential signals. doing. The main display device DS1 incorporates a conversion reception section RV for an LVDS signal, restores the RGB signal from the LVDS signal, and displays an image corresponding to the output of the display circuit A.

On the other hand, the LVDS unit 80b converts and receives all four pairs of differential signals by adding a pair for transmitting a clock signal for each of six bits (total 18 bits) excluding the lower two bits of each eight-bit digital RGB signal An image display is realized by a total of 18 bits of RGB signals that are output to the unit RV and received by the sub display device DS2 from the conversion reception unit RV (THCV 214). This is because the sub display device DS2 does not need the 2 ⁸ * 2 ⁸ * 2 ⁸ resolution, and 2 ⁶ * 2 ⁶ * 2 ⁶ resolution is sufficient. However, the present invention is not particularly limited, and all 5 pairs of differential signals may be transmitted to realize 2 ⁸ * 2 ⁸ * 2 ⁸ resolution.

  Also, it is not always necessary to use an LVDS signal. For example, when the transmission distance is short, the digital RGB signal is directly transmitted to the display device via the digital RGB unit 80c or when the transmission distance is long. The digital RGB signal is converted to a V-By-one (registered trademark) signal in the conversion transmitter TR ′ and transmitted to the conversion receiver RV ′, and then converted back to the digital RGB signal in the conversion receiver RV ′. Is also suitable. Note that although the broken line in FIG. 9E indicates this operation mode, any output signal of the display circuit A / B / C can be set by appropriately setting the operation of the output selection unit 79. The above operation is possible.

  Next, the SMC unit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a motor controller. Then, while outputting the LED drive signal and the motor drive signal in synchronization with the clock signal to the LED / Motor driver (driver IC incorporating the shift register) mounted on the external substrate, the latch pulse is output at appropriate timing. It is configured to be able to output.

  Regarding the internal circuits of the VDP circuit 52 described above and the operation thereof, the operation contents to be executed by the internal circuit are defined by the operation parameters (set values) set in the register group 70 by the image control CPU 63 and the execution state of the VDP circuit 52 Can be specified by READing the operation status value of the register group 70. The register group 70 means a large number of registers mapped to a memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the image control CPU 63, and the image control CPU 63 transmits operating parameters via the CPUIF unit 81. The WRITE (setting) operation and the READ operation of the operation status value are performed (see FIG. 6 (b)).

  Settings related to data transfer processing by data transfer circuit 72 between “System control register” where initial setting values related to system operation such as interrupt operation are written in register group 70 and internal circuits of image control CPU 63 and VDP circuit 52 The “data transfer register” in which values and the like are written, the “GDEC register” that specifies the execution status of the graphics decoder 75, the “draw register” in which the write command and setting values for the draw circuit 76 are written, The “preloader register” into which the setting value regarding the operation of the is written, the “display register” into which the setting value regarding the operation of the display circuit 74 is written, and “the LED into which the setting value regarding the LED controller (SMC unit 78) is written Settings related to the “control register” and the motor controller (SMC unit 78) There and a "motor control register" to be written.

  Then, the image control CPU 63 writes an appropriate set value into any of the register group 70, whereby the internal operation of the VDP circuit 52 is realized. Therefore, the image control CPU 63 realizes an image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set values for the registers constituting the register group 70 described above. In this embodiment, since the effect control CPU 40 of the effect control board 22 takes charge of lamp effects and motor effects, the SMC unit 78 is not used, and setting values are written in the LED control register and motor control register. There is nothing to be done.

  Subsequently, with regard to the control operation of the image effect performed using the two display devices DS1 and DS2, reference is made to the flowcharts of FIG. 9A to FIG. 9D and the time chart of FIG. While explaining. The image effect is realized by the image control CPU 63 receiving the control command CMD 'from the effect control CPU 40, and the VDP circuit 52 that is instructed by the image control CPU 63 to function. As described above, the instruction from the image control CPU 63 to the VDP circuit 52 is specified by the operation parameter written to the register group 70.

  As shown in FIG. 9, the image rendering operation includes a display list update process (FIG. 9A) executed by the image control CPU 63 every predetermined time, and a preloader 73 that operates based on the display list received from the image control CPU 63. This is realized by the sequence operation (FIGS. 9B to 9D) of the drawing circuit 76 and the display circuit 74. Note that the image control CPU 63 registers the necessary operation parameters into the register group at power reset and necessary timing thereafter so that the preloader 73, the drawing circuit 76, and the display circuit 74 realize the sequence operation described below. It is set to 70.

  To explain based on the above, the image control CPU 63 starts the list update process (ST1) every 1/30 seconds, for example, and starts the sequence operation of the preloader 73, the drawing circuit 76, and the display circuit 74 (ST2). ). As shown in FIG. 10A, the image control CPU 63, the preloader 73, the drawing circuit 76, and the display circuit 74 execute their own operations in parallel intermittently at fixed time (δ) intervals. Become. FIG. 10B schematically shows the contents of each memory for the built-in RAM 59 of the CPU circuit, the built-in VRAM 71 of the VDP circuit, the external DRAM 54, and the CGROM 55.

  To continue the description of the operation of the image control CPU 63, following the process of step ST2, the image control CPU 63 updates the display list DL based on the rendering scenario (ST3). Here, the rendering scenario is a realization of the image rendering specified by the control command CMD 'received from the rendering control CPU 40. That is, in the rendering scenario, a series of moving images that continue for a certain period of time, and a still image (including a background image and a preview image) for which the drawing position, the arrangement attitude, and the enlargement / reduction ratio are appropriately defined The start time and end time of the animation effect, (2) which still picture, at which time, at which position, how to draw, etc. are specified.

  Note that, although the motion picture effect is said, the drawing image of the display device only changes quickly and smoothly, and a still image in that the same or different next image data is drawn on the display device at regular intervals. Is the same as Further, in this embodiment, since different images are displayed on the two display devices DS1 and DS2, the rendering scenario is divided into two corresponding to this configuration.

  Then, the image control CPU 63 refers to the rendering scenario having such a configuration, and at each timing (T1, T1 + δ, T1 + 2δ,...), A group of drawing commands specifying the display image of the display devices DS1 and DS2 The listed display list DL is generated. The display list DL specifies, for moving images, which part of moving images is to be displayed temporally by specifying the storage position of the CGROM, and for still images such as sprite images, it is stored in the CGROM. It defines, for example, at which position of the display device and how to draw the image.

  Next, the display list DL configured in this way is transferred to a defined area of the external DRAM 54, and it waits for the next list update timing to be reached (ST4). In FIGS. 10A and 10B, as a result of the operation of the image control CPU 63 starting from timing T1, a display list DL1 is generated and transferred to the external DRAM 54 at timing T1 ′. It is done.

  In this embodiment, the display list DL1 is rewritten by the preloader 73 at timing T1 + δ delayed by one timing and drawn by the drawing circuit 76 based on the display list DL1 after rewriting at timing T1 + 2δ further delayed by one timing. It is processed. Then, at timing T1 + 3δ delayed by one more timing, based on the display operation of the display circuit 74, the display screen specified by the display list DL1 appears on the display devices DS1 and DS2.

  As described above, in this embodiment, the preloader 73, the drawing circuit 76, and the display circuit 74 are configured to operate with a delay by one timing. Therefore, the preloader 73 started from the timing T1 processes the unprocessed and oldest display list of the external DRAM 54, specifically, processes the display list generated at the timing before one. become. In other words, the display list DL1 generated by the image control CPU 63 at the timing T1 is processed as follows based on the operation of the preloader 73 started at the timing T1 + δ.

  Hereinafter, the timing after the timing T1 + δ will be described. The preloader 73 analyzes the display list DL1 stored in the defined area of the external DRAM 54, which is the unprocessed and oldest display list. Then, when a drawing command required for CG data of CGROM is detected in the display list DL1, the CG bus IF unit 82 functions to acquire the group of CG data in the CG data area of the external DRAM 54. . Further, the storage position of CG data in the drawing command related to the pre-reading (preloading) process is rewritten from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (SS10).

  The above operation is repeatedly executed each time a drawing command requiring CG data of CGROM is detected, and all CG data (compressed data) for constructing one frame of the display device DS1 and the display device DS2 are all The CGROM 55 is secured in the CG data area of the DRAM 54. The CG data once secured in the CG data area of the DRAM 54 is managed so as to be usable thereafter, so when using the CG data secured at a timing earlier than that, the preload processing (SS11) is skipped Then, only processing (SS10) is executed to rewrite the storage position of CG data from the source address value of the CGROM 55 to the address value of the CG data area secured in the DRAM 54 (see the broken line in FIG. 9B).

  Then, with regard to the display list DL1 specifying one frame of each of the display device DS1 and the display device DS2, the transfer processing of necessary CG data to the DRAM 54 and the rewrite processing of the display list are performed for all drawing commands described therein. If it ends, it will stand by until the next preload operation started intermittently (SS12). In FIG. 10B, a state in which necessary CG data is transferred from the CGROM 55 to the external DRAM 54 is described by an arrow at timing T1 + δ. The transferred CG data remains compressed.

  Subsequently, a drawing operation performed by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, etc. in cooperation with each other will be described with reference to FIG. 9C. As shown in FIG. 10A, this drawing operation is repeated every fixed time (δ), but for convenience, in the following description, the drawing operation after timing T1 + 2δ executed based on the display list DL1 after rewriting Explain.

  The drawing circuit 76 sequentially analyzes drawing commands described in the display list DL1 which is the unprocessed and oldest display list among the display lists stored in the external DRAM 54 (SS20), The graphics decoder 75 and the geometry engine 77 operate on still images and moving images specified by Since the drawing circuit 76 processes the display list DL1 after rewriting, the reference destination of the CG data regarding the still image and the moving image is the external DRAM 54.

  Then, the still picture data and the moving picture data decoded by the graphics decoder 75 are expanded and developed in the still picture decoding area and the moving picture decoding area secured in the built-in VRAM 71, respectively (SS22 to SS23). Next, the rendering process is executed by writing the decoded still image data and moving image data in a predetermined position of the frame buffer FB of the VRAM 71 in a rendering manner defined by a rendering command (SS24).

  Although the drawing mode includes the drawing position in the frame buffer FB, in the case of a sprite image or the like, the drawing attitude, the enlargement / reduction ratio, etc. may be further defined, and the geometry engine 77 functions. When the original image data D0 is moving image data divided into basic image data d1 and effect image data d2, the decoded effect image data d2 is expanded in the vertical and horizontal directions and then decoded. It is overwritten on the basic image data.

  As shown in FIG. 9E, in this embodiment, the first frame buffer FBa and the second frame buffer FBb are secured in the frame buffer FB, corresponding to the two display devices DS1 and DS2. A drawing operation is realized by writing decoded data of a still image or a moving image at a predetermined position of the frame buffer FBa / FBb specified by the command (SS24). As described above, the frame buffer FBa / FBb has a double buffer structure divided into a drawing area and a display area, and in the drawing operation (SS24), the drawing area of the frame buffer FBa / FBb is more accurately determined. Decoded data is to be written at a predetermined position in. Although different from the embodiment, if the third frame buffer FBc is secured in the frame buffer FB, it is possible to draw the image of the third display device in parallel.

  In any case, after the process of step SS22 or step SS23, a necessary image is drawn at a predetermined position of a predetermined frame buffer FBa / FBb based on the decoded data (moving image / still image) (SS24). Then, since this process is executed in the order of the drawing commands from the top to the end of the display list DL1, the image drawn first is to be overwritten by the image drawn in the same area thereafter .

  When the drawing process for all drawing commands is completed, the next drawing operation started intermittently is put in a standby state (SS25). In FIG. 10B, it is described by an arrow that a necessary image is drawn in the frame buffer FB (FBA + FBb) at timing T1 + 2δ.

  Finally, the operation of the display circuit 74 will be described based on FIG. 9 (d). Although this display operation is also repeated every fixed time (δ), for convenience, in the following description, the display operation after timing T1 + 3δ shown in FIG. 10 will be described. As described above, at this timing, the image data based on the display list DL1 is secured in the drawing area of the frame buffer FBa / FBb. And this drawing area functions as a display area in the display operation after timing T1 + 3δ.

  As shown in FIG. 9E, the VDP circuit 52 is provided with three display circuits A / B / C to be executed in parallel. In this embodiment, two display circuits A / B are provided. Only is set to work. Then, the display circuit A / B reads the image data stored in the display area of the frame buffer FBa / FBb corresponding to each, and outputs the image data to the output selection unit 79 (SS30).

  Thereafter, based on the operation of the output selection unit 79, the image data of the frame buffer FBa output by the display circuit A is transmitted to the main display device DS1 via the LVDS unit 80a as described above. . Further, as described above, the image data of the frame buffer FBb output from the display circuit B is transmitted to the sub display device DS2 via the LVDS unit 80b. In FIG. 10B, it is described by an arrow that the image data of the display area of the frame buffer FB (FBA + FBb) is output at timing T1 + 3δ.

  As described above, in this embodiment, since the preloader 73, the drawing circuit 76, and the display circuit 74 perform the series of operations in parallel and concurrently execute the processing they are in charge of, a high image quality and a high speed can be achieved. It is possible to realize an image effect of a changing large screen without any problem. In particular, in the present invention, since two display devices are used, the control burden of image rendering is large, so the parallel operation of this embodiment is highly valuable.

  Moreover, in the present invention, since the preloader 73 is operated prior to the drawing circuit 76 to pre-read CG data in the RAM, it is necessary to use random access memory (mask ROM etc.) as the CGROM 55. Instead, sequential access memory can be used, and the manufacturing cost can be reduced.

  As mentioned above, although the Example of this invention was described in detail, the specific description content does not specifically limit this invention. For example, in the above embodiment, as shown in FIG. 6A, the composite chip 50 incorporating the built-in CPU circuit 51 and the VDP circuit 52 is used, but such composite chip 50 is used. It is also preferable to use a one-chip microcomputer having a configuration different from that of the VDP circuit 52 instead of the built-in CPU circuit 51.

  In the above embodiment, as shown in FIG. 3, the image control is controlled by the image control CPU 63 which receives the control command CMD 'from the effect control CPU 40 controlling the sound effect and the lamp (motor) effect. It is also preferable that the image control CPU 63 collectively control the voice effect, the lamp effect, the motor effect, and the image effect uniformly by receiving the control command CMD of the main control unit 21 directly without using the CPU 40. It is.

  FIG. 11 shows a configuration in which the image control CPU 63 incorporated in the composite chip 50 controls all the rendering operations. In the case of such a configuration, the process of transmitting and receiving the control command CMD 'becomes unnecessary, so the circuit configurations of the rendering interface board 22 and the image control board 23 are simplified, and the control command CMD' is transmitted and received. In addition to the reduction of the control load, there is an advantage that the problem of transmission error of the control command CMD 'and the synchronization deviation between the image effect and other effects are eliminated. In FIG. 11, the composite chip 50 is used, but instead of using the VDP circuit 52 and the image control CPU 63 built in the composite chip 50, a higher performance one-chip microcomputer and a dedicated VDP circuit are used. It is also preferred to use

  FIG. 12 illustrates the main part of FIG. 11 in detail, and shows a case where the image control CPU 63 incorporated in the composite chip 50 controls the sound effect, the lamp effect, the motor effect, and the image effect. . Further, FIG. 13 illustrates the composite chip 50 of FIG. 12 together with other circuit components.

  As shown in FIG. 13, in this embodiment, the control command CMD from the main control unit 21 is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. Also, the strobe signal STB is supplied to the interrupt terminal of the image control CPU 63 via the input / output circuit 64p, thereby activating the reception interrupt process. Therefore, the image control CPU 63 having grasped the control command CMD based on the reception interrupt process uniformly controls the sound effect, the lamp effect, the motor effect, and the image effect corresponding to the control command CMD through the effect lottery and the like. It will be done.

  By the way, in the embodiment of FIGS. 11 to 13, the SMC unit (Serial Management Controller) 78 of the VDP circuit 52 is used for the lamp effect and the motor effect. As described above, the SMC unit 78 incorporates an LED controller and a motor controller, and is configured to output a serial signal in a clock synchronous system. Further, the motor controller is configured to be able to output a latch pulse at an arbitrary timing based on a set value to a predetermined register 70, and is configured to be able to input a serial signal in a clock synchronous system.

  Therefore, in the present embodiment, while the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, the latch pulse is output as the operation control signal ENABLE at an appropriate timing. . Further, origin sensor signals SN0 to SNn from the effect motor groups M1 to Mn are serially input in a clock synchronous system.

  As shown in FIG. 12, the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 drive the lamp drive boards 36, 29 and the lamp motor via the output buffers 47, 48, 49. It is transmitted to the substrate 30. The sensor signals SN0 to SNn are serially input from the motor lamp drive board 30 to the SMC unit 78 via the input buffer 49.

  In the configurations of FIGS. 11 to 13, it is not essential to use the SMC unit 78. That is, since the general-purpose serial input / output port SIO is built in the built-in CPU circuit 51, it is possible to use them to execute the lamp effect and the motor effect. In FIG. 13, clock signals CK0 to CK2 and drive signals SDATA0 to SDATA2 are output via the input / output circuit 64s internally connected to the serial input / output port SIO, and the operation control via the input / output circuit 64p is performed. The configuration in which the signals ENABLE0 to ENABLE2 are output is indicated by a broken line. Although the term “input / output port” or “input / output circuit” is used for convenience, it is the output port or output circuit that actually functions.

  The preloading operation can also be appropriately changed, including the use or non-use thereof. FIG. 14 shows an embodiment in which the preload operation is omitted, and the display list update process by the image control CPU (FIG. 14 (a)), the drawing operation by the drawing circuit 76 etc. (FIG. 14 (b)), and the display circuit The display operation by 74 (FIG. 14 (c)) shows an operation mode which is repeated at fixed time intervals. In the case of such an embodiment, for example, the display list updated at the timing T1 is activated at the timing T1 + 2δ, and a display screen corresponding to the display list is displayed on the display devices DS1 and DS2. In the case of using a randomly accessible memory such as a normal mask ROM, the preload operation by the preloader 73 is not particularly required, and it is preferable to adopt the configuration as shown in FIG.

  On the contrary, when using the sequential access memory, the preloader 73 is suitably used, but it is not necessary to preload every CG data of one frame. FIG. 15 shows the process of updating the display list by the image control CPU (FIG. 15 (a)) and the multiple preload process by the preloader 73 (FIG. 15 (b)) in the case of collectively preloading a plurality of frames of the display screen. Is shown. Although the drawing operation by the drawing circuit 76 etc. and the display operation by the display circuit 74 are not described, as in the case of FIG. 9 and FIG. 10, every predetermined time δ (eg 1/30 seconds) It is repeatedly executed.

  Hereinafter, the list update process will be described. The image control CPU starts the drawing operation by the drawing circuit 76 etc. and the display operation by the display circuit 74 every predetermined time (ST11), but until the update timing is reached, the display It waits without updating the list DL (ST12). Then, when the update timing is reached, a plurality of n display lists DL1 to DLn are collectively generated (ST13), and, for example, they are transferred to the external DRAM 54 and the preloader 73 is activated (ST14).

  Then, in response to this processing, the preloader 73 starts operation, and among the plurality of display lists stored in the external DRAM 54, analysis processing is sequentially started from the unprocessed and oldest display list, The display list is rewritten for the address value of the CGROM (SS10). Then, if necessary, the CG data of the CGROM is pre-read (SS11).

  In this embodiment, the above processes (SS10 to SS11) are not limited to a single display list DL, and all of the plurality of n display lists DL1 to DLn may be ordered as long as other operations do not interfere. Is executed (SS12 ', SS12). The case where another operation is disturbed is, for example, the case where the preload area (see FIG. 10B) secured in the external DRAM 54 is full of unused CG data, In such a case, in order to avoid overwriting CG data, the process waits for a vacancy in the preload area (SS12 '). In the list update process, it is also preferable to make the process of step SS12 'unnecessary by setting the number of display lists DL1 to DLn to be generated to an appropriate value.

  In any case, the above operation is repeated until all the display lists DL1 to DLn have been processed (SS12). According to this embodiment, the problem of concentration of READ access of a large amount of CG data at a certain timing which can occur in the embodiment of FIG. 9 is solved, and the access load to the CGROM can be smoothed. The list updating process of FIG. 9 and the multiplex list process of FIG. 15 may be mixed, and the process may shift to the multiplex list process of FIG. 15 only when the READ access is concentrated.

The bus width of the CG bus IF unit 82 and the configuration of the CGROM 55 are not particularly limited to the configuration shown in FIG. FIG. 16A shows a circuit configuration in which the data bus width of the CG bus IF unit 82 is set to 128 bits and four memory elements MR having a storage capacity of 32 × ²³⁶ bits are connected in parallel. .

That is, in this circuit configuration, the total data amount is 2 ⁵ × 2 ³⁶ × 2 ² = 2 ⁴³ bits = 2 ⁴⁰ bytes. In this circuit configuration, 32-bit CG data is continuously stored in four memory elements, and when G_CE0 (Chip Enable) and G_OE0 (Output Enable) are asserted in this order, a 128-bit CG is generated. The data is collected and the memory READ is performed. Therefore, it is suitable for high speed sequential access / random access to a group of CG data.

  FIG. 16B shows an interleaving circuit configuration, and each memory element MR is provided with four 32-bit storage banks (# 0 to # 3). Then, the CE0 terminal and CE2 terminal of each memory element MR are connected directly to be connected to the G_CE0 (Chip Enable) terminal of the VDP circuit 52, and the OE0 terminal and OE2 terminal are connected directly to connect the G_OE0 (Output Enable) of the VDP circuit 52. By connecting to the terminals, a 64-bit even area bank EV (# 0 and # 2) is configured.

  Similarly, the CE1 terminal and CE3 terminal of each memory element MR are connected directly to be connected to the G_CE1 (Chip Enable) terminal of the VDP circuit 52, and the OE1 terminal and OE3 terminal are connected directly to connect the G_OE1 (Output Enable of the VDP circuit 52). By connecting to the) terminal, a 64-bit long odd number area bank OD (# 1 and # 3) is configured.

As illustrated, the bus width of the address buses G_MA38 to G_MA4 is 35 bits long. Further, each of the even number storage banks EV and the odd number storage banks OD of each storage element MR has a length of 2 ³⁵ × 8 bytes, and the total of two storage elements is 2 ³⁵ × 16 bytes = ²³⁹ bytes. In this circuit configuration, in the address space, the memory element MR is switched every eight addresses in both the even bank EV and the odd bank OD. Then, a series of CG data are stored every 128 bits as 64 bits of the odd bank OD selected by the same address data following 64 bits of the even bank EV selected by the 35-bit address data. There is.

  When sequential CG data are to be accessed sequentially, the 35-bit address data (G_MA38 to G_MA4) are determined, and then the G_CE0 and G_OE0 terminals are asserted to memory 128 bits of the even bank EV. Then, the G_CE1 terminal and the G_OE1 terminal are asserted without changing the address data, and the memory READ of 128 bits of the odd bank OD is performed. Therefore, it is particularly suitable for high speed sequential access to a group of CG data.

  Also in this circuit configuration, the page read method can be adopted by continuously storing a series of CG data in the even storage bank EV and the odd storage bank OD without switching the storage bank. Note that the bit value of G_MA 39 functions as a bank switching signal for CG bus IF unit 82, and at random access, either G_CE0 terminal or G_CE1 terminal is selectively asserted to enable either one of storage banks EV and OD. A memory READ operation can also be performed on a group that includes an arbitrary address.

  As mentioned above, although the ball-and-ball game machine was explained exclusively in each above-mentioned example, it is needless to say that it can be suitably used also in other game machines with image effects, such as a coin-roll game machine.

GM game machine DS1 display 55 storage device

Claims (1)

In a gaming machine capable of performing image effects by displaying a still image and / or a moving image on a display device,
An image of one frame, which is a unit of a predetermined moving image effect, is one frame of a basic image in which the outline of the image is fixed or smoothly changing, and one or more types of effect images in which the outline of the image is irregularly changed . And one frame is duplicated,
The basic image maintaining the specified number of vertical and horizontal pixels corresponding to the image rendering to be performed and the effect image having the number of vertical pixels and / or horizontal pixels smaller than the predetermined number of pixels are each stored in the storage device in a compressed state Has been
At the image display timing, the basic image and the effect image read from the storage device are each decompressed from the compressed state, and the effect image is further subjected to enlargement processing for the number of vertical pixels and / or the number of horizontal pixels. It is configured to be restored to a prescribed number of vertical and horizontal pixels, and to display the image in a state in which the effect image in the restored state and the basic image in the restored state overlap.
The basic image and the effect image are stored in the storage device in a compressed state (B> C) in which the compression ratio (1 / B) of the basic image is higher than the compression ratio (1 / C) of the effect image before enlargement processing. A game machine characterized by having been.