JPH0547190A - Memory card device - Google Patents

Abstract

PURPOSE:To prevent to erase excessively even data unnecessitating to erase by corresponding to new data quantity to rewrite and by erasing the storing content of an EEPROM in pages. CONSTITUTION:By a holding means 14 inputting/outputting the data in bytes and a condition inputting the data of a prescribed byte number constituting a first page to this holding means 14, a discriminating means 13 discriminates whether the data of in bytes constituting continuously a next second page is inputted or not. Then, by the data input/output control circuit 13, in the state of being decided to be inputted by the above-mentioned discriminating means 13, the data constituting a first page held by the holding means 14 is written to the EEPROM 17 and, simultaneously, the storing area of the EEPROM 17 to write the data constituting the second page is erased in pages. Thus, a matter that next page is erased automatically in spite of the data to write is not present is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card device using an EEPROM (Electrically Erasable and Programmable Read Only Memory) as a semiconductor memory, and more particularly to a digital image of an optical image of a photographed subject. The present invention relates to a device suitable for use in an electronic still camera device or the like that converts data and records it in a semiconductor memory.

[0002]

2. Description of the Related Art As is well known, an electronic still which converts an optical image of a photographed object into an electric image signal by using a solid-state image pickup device, converts the image signal into digital image data, and records the digital image data in a semiconductor memory. Camera devices have been developed.
In this type of electronic still camera device, a memory card in which a semiconductor memory is built in a card-shaped case is configured to be detachable from the camera body so that it can be used as a film in a normal camera. Equivalent handling can be done.

The memory card of the electronic still camera device is currently being standardized, and the built-in semiconductor memory is required to have a large storage capacity for recording a plurality of digital image data. For example, SR
AM (Static Random Access Memory),
A mask ROM and an EEPROM capable of electrically writing and erasing data have been considered, and a memory card using an SRAM has already been commercialized.

By the way, the memory card using the SRAM has an advantage that it can correspond to a data structure of any format and has a high data writing speed and a high data reading speed, but holds the written data. Since it is necessary to store a backup battery in the memory card for this purpose, the storage capacity is reduced by the amount of the battery storage space and SR
There is a problem that the cost of AM itself is high and causes an economic disadvantage.

Therefore, in order to solve the problems of the SRAM, the EEPROM is now attracting attention as a semiconductor memory used for a memory card. This EEP
The ROM has been attracting attention as a recording medium that replaces the magnetic disk, and it does not require a backup battery for holding data and can reduce the cost of the chip itself, which is a unique advantage that SRAM does not have. Therefore, development for use as a memory card has been actively carried out.

Here, FIG. 4 shows a comparison between the length of a memory card using SRAM (SRAM card) and the length of a memory card using EEPROM (EEPROM card). First, regarding the backup battery and the cost of the comparison items 1 and 2, the SRAM card needs the backup battery and the cost is high as described above, while the EEPROM card does not need the backup battery and the cost is high. Also has the advantage that it can be lowered.

Regarding the write speed and read speed of comparison items 3 and 4, random access common to SRAM and EEPROM is performed for writing and reading data to or from a byte or bit arbitrarily designated by an address. A mode and a page mode peculiar to the EEPROM, in which data is written and read collectively in page units by designating a page made up of a plurality of consecutive bytes (several hundred bytes), can be considered.

In the random access mode,
The SRAM has a high writing speed and a high reading speed, and the EEPROM has a low writing speed and a low reading speed. In addition, EEPROM
In the page mode, since a large amount of data for one page is written and read all at once, the data write speed and the data read speed are faster than in the random access mode.

Further, the erase (erase) mode of the comparison item 5 is a mode peculiar to the EEPROM, which is the SRAM.
Is a mode that does not exist in. That is, the EEPROM
When writing new data to the area where data has already been written, new data cannot be written unless the previously written data is erased. Therefore, when writing data, this erase mode Is to be executed. The erase mode includes a chip erase that erases all the contents stored in the EEPROM at once and a page erase that erases the contents stored in page units.

Further, the write verify of the comparison item 6 is also a mode peculiar to the EEPROM and is not present in the SRAM. That is, the EEPROM is
When writing data, complete writing is not normally performed in one writing operation. Therefore, EEP
EEP every time one write operation is performed to ROM
It is necessary to read the written contents of the ROM and check whether or not they are correctly written, and this is the write verify.

Specifically, the data to be written in the EEPROM is recorded in the buffer memory, the data is transferred from the buffer memory to the EEPROM and written, and then,
The contents written in the EEPROM are read out and compared with the contents in the buffer memory to determine whether they match. Then, when it is determined as a result of the write verify that there is a mismatch (error), the operation of writing the contents of the buffer memory to the EEPROM again is repeated.

As is clear from the above comparison results, EE
The PROM does not require a backup battery, is low in cost, and is capable of writing and reading data in page units. It has unique advantages not found in SRAM, but on the other hand, it does not store data in the random access mode. There is also a disadvantage that the writing speed and the reading speed are slow and that a mode such as an erase mode and a write verify which is not in the SRAM is required.

Therefore, as the semiconductor memory used for the memory card, the EE is used instead of the currently used SRAM.
Considering the use of PROM, the problems of data write speed and read speed, the problem of needing erase mode and write verify, etc. can be solved, and it can be handled in the same manner as a memory card with built-in SRAM. As described above, that is, it is important to make various improvements in detail so that it can be used in an SRAM card-like manner.

In this case, the EEP is particularly problematic.
In the data rewriting operation for the ROM, first, new data is written to the storage area to be rewritten, and at that time, the next one page of the storage area is automatically page erased. That is, the operation of coping with the writing of data for the next one page is repeated.

For this reason, if one page is composed of 512 bytes, for example, if the input data ends at 300 bytes below that, the next page is not erased, but the input data ends at just 512 bytes. Then, there is a problem that the next page is automatically erased even if there is no data to be written next, and even data that does not have to be erased is additionally erased.

[0016]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
A conventional memory card having a built-in ROM has a problem that even when data is rewritten, data that does not need to be erased is additionally erased.

Therefore, the present invention has been made in consideration of the above circumstances, and the contents stored in the EEPROM can be page erased in accordance with the amount of new data to be rewritten, and the data need not be erased. It is an object of the present invention to provide an extremely good memory card device capable of preventing the inconvenience that the contents are erased excessively.

[0018]

A memory card device according to the present invention is intended for a memory card device provided with an EEPROM for erasing and writing data in page units. Then, the holding means for inputting data in byte units and the next second page are continuously formed in a state where a predetermined number of bytes of data forming the first page are input to the holding means. A discriminating means for discriminating whether or not the data in byte unit is inputted, and in a state where it is judged that the data is inputted by the discriminating means, the data constituting the first page held in the holding means is written in the EEPROM
EEPR to write the data that makes up the second page
A control means for erasing the storage area of the OM in page units is provided.

[0019]

According to the above-mentioned structure, the storage area in which the data forming the second page of the EEPROM is to be immediately written is stored in page units while all the data forming the first page is held in the holding means. In the state where all the data forming the first page is input to the holding means without erasing with, it is determined whether or not the byte unit data forming the next second page is continuously input. Since the storage area of the EEPROM for writing the second page data is erased page by page when it is determined that the data has been input, the EEPROM storage corresponding to the amount of new data to be rewritten. The contents can be page erased, and it is possible to prevent the inconvenience that even data that does not need to be erased is erased excessively.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic still camera device will be described in detail below with reference to the drawings. In FIG. 1, 11 is a memory card main body, which is connected to an electronic still camera main body (not shown) via a connector 12 installed at one end thereof. The connector 12 is provided with digital data DA to be written in the memory card body 11 from the electronic still camera body side and address data AD indicating the writing location.
And are supplied. The digital data DA and the address data AD are supplied to the data input / output control circuit 13 via the bus lines D0 to D7.

Further, from the electronic still camera main body, to the connector 12, a card enable signal CE which becomes H (high) level when the memory card main body 11 is selected.
And an address / data switching signal A / D which becomes L (low) level when the data supplied to the bus lines D0 to D7 is address data AD and becomes H level when the data is digital data DA, and a data write request to an EEPROM described later. The read / write switching signal R / W which becomes L level at the time of and becomes H level at the time of data read request, and the bus clock BCK synchronized with the address data AD
It is being supplied.

These card enable signal CE, address / data switching signal A / D, read / write switching signal R
/ W and the bus clock BCK are also supplied to the data input / output control circuit 13. Further, from the electronic still camera body, a command for requesting data erase to the EEPROM is also supplied to the data input / output control circuit 13 via the connector 12. Further, from the data input / output control circuit 13, when the input of the digital data DA from the electronic still camera main body is permitted, it becomes H level,
Ready / busy switching signal R which becomes L level when input is rejected
DY / BSY is generated.

Here, a schematic operation will be described. The digital data DA supplied to the connector 12 is described.
Under the control of the data input / output control circuit 13, is temporarily stored in the buffer memory 14 and recorded. At this time, the fetch timing of the digital data DA of the buffer memory 14 is controlled by the address data output from the address generation circuit 15. The address generation circuit 15 also counts the clock CK selected by the selector 16 to generate address data for the buffer memory 14. The selector 16 includes the bus clock BCK and the data input / output control circuit 1
The clock YCK output from the circuit 3 is supplied.

Then, when the digital data DA of the buffer memory 14 is fetched, the selector 16 selects the bus clock BCK by the select signal SEL output from the data input / output control circuit 13 and outputs it to the address generation circuit 15 as the clock CK. is doing. Therefore, the digital data DA sent from the electronic still camera body to the connector 12 is stored in the buffer memory 1 according to the address data generated based on the bus clock BCK.
4 will be written.

After that, when the writing of the digital data DA into the buffer memory 14 is completed, the data input / output control circuit 13 controls the select signal SEL so that the clock YCK generated by itself is led to the address generation circuit 15. The selector 16 is switched as follows. Therefore, the buffer memory 1 is generated by the address data generated by the address generation circuit 15 based on the clock YCK.
The digital data DA is read from 4.

At this time, the data input / output control circuit 13 is
Chip enable signal CEN for EEPROM 17
And the write enable signal WE is output, the address data AD is output, and the digital data DA read from the buffer memory 14 is controlled to be written in the EEPROM 17, for example, in 512-byte page units. Then, the digital data DA is stored in the EEPROM 17.
Is written, the data input / output control circuit 13
Out enable data O for the EEPROM 17
E and the address data AD that previously specifies the writing of data are output, the written digital data DA is read from the EEPROM 17, and it is determined whether or not it matches the digital data DA recorded in the buffer memory 14. , Write verify is executed.

If the digital data DA read from the EEPROM 17 and the digital data DA recorded in the buffer memory 14 do not match, the data input / output control circuit 13 again reads from the buffer memory 14 E.
The digital data DA is transferred to and written in the EPROM 17, and this operation is repeated until the digital data DA read from the EEPROM 17 and the digital data DA recorded in the buffer memory 14 completely match. DA EEPROM 17
Is written to.

In addition, from the electronic still camera body to the EEPR
When an instruction to erase the data recorded in the OM 17 is generated, the data input / output control circuit 13 drives the erasing circuit 18 based on the erasing instruction. This erase circuit 18
On the basis of the control of the data input / output control circuit 13,
By outputting a signal for erasing to the address line and data line of the PROM 17, the EEPROM 17 is electrically chip-erased or page-erased.

Next, the operation of reading the digital data DA from the EEPROM 17 to the outside of the memory card body 11 will be described. First, a read request and a recorded address of data to be read are specified from the electronic still camera body side via the connector 12. Then, the data input / output control circuit 13 sends the chip enable signal CEN and the out enable data OE to the EEPROM 17.
Also, the address data AD is output, the digital data DA is read from the EEPROM 17 in page units, and the selector 16 is switched so that the clock YCK generated by itself is derived to the address generation circuit 15 and written in the buffer memory 13.

Thereafter, the data input / output control circuit 13 switches the selector 16 so that the bus clock BCK supplied from the electronic still camera main body side via the connector 12 is led to the address generation circuit 15, and the bus clock BCK. Based on the address data generated by the address generation circuit 15, the data is read from the buffer memory 14 and led out to the electronic still camera body through the connector 12, and the digital data DA is read there.

Therefore, according to the above configuration,
Since the data transfer between the electronic still camera body and the memory card body 11 is always performed via the buffer memory 14, the data writing speed and the data reading speed are improved so that the data can be used in an SRAM card-like manner. Become. Further, since the write verify peculiar to the EEPROM 17 is also carried out by using the buffer memory 14 provided inside the memory card body 11, the memory card body 11 should be used just like an SRAM card. You can

Here, the detailed timing of the writing operation of the digital data DA to the EEPROM 17 is shown in FIG. First, the card enable signal CE is H
When the memory card body 11 is designated as the level,
When the address / data switching signal A / D is at L level, the address data AD is supplied to the bus lines D0 to D7. At this time, the bus clock BC is synchronized with the address data AD.
K is generated and read / write switching signal R /
W is in the L level data write request state, and ready / busy switching signal RDY / BSY is in the H level input enable state.

In such a state, the address / data switching signal A / D is inverted to H level and the bus lines D0 to D7.
When the data of No. changes to digital data DA, D0
512 digital data DA up to D511, that is, one page of digital data DA is input to the data input / output control circuit 13 together with 512 bus clocks BCK and sequentially written in the buffer memory 14. Then, the data input / output control circuit 13, in a state where the digital data DA for one page from D0 to D511 is written in the buffer memory 14,
Wait until the 513th bus clock BCK is generated, and then the D corresponding to the 513th bus clock BCK
It is determined whether or not the 512 digital data DA exists.

The data input / output control circuit 13 outputs 5
When the digital data DA of D512 corresponding to the thirteenth bus clock BCK exists, the digital data DA of D512 is written in the buffer memory 14, and the ready / busy state is synchronized with the 513th bus clock BCK. The switching signal RDY / BSY is inverted to the L level, and the input of the electronic still camera body is rejected. At this time, the data input / output control circuit 13 automatically page erases the storage area for one page of the EEPROM 17 into which the digital data DA for one page after D512 should be written via the erasing circuit 18.

After that, the data input / output control circuit 13 has already erased one page of digital data DA from D0 to D511 among the digital data DA written in the buffer memory 14 to the EEPROM 1 which has already erased the page.
7 is written in the memory area in page units, and the ready / busy switching signal RDY / BSY is set to L during this writing operation.
It is set to the level and the input refusal state is maintained.

When the writing of one page of digital data from the buffer memory 14 to the EEPROM 17 is completed in this way, the data input / output control circuit 13
The ready / busy switching signal RDY / BSY is set to the input permission state of H level, and the digital data DA after D513 is controlled to be written in the buffer memory 14 following the digital data DA of D512 previously written in the buffer memory 14, The same operation is repeated thereafter, and the EEPR
A page write operation for the OM 17 is performed.

Therefore, according to the configuration of the above embodiment, the ready / busy switching signal RDY / BSY is immediately set to the L level while the digital data DA for one page D0 to D511 is written in the buffer memory 14. Then, the EEPROM 17 is not page-erased, and waits until the 513th bus clock BCK which is the 1st page + 1 is generated, and the 513th bus clock B is generated.
It is determined whether or not the digital data DA of D512 corresponding to CK exists, and if there is, the ready / busy switching signal RDY / BSY is set to L level, and the digital data DA for one page after D512 should be written. EEP
Since the storage area of the ROM 17 is page erased, even if the digital data DA to be written in the EEPROM 17 is just 512 bytes, the EEP
The next page of the ROM 17 is not erased automatically and the digital data D need not be erased.
It is possible to prevent the inconvenience that even A is erased excessively.

In this case, one page plus the first 51
As shown in FIG. 3, the ready / busy switching signal RDY is synchronized with the 512th bus clock BCK without determining whether the digital data DA of D512 corresponding to the third bus clock BCK exists. When / BSY is set to L level and the next page of the EEPROM 17 is erased, the digital data D to be written in the EEPROM 17
EEPRO if A ends in just 512 bytes
The next page of M17 is erased automatically,
Even if it is not erased, even the digital data DA will be erased excessively.
The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0039]

As described in detail above, according to the present invention,
EEPRO corresponding to the amount of new data to be rewritten
It is possible to provide a very good memory card device capable of page-erasing the stored contents of M and preventing the inconvenience that even data that does not need to be erased is erased excessively.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a timing chart shown for explaining the effect of the embodiment.

FIG. 4 is a diagram showing the lengths of an SRAM and an EEPROM in comparison.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 ... Data input / output control circuit, 14 ... Buffer memory, 15 ... Address generation circuit, 16 ... Selector, 17 ... EEPROM,
18 ... Erase circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takaaki Suyama 3-3-9 Shimbashi, Minato-ku, Tokyo Inside Toshiba Abu E., Ltd.

Claims (1)

[Claims] 1. In a memory card device having an EEPROM in which data is erased and written in page units, holding means for inputting the data in byte units and a predetermined page constituting the first page in the holding means. In the state where the data of the number of bytes has been input, it is determined that the determination unit determines whether or not the data of the byte unit forming the next second page is continuously input, and the determination unit has input the data. The first portion held by the holding means in the closed state.
Memory card device for writing the data forming the page of the above into the EEPROM and controlling the storage area of the EEPROM for writing the data forming the second page in page units. .