JP2008176606A - Memory controller and flash memory system equipped with memory controller and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently transmit internal information in a flash memory system required from a host system side to a host system side in a flash memory system connected to an ATA interface, and enable the host system to acquire status information longer than the length of a status register from a flash memory with a simple means. <P>SOLUTION: A memory controller writes internal information about a status in the flash memory in a buffer responding to instruction information given from the host system, and when writing of internal information to the buffer is completed, notifies the host system that data which can be transmitted to the buffer is held, and transmits the internal information currently held in the buffer to the host system. The host system can acquire internal information by the same operation as when reading data stored in the flash memory. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed, and is widely used as a storage medium for information devices (host systems) such as digital cameras. As the data handled by such information devices has increased in capacity, the storage capacity of the flash memory has been increased. For this reason, attention has been focused on NAND flash memories that have a high degree of integration and are easy to increase in capacity.

  The NAND flash memory can be performed in units of memory cells when the memory cells are changed from the erased state (logic value = 1) to the written state (logic value = 0). However, when the memory cell is changed from the written state (logic value = 0) to the erased state (logic value = 1), it can be performed only in a predetermined erase unit (block unit) composed of a plurality of memory cells. . Data reading and writing are performed in units of pages, and a block as an erasing unit is composed of a plurality of pages.

  A page of the NAND flash memory corresponds to one or a plurality of sectors in the magnetic disk device. Accordingly, a memory system using a NAND flash memory is often used for a purpose of replacing a conventional magnetic disk device. For this reason, ATA (AT Attachment), which is usually used in magnetic disk devices, is employed as an interface for a memory system using a NAND flash memory.

  As shown in FIG. 7, the ATA-compliant interface (hereinafter referred to as the ATA interface) includes an ATA register 15 such as a command register 15a, a sector count register 15b, an LBA (Logical Block Address) register 15c, a data register 15d, and a status register 15e. It has. By writing to or reading from the ATA register 15, access is made to peripheral devices connected to the ATA interface. Therefore, even in the case of a flash memory system in which the peripheral device uses a flash memory as a storage medium, when accessing the flash memory system from the host system side, the access is made by setting instruction information such as commands and addresses in the ATA register 15. Done.

  For example, when reading or writing is performed from the host system side to the flash memory system, the start address of the sector to be read or written is set in the LBA register 15c from the host system side, and the number of sectors to be read or the sector to be written The number is set in the sector count register 15b, and a read or write command is set in the command register 15a. Based on this setting, in the case of writing, data is written to the flash memory, and in the case of reading, data is read from the flash memory.

  In addition, the host system can know the state of the peripheral device connected to the ATA interface based on information set in the status register 15e. That is, when it is desired to know the state of the peripheral device connected to the ATA interface, information set in the status register 15e (hereinafter referred to as status information) is disclosed in Patent Document 1 below. Read out. Predetermined information is assigned to each bit of the status register 15e. Therefore, the state of the peripheral device can be determined based on the logical value of each bit of the status information read from the status register 15e.

JP 2005-71560 A

  However, only the information assigned to each bit of the status register 15e can be known from the status information read from the status register 15e. Therefore, in the flash memory system connected to the ATA interface, information indicating the internal state such as the number of defective blocks and the number of free blocks in the flash memory (hereinafter referred to as internal information) could not be acquired.

  Therefore, the present invention provides a memory controller suitable for acquiring internal information of the flash memory system connected to the ATA interface from the host system side, a flash memory system including the memory controller, and a flash memory control method. The purpose is to do.

  In order to achieve the above object, a memory controller according to the present invention is a memory controller that controls access to a flash memory in which erasure of stored data is performed in units of physical blocks based on instruction information given from a host system. Data holding means for holding write data to be written to the flash memory or read data read from the flash memory in units of one or more sectors, and data that can be transferred to the data holding means are held for the host system. In the flash memory in response to the instruction information given from the host system, the data transfer means for transferring the data held in the data holding means to the host system Before internal information data on the state of A data setting means for writing to the data holding means, wherein the notifying means stores the read data that can be transferred to the host system when the data holding means is held or when the information setting means sends the data holding means to the data holding means. When the writing of the internal information data is completed, the data holding unit is notified that data that can be transferred is held.

  The internal information is preferably the number of defective blocks and the number of empty blocks in the flash memory.

  In order to achieve the above object, a flash memory system according to the present invention includes any one of the memory controllers and a flash memory.

  In order to achieve the above object, a flash memory control method according to the present invention is a flash memory for controlling access to a flash memory in which erasure of stored data is performed in units of physical blocks based on instruction information given from a host system. In response to the instruction information given from the host system, the internal information data relating to the state in the flash memory, the data to be written to the flash memory, or the data read from the flash memory A data setting step for writing to the data holding means to be held in sector units, and when the writing of the internal information data to the data holding means is completed, there is data that can be transferred to the data holding means to the host system Notifications to notify that they are held And-up, the internal information data held in the data holding means, characterized in that it comprises a data transfer step of transferring to the host system.

  According to the present invention, in the flash memory system connected to the ATA interface, internal information in the flash memory system requested from the host system side can be efficiently transferred to the host system side. Further, the host system can acquire internal information by the same operation as when reading data stored in the flash memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, a flash memory system 1 includes a flash memory 2 that is a NAND flash memory and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data between the register and the memory cell array.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is written or read between the selected memory cell and the register via the word line.

  A memory cell constituting a memory cell array includes a control gate and a floating gate. Data can be written or erased by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Done. Here, the erase state corresponds to the logical value “1”, and the write state corresponds to the logical value “0”.

  FIG. 2 shows the structure of the flash memory 2 which is a NAND flash memory. The flash memory 2 includes “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  The physical block and page configuration differ depending on the specifications of the flash memory, but there are a small block flash memory as shown in FIG. 2 (a) and a large block flash memory as shown in FIG. 2 (b). Commonly used. In the small block configuration, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31), and each page has a 512-byte (one sector) user area 25 and a 16-byte redundant area 26. It consists of In the large block configuration, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page has a user area 25 of 2048 bytes (4 sectors) and a redundancy of 64 bytes. The area 26 is configured.

  Here, the user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for storing additional data such as an error correction code, logical address information, and block status.

  The error correction code is data for detecting and correcting an error included in user data stored in the user area 25.

  The logical address information is information used to specify a logical block corresponding to user data when valid user data is stored in the physical block. The logical block is a collection of a plurality of sectors in the address space on the host system 4 side, and the logical address and flash memory managed by the host system 4 are managed by managing the correspondence between the logical block and the physical block. 2 is managed. The address space on the host system 4 side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). The host system 4 designates an access area in the flash memory 2 with this LBA.

  When valid user data is not stored in the physical block, the logical address information is not written in the redundant area 26 of the physical block. Accordingly, whether or not the physical block is an empty block (erased block) can be determined based on whether or not the logical address information is written in the redundant area 26. That is, if logical address information is not written, it is determined that the block is an empty block (erased block).

  The block status is information indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). Based on this information, the block status is identified. Is done. Therefore, information indicating a defective block is set as a block status in the redundant area 26 of the physical block determined to be a defective block.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and executes operations such as data reading, writing, and erasing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (Error Correcting Code) block 11, a ROM ( Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set (sequence command) defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  The host interface block 7 exchanges data, address information, status information, external commands, and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 and the like is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells. The work area 8 stores, for example, an address conversion table for converting a logical address and a physical address, an empty block search table for searching for an empty block, and the like.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2 in units of one sector or a plurality of sectors. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 is a block that controls writing processing from the buffer 9 to the flash memory 2 and reading processing from the flash memory 2 to the buffer 9. A series of control operations when executing the writing process and the reading process are executed based on a sequence command instructing a series of control operations stored in the ROM 12.

  The ECC block 11 generates an error correcting code (ECC) to be added to data to be written to the flash memory 2, and based on the error correcting code (ECC) added to the data read from the flash memory 2. Then, an error included in the read data is detected and corrected.

  The ROM 12 is a non-volatile storage element that stores a program or the like that defines the procedure of processing executed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  Next, a method for managing the storage area of the flash memory will be described. As the storage capacity of flash memory has been increasing, in order to smoothly manage the storage area of the flash memory whose capacity has been increased, a method of managing this storage area by dividing it into a plurality of zones has been used. Yes.

  FIG. 3 shows an example of managing the storage area of the flash memory 2 by dividing it into a plurality of zones (physical zones). A unique physical block address (PBA) is assigned to each physical block which is an erase unit of stored data. Each physical block is classified into one of a plurality of physical zones, and a physical zone number (PZN) is assigned to each physical zone. A serial number in each physical zone of a physical block included in each physical zone is called an intra-physical zone block number (PZIBN). In the example of FIG. 3, PBA continuous from # 0 is assigned to the physical block, and a total of 1024 physical blocks of PBA # 0 to # 1023 are included in the physical zone of PZN # 0, and PBA # 1024 to A total of 1024 physical blocks of # 2047 are included in the physical zone of PZN # 1, and a total of 1024 physical blocks of PBA # 2048 to # 3071 are included in the physical zone of PZN # 2.

  On the other hand, the address space on the host system 4 side is also divided into a plurality of zones (logical zones), and one physical zone is assigned to one logical zone. Data corresponding to each logical block included in the logical zone is written into a physical block included in the physical zone assigned to the logical zone. Note that the number of logical blocks included in the logical zone is set to be smaller than the number of physical blocks included in the physical zone. For example, a logical zone including 1000 logical blocks is allocated to a physical zone including 1024 physical blocks. In this way, the number of logical blocks included in the logical zone is made smaller than the number of physical blocks included in the physical zone because the number of congenital bad blocks and the number of blocks that are acquired badly are reduced. It is taken into consideration.

  Further, logical address information corresponding to the written data is written in the redundant area of the physical block in which the data is written. Even if this logical address information is a logical block number (LBN) which is a serial number assigned to a logical block, a logical zone block number (LZIBN) which is a serial number within each logical zone of the logical block included in each logical zone. ).

  Next, a procedure for acquiring information (internal information) indicating the internal state of the flash memory 2 from the host system 4 side will be described. In the following description, it is assumed that the number of defective blocks and the number of free blocks for each physical zone as shown in FIG. 4 are acquired as internal information. Hereinafter, the memory controller 3 creates information regarding the number of bad blocks and the number of free blocks for each physical zone, and the information created from the host system 4 side is read (information created on the host system 4 side is transferred). Will be described with reference to FIGS.

  In this embodiment, a command code whose operation is not defined in the ATA standard is assigned to a command for acquiring the number of defective blocks and the number of empty blocks for each physical zone. Such a vendor-specific special command not defined in the ATA standard is called a vendor command. In the following description, a vendor command for acquiring the number of defective blocks and the number of free blocks for each physical zone is referred to as an internal information acquisition command.

  With reference to FIG. 5, creation of internal information and reading of the created internal information from the host system 4 side (transfer to the host system 4 side) in the first embodiment of the present invention will be described. In the first embodiment, first, the host system 4 writes the command code of the internal information acquisition command in the command register (command register 15a of the ATA register 15 shown in FIG. 7) in the memory controller 3. In response to this internal information acquisition command, the memory controller 3 starts creating information on the number of defective blocks and the number of free blocks for each physical zone. In this creation process, the block status and logical address information written in the redundant area of each physical block are read sequentially, and the number of defective blocks and free blocks for each physical zone are counted based on the read block status and logical address information. To do.

  First, the block status and logical address information written in the redundant areas of the physical blocks PBA # 0 to # 1023 are sequentially read, and the number of defective blocks and the number of free blocks in the physical zone of PZN # 0 are counted. Here, regarding the number of defective blocks, the number of physical blocks in which information indicating a defective block is written as a block status is counted. As for the number of free blocks, the number of physical blocks in which no information indicating a bad block is written as the block status and logical address information is not written is counted. When counting of the number of bad blocks and the number of free blocks in the physical zone of PZN # 0 is completed, the number of bad blocks and the number of free blocks in the physical zone of PZN # 0 are written into the buffer 9.

  Next, the block status and logical address information written in the redundant areas of the physical blocks PBA # 1024 to # 2047 are sequentially read, and the number of defective blocks and the number of free blocks in the physical zone of PZN # 1 are counted. When counting of the number of bad blocks and the number of free blocks in the physical zone of PZN # 1 is completed, the number of bad blocks and the number of free blocks in the physical zone of PZN # 1 are written to the buffer 9. In this way, the number of bad blocks and the number of free blocks in the physical zones PZN # 0 to # 7 are counted, and the number of bad blocks and the number of free blocks for each physical zone are written in the buffer 9 as internal information. When counting the number of bad blocks and the number of free blocks for each physical zone, an area for writing the number of bad blocks and the number of free blocks for each physical zone is allocated on the buffer 9, and “0” is set as an initial value in the allocated area. When writing, bad blocks, or empty blocks are detected, the values written in those areas may be increased by one. For example, if a bad block included in the physical zone of PZN # 1 is detected and “3” is written in the area for writing the number of bad blocks in the physical zone of PZN # 1, the value is set to “4”. To "".

  Next, reading from the host system 4 side (transfer to the host system 4 side) of internal information (information regarding the number of defective blocks and the number of empty blocks for each physical zone) written in the buffer 9 will be described.

  When all the internal information is written in the buffer 9, the memory controller 3 notifies the host system 4 to that effect. For this notification, a signal output from the ready / busy (R / B) terminal of the memory controller 3 is used. That is, the level (high level or low level) of the signal output from the ready / busy (R / B) terminal indicates a ready state or a busy state (hereinafter, a signal indicating the ready state is referred to as a ready signal, A signal indicating a busy state is called a busy signal). For example, when the high level is set to the ready state and the low level is set to the busy state, the low level (busy signal) is output from the ready / busy (R / B) terminal until the writing of the internal information to the buffer 9 is completed. When the writing of internal information to the buffer 9 is completed, a high level (ready signal) is output from the ready / busy (R / B) terminal.

  A method for notifying the host system 4 that all internal information has been written to the buffer 9 is a method of outputting an interrupt signal or rewriting the logical value of a specific bit in the status register 15e. It may be.

  When the memory controller 3 notifies the host system 4 that all internal information has been written to the buffer 9, the host system 4 sends high level and low level signals to the read enable (RE) terminal of the memory controller 3. Input alternately. The memory controller 3 stores the internal information written in the buffer 9 at the timing at which the level of the signal input to the read enable (RE) terminal transitions (timing from high level to low level or from low level to high level). Transfer to the data register 15d. Here, the internal information written in the buffer 9 is transferred in units of 1 byte when the number of bits of the data register 15d is 8 bits, and in units of 2 bytes when the number of bits of the data register 15d is 16 bits. On the other hand, the host system 4 alternately inputs a high level signal and a low level signal to a read enable (RE) terminal, and reads information held in the data register 15d.

  In this way, the internal information written in the buffer 9 is transferred to the data register 15 d and read by the host system 4. When all the internal information written in the buffer 9 is stored in the data register 15d, the memory controller 3 outputs a busy signal from the ready / busy (R / B) terminal, and the host system 4 reads the read enable (RE). The input of the signal to the terminal and the reading of the information held in the data register 15d are finished.

  Next, creation of internal information and reading of the created internal information from the host system 4 side (transfer to the host system 4 side) according to the second embodiment of the present invention will be described with reference to FIG. In the case of the second embodiment, instead of starting counting the number of defective blocks and the number of free blocks when an internal information acquisition command is given from the host system 4, an address conversion table and a free block table are created. At the same time, the number of defective blocks and the number of free blocks are counted in parallel, and the number of defective blocks and the number of free blocks for each physical zone are held in the work area 8.

  Thereafter, when an internal information acquisition command is given from the host system 4, the memory controller 3 buffers internal information (information on the number of defective blocks and the number of free blocks for each physical zone) held in the work area 8. 9 is written and a ready signal is output from the ready / busy (R / B) terminal. Thereafter, as in the case of the first embodiment, the internal information written in the buffer 9 is transferred to the data register 15 d and read by the host system 4. When creating the address translation table and the free block table, the number of defective blocks and the number of free blocks are counted in parallel. When creating the address translation table and the free block table, the redundant area of each physical block. This is because the block status and the logical address information written in are read out.

  Here, the address conversion table is a table showing the correspondence between logical blocks and physical blocks, and the free block table is a table showing physical block addresses (PBA) of free blocks. The address conversion table and the empty block table can be created for each logical zone. Therefore, an address conversion table and an empty block table may not be created for a logical zone that has not been accessed. Therefore, in such a case, when an internal information acquisition command is given from the host system 4, the number of defective blocks and the number of free blocks are only obtained for the physical zone corresponding to the logical zone in which the address conversion table and the free block table are not created. Count.

  In this embodiment, since the internal information is held in the work area 8, when the internal information acquisition command is given from the host system 4 as in the first embodiment, the number of defective blocks and the free block There is no need to count the number, and there is an advantage that it can respond quickly to the internal information acquisition command.

  However, in this embodiment, since the number of empty blocks and the number of defective blocks change at any time, it is necessary to update the internal information every time it changes. For example, when user data is written in an empty block, the number of empty blocks in the corresponding physical zone is decremented (decremented by 1), and conversely, the block in which user data has been written is erased to become an empty block. Increments (increases by 1) the number of free blocks in the corresponding physical zone. Similarly, in the case of a defective block, when a new defective block occurs, the number of defective blocks in the corresponding physical zone is incremented (increased by one).

  As described above, according to the present invention, when the memory controller 3 writes internal information to the buffer 9 and all internal information is written to the buffer 9 in response to a command given from the host system 4, the memory controller 3 This is notified to the host system 4. In response to this notification, the host system 4 alternately inputs a high level signal and a low level signal to the read enable (RE) terminal, and reads the information held in the data register 15d. Since the internal information written in the buffer 9 is transferred to the data register 15d at the timing when the signal input to the read enable (RE) terminal transitions, the host system 4 reads the data stored in the flash memory 2. Internal information can be acquired by the same operation as when.

  In the present embodiment, the internal information is the number of defective blocks and the number of empty blocks for each physical zone, but the internal information is not limited to these information. Therefore, the internal information may be information such as a physical block address (PBA) of a bad block.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 is a block diagram schematically showing a flash memory system in an embodiment of the present invention. FIG. It is explanatory drawing which shows the relationship between the block of a flash memory, and a page. It is an example of a storage area of a flash memory that is divided into zones and managed. It is an example of the internal information in the embodiment of the present invention. FIG. 6 is an explanatory diagram for explaining an operation of the memory controller according to the first embodiment of the present invention. It is explanatory drawing for demonstrating operation | movement of the memory controller in the 2nd Embodiment of this invention. It is a figure which shows an ATA register schematically.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External Bus 14 Internal Bus 15 ATA Register 15a Command Register 15b Sector Count Register 15c LBA Register 15d Data Register 15e Status Register 25 User Area 26 Redundant Area

Claims (4)

A memory controller for controlling access to a flash memory in which erasure of stored data is performed in units of physical blocks based on instruction information given from a host system,
Data holding means for holding write data to be written to the flash memory or read data read from the flash memory in units of one or more sectors;
Notification means for notifying the host system that data that can be transferred to the data holding means is held;
Data transfer means for transferring data held in the data holding means to the host system;
In response to the instruction information given from the host system, data setting means for writing internal information data relating to the state in the flash memory to the data holding means,
When the read data that can be transferred to the host system is held in the data holding unit, or when the writing of the internal information data to the data holding unit by the information setting unit is completed, A memory controller that notifies the data holding means that transferable data is held.   2. The memory controller according to claim 1, wherein the internal information is the number of defective blocks and the number of empty blocks in the flash memory.   A flash memory system comprising the memory controller according to claim 1 and a flash memory. A flash memory control method for controlling access to a flash memory in which erasure of stored data is performed in units of physical blocks based on instruction information given from a host system,
In response to instruction information given from the host system, data holding for holding internal information data relating to the state in the flash memory, data to be written to the flash memory, or data read from the flash memory in units of one or more sectors A data setting step for writing to the means;
A notification step of notifying the host system that data that can be transferred to the data holding means is held when the writing of the internal information data to the data holding means is completed;
A data transfer step of transferring the internal information data held in the data holding means to the host system;
A method for controlling a flash memory, comprising:

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