JP4241741B2 - Memory controller and flash memory system - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased. In order to smoothly manage the storage area of the flash memory having such a large capacity, a method of managing the storage area by dividing it into a plurality of zones has been used in recent years (see, for example, Patent Document 1).

  More specifically, the storage area of the conventional flash memory having a plurality of zones is partitioned and managed in the form shown in FIG. 8, for example.

  That is, a specific physical block address (PBA) is assigned to each physical block that is a unit of data erasing and includes a predetermined number of pages that are units of physical data reading and writing. Each physical block is classified into one of a plurality of physical zones, and a unique physical zone number (PZN) is assigned to each physical zone. In the example of FIG. 8, a total of 2048 physical blocks are assigned consecutive PBAs # 0 to # 2047, and a total of 512 physical blocks PBA # 0 to # 511 belong to the physical zone of PZN # 0. , PBA # 512 to # 1023 total 512 physical blocks belong to PZN # 1 physical zone, and PBA # 1024 to # 1535 total 512 physical blocks belong to PZN # 2 physical zone, PBA # 1536 A total of 512 physical blocks of ˜ # 2047 belong to the physical zone of PZN # 3. In other words, conventionally, physical blocks having continuous PBAs are allocated to each physical zone in units of the total number of physical blocks included in the zone.

  Each page is assigned a physical page address (PPA). The PPA has a form in which a page number (PN), which is a serial number of the page in the physical block, is added to the lower level of the PBA of the physical block to which the page belongs.

  On the other hand, the address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. The serial number assigned to the logical block is called a logical block number (LBN), and the serial number assigned to the logical zone is called a logical zone number (LZN). Further, the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, LZIBN (or LBN) of the logical block corresponding to the data is written in the redundant area of the physical block in which the data is written.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. This address conversion table can be created for each logical zone. That is, since the correspondence between the logical zone and the physical zone is set in advance, the address conversion table can be created by referring to the LZIBN written in the redundant area of the physical block in which the data is written. .

  Here, even if the information (hereinafter referred to as logical address information) specifying the logical block to be written in the redundant area is LBN, an address conversion table can be created, but generally LZIBN with a small amount of data is used. Is written in the redundant area as logical address information.

  Normally, a plurality of sectors with consecutive LBAs are assigned to each logical zone. In the example of FIG. 8, LBA # 0 to # 15999 sectors are in the LZN # 0 logical zone, LBA # 16000 to # 31999 sectors are in the LZN # 1 logical zone, and LBA # 32000 is in the LZN # 2 logical zone. ... To # 47999, and LBA # 48000 to # 63999 are assigned to the logical zone of LZN # 3, respectively. In this example, one page of the flash memory corresponds to one sector, and each physical block is composed of 32 pages.

The 16000 sectors assigned to each logical zone are managed as logical blocks in units of 32 sectors in which LBAs are continuous in the logical zone. Therefore, in other words, 32 sectors with consecutive LBAs are assigned as logical blocks, and 500 logical blocks with consecutive LBNs (LZIBN # 0 to # 499) are assigned to each logical zone. Here, the number of sectors included in the logical block is set as appropriate so that the capacities of one logical block and one or a plurality of physical blocks coincide. Since each page of physical blocks stores data in LBA order, it is based on the correspondence between the logical blocks included in each logical zone and the physical blocks included in the physical zone corresponding to the logical zone. The access destination in the flash memory can be specified.
JP 2005-18490 A

  However, if physical blocks with continuous PBA in the flash memory are allocated to each physical zone in units of all, when bad blocks are concentrated in a specific area, it is required in the physical zone to which the area is allocated. The required number of good blocks could not be secured.

  The present invention has been made in view of the above circumstances, and a memory controller capable of avoiding the concentration of defective blocks in a specific physical zone even when the defective blocks are concentrated in a specific area, and a flash memory including the memory controller The purpose is to provide a system.

In order to achieve the above object, the memory controller of the present invention provides:
A memory controller that controls access to a flash memory in which stored data is erased in units of physical blocks in response to a command from a host system,
By distributing the physical blocks in the flash memory one by one in the order of the physical block addresses of the physical blocks to the power zone of 2 physical zones , the physical zone including a plurality of physical blocks is raised to a power of 2 A physical zone forming means to form;
Logical zone forming means for forming a logical zone in which a plurality of logical blocks including a plurality of sector areas having continuous logical addresses in the address space on the host system side is formed, the same number as the number of the physical zones;
The correspondence between the physical zone and the logical zone is the correspondence between the physical zone number that is a serial number starting from 0 assigned to the physical zone and the logical zone number that is a serial number starting from 0 attached to the logical zone. and zone management means to manage by,
Between the logical zone and the physical zone that correspond to each other, the correspondence between the logical address in the logical zone and the physical address in the physical zone is attached to the physical block in the physical zone. An address management means for managing by a correspondence relationship between a physical zone block number starting from 0 and a logical zone block number starting from 0 assigned to a logical block in the logical zone ;
Access means for accessing the flash memory in response to an instruction given from the host system ,
The access means specifies the physical zone number of the physical zone to which the physical block to be accessed belongs based on the correspondence between the physical zone number and the logical zone number, and the physical zone block number and the logical zone The physical zone block number of the physical block to be accessed is identified based on the correspondence relationship with the internal block number, and the identified physical zone number and the intra-physical zone block number are set to the lower side. To obtain the physical block address of the physical block to be accessed by concatenating in binary notation,
It is characterized by that.

  A flash memory system according to the present invention includes the memory controller described above and a flash memory.

  According to the present invention, when defective blocks are concentrated in a specific area in the flash memory, a memory controller capable of avoiding the concentration of these defective blocks in a specific physical zone, and a flash memory system including the memory controller Can be realized. That is, when defective blocks are concentrated in a specific area due to an initial defect or the like, these defective blocks can be distributed to a plurality of physical zones.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory shown in FIG. 2, one page is composed of a user area 25 of 1 sector (512 bytes) and a redundant area 26 of 16 bytes, and one physical block is composed of 32 pages. . There is a flash memory in which one page is composed of a 4-sector user area and a 64-byte redundant area, and one physical block is composed of 64 pages. The user area 25 stores user data supplied from the host system 4.

  The redundant area 26 is an area for recording additional data such as an error collection code, logical address information, and a block status (flag).

  The error collection code is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when no logical address information is stored in the redundant area 26, no valid data is stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the physical block including the page must be rewritten.

  That is, in normal data rewriting, data stored in all pages of a physical block including a page to be rewritten is written to another erased physical block. At this time, as for the data stored in the page where the data is not changed, the previously stored data is rewritten as it is.

  In rewriting data as described above, the rewritten data is usually written in a physical block different from the physical block stored previously. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on logical address information (LZIBN or LBN) stored in the redundant area 26 of each physical block. Note that such a dynamic address management method is a method generally used in a memory system using a flash memory as described above.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  As shown in FIG. 3, the host interface block 7 includes a command register R1, a sector number register R2, and an LBA register R3, and exchanges data, address information, status information, external commands, etc. with the host system 4. To do. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells. In the work area 8, for example, an address conversion table for converting a logical address and a physical address, an empty block table for registering an empty block, and the like are stored.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address processing unit, a command register, an instruction processing block, and the like. As shown in FIG. 3, the address processing unit includes a physical block address register R11, a page number register R12, a counter R13, and a command register R21.

  The physical block address register R11 stores the physical block address PBA of the physical block to be accessed in the flash memory 2. The physical block address PBA set in the physical block address register R11 is determined based on an address conversion table created in the work area 8. This address conversion table is formed for each pair of corresponding logical zone and physical zone, and stores the correspondence between the logical block number LZIBN in the logical zone and the physical block number PZIBN in the physical zone.

The page number register R12 stores the page number PN of the page to be accessed. The counter R13 counts the remaining amount of pages to be accessed in each physical block.
The command register R21 is set with a sequence command for instructing processing to be executed by the flash memory interface block 10.

  The instruction processing block outputs an internal command, a physical address, and the like for controlling the flash memory 2 according to the sequence command stored in the command register R21.

  The flash memory interface block 10 supplies the flash memory 2 with internal commands, address information, and the like output from the instruction processing block, thereby causing the flash memory 2 to execute reading and writing.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

Next, allocation of physical blocks to a plurality of physical zones will be described.
In order to facilitate understanding, in the following description, the number of physical blocks in the flash memory 2 is assumed to be 2048, and the number of physical zones to which these physical blocks are allocated is assumed to be four.

  Here, the physical block addresses PBA of 2048 physical blocks can be expressed in binary with 11 bits, as shown in FIG.

  Conventionally, 512 physical blocks each having a continuous PBA in the flash memory are allocated to 4 physical zones. Therefore, the most significant 2 bits of the PBA indicate the physical zone, and the lower 9 bits indicate the block number PZIBN in the physical zone that is the serial number of the physical block in any of the physical zones.

  On the other hand, in the present embodiment, the physical blocks in the flash memory 2 are sequentially allocated to four physical zones by a predetermined number in the PBA order. For example, as shown in FIG. 5, four physical blocks in the flash memory 2 are allocated to the physical zones of PZN # 0 to # 3. Here, when the predetermined number of physical block allocation units and the number of physical zones of the allocation destination are powers of 2, the physical zone number PZN of the allocation destination physical zone is set based on the bits in the specific range of the PBA. Can be determined.

  That is, as shown in FIG. 5, when four physical blocks are allocated to four physical zones, as shown in FIG. 4A, the lower 4th bit and 3 bits of the 11-bit PBA are used. The second 2 bits indicate the physical zone number (PZN: # 0 to 3), and 9 bits excluding these 2 bits indicate the physical zone block number (PZIBN: # 0 to 511).

  FIG. 4B shows the physical zone numbers PZN # 0-3 at this time, the physical block address PBA of the physical block arranged in each physical zone, and the binary notation thereof. As shown here, the 2nd bit of the 4th and 3rd bits from the PBA of the physical block allocated to the physical zone of PZN # 0 is “00”, and the physical zone of PZN # 1 The 2nd bit of the 4th and 3rd bits from the lower PBA of the allocated physical block is “01”, and the 4th and 3rd bits of the lower PBA of the physical block allocated to the physical zone of PZN # 2 The second two bits are “10”, and the second and third bits from the lower PBA of the physical block allocated to the physical zone of PZN # 3 are “11”. Also, the remaining 9 bits except the 2nd bit of the 4th bit and the 3rd bit from the lower order of the 11-bit PBA correspond to PZIBN # 0-511. For example, PBA # 33 (binary notation: 000 0010 0001), which is a physical block allocated to the physical zone of PZN # 0, corresponds to PZIBN # 9 (binary notation: 0 0000 1001).

  Next, reading processing from the flash memory 2 will be described.

  The read process is executed based on the number of sectors set in the sector number register R2 of the host interface block 7, the leading value of the LBA set in the LBA register R3, and the external command set in the command register R1. This read process is started when an external command that instructs the read process is set in the command register R1.

  First, the microprocessor 6 sets the logical zone number LZN and the logical zone block number LZIBN of the access target area based on the head LBA stored in the LBA register R3 and the number of sectors to be accessed set in the sector number register R2. Obtained in units of logical blocks. That is, when the access target area extends over a plurality of logical blocks, a plurality of sets of LZN and LZIBN are obtained.

  Next, the physical block address PBA of the physical block for the logical block is obtained based on the logical zone number LZN and the intra-logical zone block number LZIBN thus obtained. When obtaining this PBA, an address conversion table showing the correspondence between the logical block included in the logical zone to be accessed and the physical block included in the physical zone corresponding to this logical zone is referred to. For example, when the logical zone of LZN # 0 corresponds to the physical zone of PZN # 0, the correspondence relationship between LZIBN of the logical block included in the logical zone of LZN # 0 and PZIBN of the physical block included in the physical zone of PZN # 0 Is created, and PZIBN of the physical block to be accessed is obtained by referring to this address translation table.

  Furthermore, PBA can be obtained by adding a bit indicating PZN to the obtained PZIBN. For example, if the physical block to be accessed is a PZIBN # 6 (binary notation: 0 0000 0110) physical block of PZN # 0 (binary notation: 00), the PBA of this physical block is PZIBN # 6 (binary notation). It is obtained by adding 2 bits indicating PZN # 0 (binary notation: 00) between the second and third bits from the lower order of the notation: 0 0000 0110). That is, the PBA of the physical block of PZIBN # 6 (binary notation: 0 0000 0110) of PZN # 0 (binary notation: 00) is # 18 (binary notation: 000 0001 0010).

Note that the number of bits indicating PZN is determined by the number of physical zones to which distribution is performed,
The position of the bit indicating PZN in the PBA is determined by a predetermined number of physical block allocation units. That is, if the number of physical zone assignment destination is 2 ^j-number, the number of bits bits indicating PZN becomes j bits. Furthermore, the number is 2 ^j-number of physical zone assignment destination, if a predetermined number of distribution units of the physical blocks of 2 ^k pieces, k + 1 bit from the k + j th bit counted from the lower PBA becomes bit indicating PZN .

For example, if in a case where the number of physical zone assignment destination is four (2 ²⁾ and 8 (2 ^3), the position of the bits indicating the PZN in the PBA sorting units of physical blocks as follows predetermined It depends on the number.

<When the number of distribution-destination physical zones is four>
Predetermined number of distribution units is one: 2nd to 1st bit distribution units counted from the lower order of the PBA: 2nd predetermined number of distribution units counted from the lower order of the PBA is the predetermined number of 3rd to 2nd distribution units 4 pieces: The predetermined number of 4th to 3rd bit allocation units counted from the lower order of PBA is 8: 5th to 4th bits counted from the lower order of PBA

<When the number of distribution-destination physical zones is 8>
Predetermined number of distribution units is one: the number of 3rd to 1st bit distribution units counted from the lower part of the PBA is two: the predetermined number of fourth to second bit distribution units is counted from the lower part of the PBA 4 units: The predetermined number of 5th to 3rd bit allocation units counted from the lower order of PBA is 8: 6th to 4th bits counted from the lower order of PBA

In addition, when obtaining PBA from PZIBN, the position at which a bit indicating PZN is added to PZIBN also varies depending on the predetermined number of physical block allocation units.
Predetermined number of distribution units is one: the lowest number of additional distribution units on the lowest side of PZIBN: four predetermined numbers of additional distribution units between the second and first bits from the lower order of PZIBN: PZIBN The number of additional allocation units is 8 between the 3rd and 2nd bits from the lower order: Add between the 4th and 3rd bits from the lower order of PZIBN

The address conversion table can be created by referring to logical address information (for example, LZIBN) written in the redundant area 26 of the physical block. In this address conversion table creation process, a table area for writing the PZIBN of the physical block corresponding to each LZIBN of the logical block included in the logical zone to be created is secured in the work area 8. Subsequently, PZIBN is written in the table area with reference to the redundant area 26 of the physical block included in the physical zone corresponding to the logical zone to be created. For example, when LZIBN # 8 is written in the redundant area 26 of the physical block of PZIBN # 10 in PZN # 0, PZIBN # 10 is written in a location corresponding to LZIBN # 8 in the table area.

  Next, the microprocessor 6 sets the physical block address PBA of the physical block to be read in the physical block address register R11 of the flash memory interface block 10, and the page number register R12 of the page to start reading in the physical block. A page number is set, the number of pages to be read is set in the counter R13, and a sequence command for instructing data reading is set in the command register R21. Here, the page number of the page from which reading is started corresponds to the lower bits remaining after the bit indicating the logical block number LBN is excluded from the LBA from which reading starts. When the access target area extends over a plurality of logical blocks, the above settings are performed in order from the younger LBN.

  Subsequently, the instruction processing block of the flash memory interface block 10 outputs an internal command for controlling the flash memory 2, address information, and the like according to the sequence command stored in the command register R 21, and stores data from the flash memory 2. The read data is stored in the buffer 9. Here, the internal command given to the flash memory 2 is an internal command for instructing reading. The address information given to the flash memory 2 is generated by adding the page number PN set in the page number register R12 to the PBA set in the physical block address register R11. Further, every time data for one page (one sector) is read from the flash memory 2, the set value set in the page number register R12 is incremented (added by 1), and the set value set in the counter R13 is set. Is decremented (subtracted by 1), and the next address information is generated based on the incremented setting value of the page number register R12. The data stored in the buffer 9 is provided to the host system 4 via the host interface block 7 and the external bus 13.

  The reading process based on the information set in the physical block address register R11, page number register R12, counter R13, and command register R21 ends when the set value set in the counter R13 becomes “0”. That is, in this reading process, data corresponding to the number of pages (sector number) initially set in the counter R13 is read in order from the page (sector) corresponding to the setting value initially set in the page number register R12. .

  Next, the writing process to the flash memory 2 will be described. In the case of the write process, when an external command instructing the write process is set in the command register R1, the write process is started and the number of sectors set in the sector number register R2 of the host interface block 7 is set in the LBA register R3. The process is executed based on the set leading value of the LBA.

  When the write process is executed, the logical zone number LZN to be accessed and the block number LZIBN in the logical zone are obtained in the same procedure as in the above read process, and the PBA of the physical block to be accessed is also It is obtained in the same procedure as in the reading process. In the case of rewriting old data, an empty block is detected, and a bit indicating the PZN of the physical zone to which the empty block belongs is added to the PZIBN of the empty block, thereby obtaining the PBA of the empty block.

  Subsequently, the PBA of the write-destination physical block is set in the physical block address register R11 of the flash memory interface block 10, the page number of the page to start writing is set in the page number register R12, and the counter R13 is set in the counter R13. The number of pages to which data is written is set, and a sequence command for instructing data writing is set in the command register R21.

  The instruction processing block of the flash memory interface block 10 outputs an internal command for controlling the flash memory 2, address information, and the like according to a sequence command stored in the command register R21. Further, data sequentially supplied from the host system 4 and held in the buffer 9 is supplied to the flash memory 2. The supplied data is written in the user area 25 of the flash memory 2, and the logical block LZIBN corresponding to the data written in the user area 25 is written in the redundant area 26. Further, in the address conversion table indicating the correspondence between LZIBN and PZIBN, the portion where the correspondence has changed is updated.

  In the example shown in FIGS. 4 and 5, the number of physical zones as the allocation destination is four and the predetermined number of physical block allocation units is four. The predetermined number of distribution units can be set as appropriate.

  For example, when the number of distribution-destination physical zones is 16 and the predetermined number of physical block distribution units is 1, the physical blocks of PZN # 0 to # 15 are one by one as shown in FIG. Sorted sequentially into zones. Further, when the number of physical blocks included in each physical zone is 1024, the P384 of 16384 physical blocks allocated to the 16 physical zones is 2 in 14 bits as shown in FIG. Can be expressed in decimal. Of the 14-bit PBA, the lower 4 bits indicate the PZN of the physical zone that is the distribution destination, and the upper 10 bits indicate the PZIBN of the physical block included in each physical zone.

  In other words, the physical block whose lower 4 bits of PBA are “0000” is allocated to the physical zone of PZN # 0, and the physical block whose lower 4 bits of PBA is “0001” is allocated to the physical zone of PZN # 1, The physical block whose lower 4 bits are “0010” is allocated to the physical zone of PZN # 2, the physical block whose lower 4 bits of PBA is “0011” is allocated to the physical zone of PZN # 3, and the lower 4 bits of PBA are The physical block of “0100” is allocated to the physical zone of PZN # 4, and is similarly allocated based on the value of the lower 4 bits of PBA. The physical block whose lower 4 bits of PBA is “1111” is allocated to PZN # 4. Sorted into 15 physical zones.

  Further, the PBA of the physical block included in each physical zone can be obtained by adding the PZN of the physical zone to which the physical block belongs to the lower level of the PZIBN of the physical block. FIG. 6B shows the correspondence between PZIBN and PBA of the physical block allocated to the physical zone of PZN # 0. As can be seen from the PBA in binary notation, the PBA corresponding to each PZIBN can be obtained by adding 4 bits “0000” indicating PZN # 0 to the lower order of PZIBN. For example, PBA # 176 (binary notation: 00 0000 1011 0000) corresponding to PZIBN # 11 of PZN # 0 is 4 bits indicating PZN # 0 below PZIBN # 11 (binary notation: 00 0000 1011). It can be obtained by adding 0000 ″.

  As described above, in the flash memory system 1 according to the present embodiment, since a predetermined number of physical blocks are sequentially allocated to each physical zone, a plurality of defective blocks (for example, initial defective ones) with consecutive PBAs are allocated. When there are physical blocks), it is less likely that these bad blocks are included in a specific physical zone. For example, if there are 8 defective blocks with consecutive PBAs when allocating physical blocks in the flash memory 2 to 8 physical zones, if the predetermined number of physical block allocation units is 4, these defects will occur. Blocks are allocated to at least two physical zones, and if the predetermined number of physical block allocation units is two, these bad blocks are allocated to at least four physical zones, and the predetermined number of physical block allocation units is If there is one, these bad blocks are distributed to eight physical zones. That is, if the predetermined number of physical block allocation units is reduced, a plurality of defective blocks having consecutive PBAs can be allocated to more physical zones.

1 is a block diagram schematically showing a flash memory system according to an embodiment of the present invention. It is a figure which shows roughly the structure of the address space of the flash memory of embodiment of this invention. It is a block diagram which shows the structure of a host interface block and a flash memory interface block. (A) is a figure which shows an example of the data structure of PBA, (b) is a figure which shows the example of allocation of the physical block to each physical zone. FIG. 5 is a diagram showing an example of physical block allocation to each physical zone in the case of the PBA data structure of FIG. (A) is a figure which shows another example of the data structure of PBA, (b) is a figure which shows the example of allocation of the physical block to each physical zone. FIG. 7 is a diagram illustrating an example of physical block allocation to each physical zone in the case of the PBA data structure of FIG. It is a figure which shows roughly the structure of the address space of the conventional flash memory.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 15 Internal clock source 25 User area 26 Redundant area

Claims (2)

A memory controller that controls access to a flash memory in which stored data is erased in units of physical blocks in response to a command from a host system,
By distributing the physical blocks in the flash memory one by one in the order of the physical block addresses of the physical blocks to the power zone of 2 physical zones , the physical zone including a plurality of physical blocks is raised to a power of 2 A physical zone forming means to form;
Logical zone forming means for forming a logical zone in which a plurality of logical blocks including a plurality of sector areas having continuous logical addresses in the address space on the host system side is formed, the same number as the number of the physical zones;
The correspondence between the physical zone and the logical zone is the correspondence between the physical zone number that is a serial number starting from 0 assigned to the physical zone and the logical zone number that is a serial number starting from 0 attached to the logical zone. and zone management means to manage by,
Between the logical zone and the physical zone that correspond to each other, the correspondence between the logical address in the logical zone and the physical address in the physical zone is attached to the physical block in the physical zone. An address management means for managing by a correspondence relationship between a physical zone block number starting from 0 and a logical zone block number starting from 0 assigned to a logical block in the logical zone ;
Access means for accessing the flash memory in response to an instruction given from the host system ,
The access means specifies the physical zone number of the physical zone to which the physical block to be accessed belongs based on the correspondence between the physical zone number and the logical zone number, and the physical zone block number and the logical zone The physical zone block number of the physical block to be accessed is identified based on the correspondence relationship with the internal block number, and the identified physical zone number and the intra-physical zone block number are set to the lower side. To obtain the physical block address of the physical block to be accessed by concatenating in binary notation,
A memory controller characterized by that. The memory controller according to claim 1 and a flash memory.
A flash memory system characterized by that.

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