JP4177292B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems in the form of memory cards, silicon disks, and the like. Data stored in the flash memory is required to be retained even when power is not supplied.

The NAND flash memory is a flash memory that is particularly frequently used in the above memory system.
Each of the plurality of memory cells included in the NAND flash memory indicates a logical value “1” when in an erased state and indicates “0” when in a written state. The plurality of memory cells can change from the erased state to the written state independently of other memory cells.

  In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This collective erasure operation is generally called “block erase”. Write processing or read processing for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

In the NAND flash memory, the erase process is performed in units of blocks as described above. Therefore, the correspondence between the addresses given from the host system side and the addresses in the flash memory is usually managed in units of blocks. For example, in Patent Document 1 below, a logical block address based on an address given from the host system side and a physical block address that is a block address in the flash memory are converted in units of blocks.
JP 2003-76605 A

  In the writing process to the flash memory, data is normally written in each page constituting a block (physical block) in the flash memory in the order of addresses given from the host system side. That is, data in the order of addresses given from the host system side is sequentially written from the first page of the physical block. Accordingly, when a group of data written by a write process based on a write command given from the host system is all written in one physical block, the address conversion from the logical block address to the physical block address is performed. If this is done at the start of addressing, there is no need to perform address translation during the writing process.

  When writing to the flash memory is performed efficiently at high speed, data for one block may be written from the first page of the physical block.

  However, when a write command for writing data for one block is given from the host system side to the flash memory system, high-speed writing can be performed if the write start page is the first page of the physical block. However, if the write start page is not the first page of the physical block, address conversion must be performed in the middle of the write process, and high speed writing cannot be supported. However, it is difficult for the host system side to determine whether or not the flash memory system can handle high-speed writing.

  The present invention has been made in view of such a conventional problem, and a memory controller which determines whether or not the flash memory system side can cope with high-speed writing and can access the information from the host system side. An object of the present invention is to provide a flash memory system and a flash memory control method.

To achieve the above object, a memory controller according to a first aspect of the present invention has a storage area, and data in the storage area is erased in units of physical blocks including a plurality of pages. A memory controller that is connected to a flash memory capable of writing data in units of pages in the erased portion of the memory and a host system, and that controls access of the host system to the flash memory, from the host system, For a write data given together with a logical block address indicating a logical block to which the data belongs, a physical block address indicating a physical block to which the write data is written is set, and the write data is a position corresponding to the physical block address. Write means for writing to the host system, and a write command given from the host system. Ku write start page of the user data set is determined whether the appropriate information display means for indicating the result as determination information,
It is characterized by providing.

The information display means may be configured such that when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the physical block, the write start page of the user data group is appropriate. You may judge that there is.

  Further, the physical block is composed of a plurality of sub-blocks, and the information display means is configured such that a write start page of the user data group based on a write command given from the host system corresponds to the first page of the sub-block. In addition, it may be determined that the write start page of the user data group is appropriate.

  In order to achieve the above object, a flash memory system according to a second aspect of the present invention comprises a flash memory for storing data, and a memory controller according to the first aspect of the present invention. To do.

To achieve the above object, a flash memory control method according to a third aspect of the present invention has a storage area, and data in the storage area is erased in units of physical blocks composed of a plurality of pages. with respect to the flash memory writing that can data for each page in the erased part of the data, a control method for controlling access of host systems to said flash memory, from the host system, the data For the write data given together with the logical block address indicating the logical block to which it belongs, a physical block address indicating the physical block to which the write data is written is set, and the write data is set at a position corresponding to the physical block address. A user data group write start page based on a write process and a write command given from the host system. Di is determined whether it is appropriate, and performs the information display process shown the result as determination information.

In the information display process, when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the physical block, the write start page of the user data group is appropriate. You may judge that.

  Also, the physical block is composed of a plurality of sub-blocks, and in the information display processing, the write start page of the user data group based on the write command given from the host system corresponds to the first page of the sub-block. In addition, it may be determined that the write start page of the user data group is appropriate.

  According to the present invention, it becomes possible for the flash memory system side to determine whether or not high-speed writing is possible, and to access the information from the host system side.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to an embodiment of the present invention.

  As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is used by being detachably attached to the host system 20 and used as a kind of external storage device of the host system 20.

  Examples of the host system 20 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block includes 32 pages, and one page includes a 512-byte user area and a 16-byte redundant area. It consists of and.

  The memory controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, an internal interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12.

The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.
The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the memory controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 20. That is, when the flash memory system 1 is attached to the host system 20, the flash memory system 1 and the host system 20 are connected to each other via an external bus, and in this state, the host system 20 supplies the flash memory system 1 to the flash memory system 1. The data to be supplied is taken into the memory controller 3 using the host interface block 7 as an entrance, and the data supplied from the flash memory system 1 to the host system 20 is supplied to the host system 20 using the host interface block 7 as an exit. Is done.

  The host interface block 7 further includes a task file register (not shown) that temporarily holds a host address and an external command supplied from the host system 20 and an error register (not shown) that is set when an error occurs. ) Etc.

The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.
The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 20 is ready to receive data, and data to be written to the flash memory 2 is held in the buffer 9 until the flash memory 2 is ready to write. .

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the memory controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 20 to the flash memory system 1.

  The internal interface block 10 is a functional block that exchanges data, address information, and the like with the flash memory 2 via a bus.

  The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.

[Description of flash memory]
The NAND flash memory in which data is stored in the flash memory system 1 is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data is written. A process of erasing a block in which (data before rewriting) has been written is performed. When rewriting such data, the data after rewriting is written in a different block from before rewriting, so the logical block address based on the address given from the host system side and the block in the flash memory The correspondence with the physical block address, which is an address, dynamically changes every time data is rewritten. The correspondence between the logical block address and the physical block address is normally managed by an address conversion table indicating the correspondence.

  The configuration of the block and page differs depending on the specification of the flash memory. However, in a general flash memory, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31). Is composed of a user area of 512 bytes and a redundant area of 16 bytes. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.

  Here, the user area is mainly an area for storing data supplied from the host system, and the redundant area is for storing additional data such as an error correction code, a corresponding logical block address and a block status. It is an area. The error correction code is additional data for detecting and correcting an error included in data stored in the user area, and is generated by an external ECC block.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. It can also be judged. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block. The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  Next, a circuit configuration of the NAND flash memory will be described. A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from the register to the memory cell or copying from the memory cell to the register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate and the lower gate is called a floating gate. Data is written by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Or data is deleted.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When electrons are injected into the floating gate, a high voltage is applied so that the control gate is on the high potential side. When electrons are injected from the floating gate, electrons are injected on the floating gate. A voltage is applied to discharge electrons. Here, the state in which electrons are injected into the floating gate (write state) corresponds to the data of the logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) is the logical value. Corresponds to the data of “1”.

[Description of access to flash memory]
A case where access to the flash memory 2 is controlled will be described.
A logical block address based on address information given from the host system 20 side is converted into a physical block address which is a block address in the flash memory 2, and the flash memory 2 is accessed based on the obtained physical block address. At this time, the conversion from the logical block address to the physical block address uses an address conversion table.

  The address conversion table is a table showing the correspondence between logical block addresses and physical block addresses, and is created and saved on the work area 8 shown in FIG.

  In the write process, the host system 20 gives a write command including a write destination head address and the number of pages (number of sectors) of data to be written to the flash memory system 1. From the host system 20, a group of data (user data) to be written to the flash memory 2 is given together with this write command. For example, when the number of pages of data to be written by a write command is designated as 32 pages, a user data group for 32 pages is given from the host system 20. At this time, the user data group for 32 pages is sequentially supplied in the order of addresses in the address space on the host system 20 side (hereinafter, the order of addresses in the address space on the host system 20 side is referred to as logical address order). .

  The address given from the host system 20 includes a logical block address portion and a page portion indicating a page in the logical block. For example, in the writing process to the flash memory 2 in which one block is composed of 32 pages, the lower 5 bits of the binary address correspond to the page portion, and the upper bits excluding this page portion are the logical block address portion. Corresponding to The microprocessor 6 extracts a logical block address portion from the address given from the host system 20 via the host interface block 7. In the case of write processing, a physical block address that has been erased is appropriately assigned to this logical block address, and data is written in the order of logical addresses on pages in the physical block designated based on this physical block address. In the read process, the logical block address is converted into a physical block address with reference to the address conversion table, and data of each page in the physical block designated based on the physical block address is read out.

  In the given write command or read command from the host system 20, a command including the write destination or the start address of the read destination and the number of pages to be written or the number of pages of data to be read (the number of sectors) is given to the flash memory system 1. The microprocessor 6 generates a write address or a read address by adding a page portion which is a serial number indicating a page in the physical block to the physical block address of the physical block to be written or read. For example, in the writing process in which data for 32 pages is written in order from the first page of the physical block, page portions 0 to 31 are sequentially added to the physical block address of the writing destination.

  When the first page of data is transmitted to the flash memory 2, a write address with 0 added to the physical block address is given, and when the next page of data is transmitted , A write address obtained by adding 1 to the physical block address is given. Thereafter, write addresses are sequentially given, and a write address obtained by adding 31 to the physical block address is given when data for the last page is transmitted. Each of the 32 pages of data is sequentially written to the page designated by the write address.

FIG. 3 is an explanatory diagram showing the relationship between the system data area and the user data area in the storage area of the flash memory 2.
The user data area is an area in which write data given from the host system 20 is stored, and the system data area is an area in which information for managing user data written in the user data area is stored. The user data group (data 0 to 3) stored in the user data area is a unit of data continuously written based on a write command given from the host system. For example, a page of data written by the write command When the number is designated as 32 pages, each user data group (data 0 to 3) corresponds to 32 pages of data. Therefore, if each physical block is composed of 32 pages and the data of each user data group (data 0 to 3) is written from the first page of each physical block, each user data group (data 0 to 3) is written. ) Are written in one physical block. Therefore, it is preferable that the start position of the user area in the storage area of the flash memory 2 starts from the first page of the physical block.

  In the example shown in FIG. 3, the system data is written in the physical block 0 and the physical block 1 of the flash memory 2. Each user data group indicated by data 0 to 3 is written to physical block 2 to physical block 6 in the user data area of the flash memory 2. That is, in this state, the user data area of the flash memory 2 is started from the first page of the physical block, and each user data group (data 0 to 3) is written from the first page of the physical block. In this state, high-speed writing can be performed by sequentially writing user data groups, which are data for 32 pages.

  Further, in order to be able to know from the host system side that such an optimum state in which high-speed writing is possible is possible (for example, in the flash memory 2 or in the memory controller). 3), information indicating whether or not the state is optimum, that is, whether or not high-speed writing can be supported is set.

  For example, when the user data area is initialized to start from the first page of the physical block, information indicating that the user data area is in the optimum state is set, and when the non-optimal state described later is detected, the setting information is set. The information may be changed to indicate that the state is not optimal. Note that the physical block addresses of the physical block 2 to the physical block 5 may not be continuous physical block addresses. In that case, the physical blocks 2 to 5 are scattered in the user data area of the flash memory 2.

Next, a non-optimal state that cannot support high-speed writing will be described.
Two examples of this non-optimal state will be described. In these two examples, the cause of the non-optimal state is different, but in either case, the write start page of the user data group based on the write command given from the host system 20 does not correspond to the first page of the physical block It has become.

FIG. 4 is an explanatory diagram when a logical block straddles two physical blocks.
In the example shown in FIG. 4, since the user data area is started from the first page of the physical block, a user data group that is data of 32 pages can be written at high speed for data 0 and data 1. However, since the data capacity of the data 2 is smaller than the data for 32 pages, the data 3 is written across the physical blocks 4 and 5. Therefore, in the data 3 writing process, when the writing destination is switched from the physical block 4 to the physical block 5, address translation and allocation of the erased physical block are performed.

  Therefore, the data 3 writing process cannot cope with high-speed writing. When the microprocessor 6 detects that the write start page of the user data group based on the data 3 write command does not correspond to the first page of the physical block, as described above, the setting information is not in the optimum state. What is necessary is just to change to the information shown.

  If the host system 20 knows that the host system 20 is in a non-optimal state based on the setting information, that is, a state where high-speed writing cannot be performed, the host system 20 performs initialization, data erasure, etc. to return to the optimal state. It can be performed.

FIG. 5 is an explanatory diagram of the writing start position of user data.
In the example shown in FIG. 5, since the user data area is not started from the first page of the physical block, all the writing processes of data 0 to 3 cannot support high-speed writing. When the data 0 writing process is performed, it is detected that the data is not in the optimum state, and the setting information is changed to information indicating that the data is not in the optimum state. In addition, initialization for returning to the optimum state can be performed. When the initialization is performed, the host system can know from the setting information that the host system has returned to a state capable of supporting high-speed writing.

The present embodiment as described above can be variously modified.
6 and 7 are explanatory diagrams showing modifications of the present embodiment.
In the above embodiment, the user data group is data for one block. However, if the data capacity of the physical block is large, one user data group cannot be associated with one physical block. Therefore, a plurality of user data groups must be associated with one physical block. In this case, all the write start pages of the user data group cannot correspond to the first page of the physical block. In such a case, each physical block may be divided into a plurality of sub-blocks so that each sub-block corresponds to a user data group. At this time, each physical block is preferably composed of sub-blocks having a power of 2.

  In the example shown in FIG. 6, each physical block is divided into two sub-blocks, and each sub-block (sub-block 2-0, sub-block 2-1, sub-block 3-0, sub-block 3-1, etc.) Are associated with user data groups (data 0 to 7). Therefore, when the physical block is composed of 32 pages, the optimum state is maintained when the write start page of the user data group corresponds to page 0 or page 16, that is, corresponds to the first page of the sub-block. It is determined that

  In the example shown in FIG. 7, each physical block is divided into four sub-blocks, and each sub-block (sub-block 2-0, sub-block 2-1, sub-block 2-2, sub-block 2-3, User data groups (data 0 to 15) are associated with blocks 3-0, sub-block 3-1, sub-block 3-2, sub-block 3-3, and the like. Therefore, when the physical block is composed of 32 pages, when the write start page of the user data group corresponds to page 0, page 8, page 16, or page 24, that is, corresponds to the first page of the sub-block. When it is determined that the optimum state is maintained.

1 is a block diagram of a flash memory system according to an embodiment of the present invention. It is a figure which shows the structure of a block and a page. It is explanatory drawing which shows the relationship between the system data area | region and user data area | region in the storage area of flash memory. It is explanatory drawing when a logical block straddles two physical blocks. It is explanatory drawing of the writing start position of user data. It is explanatory drawing which shows the modification of this embodiment. It is explanatory drawing which shows the modification of this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Internal interface block 11 ECC block 12 Flash memory sequencer block 20 Host system

Claims (7)

A flash memory and a host system having a storage area, wherein erasure of data in the storage area is performed in units of physical blocks composed of a plurality of pages, and in which data in units of pages can be written in the erased portion of the data; A memory controller for controlling access of the host system to the flash memory,
For the write data given from the host system together with the logical block address indicating the logical block to which the data belongs, a physical block address indicating the physical block to which the write data is written is set, and the write data is Writing means for writing in a position corresponding to the block address;
Information display means for determining whether or not a write start page of a user data group based on a write command given from the host system is appropriate, and indicating the result as determination information;
A memory controller comprising: The information display means that the write start page of the user data group is appropriate when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the physical block. The memory controller according to claim 1 , wherein the determination is made. The physical block is composed of a plurality of sub-blocks;
The information display means that the write start page of the user data group is appropriate when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the sub-block. The memory controller according to claim 1 , wherein the determination is made. Flash memory for storing data;
A memory controller according to any one of claims 1 to 3 ,
A flash memory system comprising: A flash memory having a storage area, and erasing data in the storage area is performed in units of physical blocks consisting of a plurality of pages, and in which data can be written in units of pages in an erased portion of the data, a control method for controlling access host system to the flash memory,
For the write data given from the host system together with the logical block address indicating the logical block to which the data belongs, a physical block address indicating the physical block to which the write data is written is set, and the write data is Write to the location corresponding to the block address;
Determining whether or not the write start page of the user data group based on the write command given from the host system is appropriate, and displaying the result as determination information;
And a flash memory control method. In the information display process, when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the physical block, the write start page of the user data group is appropriate. 6. The method of controlling a flash memory according to claim 5 , wherein: The physical block is composed of a plurality of sub-blocks;
In the information display process, when the write start page of the user data group based on the write command given from the host system corresponds to the first page of the sub-block, the write start page of the user data group is appropriate. 6. The method of controlling a flash memory according to claim 5 , wherein:

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