JP4177360B2 - Memory controller, flash memory system, and flash memory control method - Google Patents

Description

The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method .

  In recent years, a flash memory, which is a non-volatile recording medium, has been actively developed and is widely used as a storage medium for information devices such as digital cameras.

A memory controller is used to control access to the flash memory by such devices. In general, a memory controller stores a command set (or command sequence), which is an array of a series of commands that define various processing procedures such as reading and writing, in advance in its own ROM (Read Only Memory) or the like. . And when performing various processes, a desired process is implement | achieved by interpreting and executing a command set (for example, refer patent document 1).
JP-A-8-137763

  However, flash memories have different configurations and functions (for example, the presence or absence of a cache, the size of a page or block, the type of supported command, etc.) depending on the type.

  Corresponding to this, if a memory controller is developed separately for each type of flash memory, a situation occurs in which the development of the memory controller cannot catch up with the diversification of the flash memory.

The present invention has been made in view of the above circumstances, and provides a memory controller that can control various types of flash memories having different command set specifications, a flash memory system including the memory controller, and a flash memory control method . For the purpose.

A memory controller according to a first aspect of the present invention includes:
Command set acquisition means for acquiring a command set, which is a series of instructions that define a processing procedure for controlling the flash memory;
And command set holding means for holding a set of commands,
In response to an instruction from a host system that uses the flash memory as a storage medium, a command set corresponding to a process to be executed by the flash memory is acquired from the command set holding unit, and an instruction included in the command set is acquired. Control means to execute,
A specific page in the flash memory stores a command set including at least a read processing command set that defines a read processing procedure, and a page other than the specific page includes a command set other than the read processing command set. Command set is stored,
The command set acquisition means reads a command set stored in the specific page of the flash memory at startup,
The control unit reads a command set stored in a page other than the specific page of the flash memory using the command set of the read process included in the command set read by the command set acquisition unit, Storing in the command set holding means;
It is characterized by that.

A memory controller according to a second aspect of the present invention is:
Command set acquisition means for acquiring a command set, which is a series of instructions that define a processing procedure for controlling the flash memory;
Command set holding means for holding the command set;
In response to an instruction from a host system that uses the flash memory as a storage medium, a command set corresponding to a process to be executed by the flash memory is acquired from the command set holding unit, and an instruction included in the command set is acquired. Control means to execute,
The command set obtaining means, at start-up, an external storage device, acquires the command set of the read process that defines the procedure for read processing that is previously stored in the external storage device,
The flash memory, command set other than the command set of the reading process is stored,
Wherein said control means uses the command set of the read processing of the command set acquisition unit has acquired, and read out the command set stored in the flash memory is stored in the command set hold means.

A flash memory system according to a third aspect of the present invention includes a memory controller having at least one of the above characteristics and a flash memory.

Control method for a flash memory according to the fourth aspect of the present invention, a command set acquiring a command set is a series of instructions that define the steps of a process for controlling the flash memory, it stores a set of commands a command set holding step that holds the apparatus, the control step in response to a command from the host system utilizing the flash memory as a storage medium, for controlling the flash memory by using the command set held in the storage device When,
With
A specific page in the flash memory stores a command set including at least a read processing command set that defines a read processing procedure, and a page other than the specific page includes a command set other than the read processing command set. Command set is stored,
The command set acquisition step includes a step of reading a command set stored in the specific page of the flash memory at startup,
The control step reads a command set stored in a page other than the specific page using the command set of the read process included in the command set read by the command set acquisition step, and stores the memory Including storing in the device;
It is characterized by that.
A flash memory control method according to a fifth aspect of the present invention includes:
A command set acquisition step for acquiring a command set, which is a series of instructions that define a processing procedure for controlling the flash memory;
A command set holding step for holding the command set in a storage device;
A control step of controlling the flash memory using a command set held in the storage device in response to a command from a host system that uses the flash memory as a storage medium;
The command set acquisition step includes a step of acquiring a command set of read processing defining a procedure of read processing stored in advance in the external storage device from an external storage device at startup,
The flash memory stores a command set other than the command set for the reading process,
The control step includes a step of reading a command set stored in the flash memory using the command set of the reading process acquired by the command set acquisition step, and storing the command set in the storage device.
It is characterized by that.

  According to the present invention, the memory controller acquires a command set suitable for the flash memory to be controlled from the ROM or the flash memory itself, and controls the flash memory with the acquired command set. Different types of flash memory can be controlled.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When electrons are injected into the floating gate, electrons are injected by applying a high voltage at which the control gate is at the high potential side. Further, when electrons are discharged from the floating gate, electrons are discharged by applying a high voltage at which the control gate is on the low potential side.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is divided based on “page” and “block”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. A block is a processing unit in a data erasing operation performed in the flash memory 2.

  One page includes a 512-byte user area 25 and a 16-byte redundant area 26. The user area 25 stores user data supplied from the host system 4.

  The redundant area 26 is an area for recording additional data such as an error correction code, a corresponding logical block address, and a block status (flag).

  The error collection code is data for detecting and correcting an error included in the data stored in the user area 25.

  The corresponding logical block address indicates the address of the logical block with which the block is associated when valid data is stored in at least one user area 25 included in one block.

  The logical block address is a block address determined based on the host address given from the host system 4. On the other hand, an actual block address in the flash memory 2 is referred to as a physical block address.

  When valid data is not stored in all user areas 25 included in one block, the corresponding logical block address is not stored in the redundant area 26 included in the block.

  Therefore, by determining whether or not the corresponding logical block address is stored in the redundant area 26, it is possible to determine whether or not the data has been erased in the block including the redundant area 26. When the corresponding logical block address is not stored in the redundant area 26, the block is in a state where data is erased.

  One block includes 32 pages. In the flash memory 2, data cannot be overwritten. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the block including the page must be rewritten.

  After at least a portion of the data read from all pages in a block has been changed, the data must be written on a block basis to one of the erased blocks.

  In rewriting data as described above, the rewritten data is written in a block different from the previously stored block. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block address and the physical block address, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on the corresponding logical block address stored in the redundant area 26 of each page. Such a dynamic address management method is a method generally used in a memory system using a flash memory.

  The block status is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status indicating a defective block is written in the redundant area 26.

  The flash memory 2 receives data, address information, status information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates according to the internal command from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  The command set defines a sequence of execution of a series of internal commands for executing processing for the flash memory 2. The process defined by the command set includes, for example, a read process, a write process, and an erase process. In accordance with this command set, the controller 3 supplies internal commands, address information, data, and the like to the flash memory 2.

  The flash memory 2 according to the present embodiment has a command set that defines the procedure of the read process, device information indicating the manufacturer and various specifications of the flash memory 2, and other processes on a specific page read by an auto read process to be described later An address or the like in which a command set defining (a process other than the read process) is stored is stored in advance. This command set is assumed to be written in advance on the page at the time of manufacturing inspection of the flash memory 2, for example.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program recorded in the ROM 12 or the work area 8. For example, the microprocessor 6 reads a command set defining various processes from the work area 8, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute the process. In addition, the microprocessor 6 realizes an auto read function according to a program stored in the ROM 12 in advance. The auto-read function is a function for reading data stored in a specific page of the flash memory without giving a command and an address.

  The host interface block 7 exchanges data, address information, status information, external commands, and the like with the host system 4. That is, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, the data supplied from the host system 4 to the flash memory system 1 is taken into the controller 3 through the host interface block 7 and the data supplied from the flash memory system 1 to the host system 4 is The host interface block 7 is supplied to the host system 4 as an exit.

  More specifically, the host interface block 7 is a command register that temporarily stores a host address and an external command supplied from the host system 4, a sector number register that stores the size of data to be written or read, and a write or read command. An LBA (Logical Block Addressing) register for storing a logical address of data to be performed. Information is exchanged with the host system 4 via these registers.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address register, a command register, an instruction processing block, and the like.

  The address register is a register for storing the physical block address of the access destination. The physical block address is address information for designating a block in the flash memory 2 to be accessed by a series of control processes executed by the flash memory interface block 10.

  The command register is a register for storing a series of internal commands constituting the command set. This command set includes a command for instructing processing in the controller 3, an internal command to the flash memory 2, and a command for instructing supply of address information and the like.

  The instruction processing block outputs an internal command for controlling the flash memory 2, address information, and the like according to a series of internal commands stored in the command register.

  The flash memory interface block 10 supplies the flash memory 2 with internal commands, address information, and the like output from the instruction processing block, thereby causing the flash memory 2 to execute reading and writing.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines processing procedures such as an auto read function and an address conversion table.

  Next, the procedure of command set acquisition processing executed when the flash memory system 1 configured as described above is started will be described with reference to the flowchart shown in FIG.

  The command set acquisition process is executed by the microprocessor 6 when the flash memory system 1 is activated.

  When the command set acquisition process is started, the microprocessor 6 uses the auto-read function to start a command set that defines the procedure of the read process from a specific page of the flash memory 2 and other processes (other than the read process). An address storing a command set defining (processing) is acquired (step S100).

  Next, the microprocessor 6 stores the acquired read processing command set in the work area 8 (step S110).

  Then, the microprocessor 6 uses the acquired read process command set and address to acquire a command set that defines the procedure of other processes (processes other than the read process) from the flash memory 2 (step S120).

  The microprocessor 6 stores in the work area 8 a command set that defines the acquired procedure of other processing (step S130), and ends the command set acquisition processing.

  The controller 3 can obtain a command set suitable for the flash memory 2 to be controlled by executing the command set acquisition process described above. Then, in response to a request from the host system 4, the microprocessor 6 included in the controller 3 reads a command set necessary for processing from the work area 8, and sequentially executes a series of commands included in the command set. Then, desired processing such as reading processing and writing processing is executed.

  As described above, the controller 3 in the flash memory system 1 of the present embodiment acquires a command set suitable for the flash memory 2 written in advance in the flash memory 2 at the time of startup. Then, the subsequent processing is executed using the acquired command set. For this reason, the controller 3 is highly versatile and can control various types of flash memories 2.

Further, the flash memory 2 in the flash memory system 1 of the present embodiment stores a command set for read processing and an address at which a command set for other processing is stored in a specific page read by the auto read function. However, other command sets are stored in pages that cannot be read by the auto read function. Then, the controller 3 acquires a command set for other processing using the command set for read processing acquired by the auto read function.
Even if the command set for all processes cannot be stored in a page that can be read by the auto-read function, the command set for all processes is acquired. Subsequent processing can be executed.

  In the above embodiment, the command set stored in the page that can be read by the auto-read function of the flash memory 2 is only for the read process. However, as long as the capacity of the page allows, the command set for other processes is stored. May also be stored. If possible, all command sets may be stored on the page.

  In the above embodiment, the command set for the reading process is read from a specific page of the flash memory 2 by the auto read function at the time of activation. However, as shown in FIG. 4, the flash memory system 1 includes an external ROM 30 in addition to the flash memory 2 and the controller 3, and includes an external ROM interface block 15 inside the controller 3. At startup, a command set for read processing stored in advance in the external ROM 30 may be read, and a command set for other processing stored in the flash memory 2 may be acquired using the command set.

1 is a block diagram schematically showing a flash memory system according to the present invention. It is a figure which shows roughly the structure of the address space of flash memory. It is a flowchart explaining the procedure of a command set acquisition process. It is a block diagram which shows the modification of the flash memory system which concerns on this invention.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 15 External ROM interface block 25 User area 26 Redundant area 30 External ROM

Claims (5)

Command set acquisition means for acquiring a command set, which is a series of instructions that define a processing procedure for controlling the flash memory;
And command set holding means for holding a set of commands,
In response to an instruction from a host system that uses the flash memory as a storage medium, a command set corresponding to a process to be executed by the flash memory is acquired from the command set holding unit, and an instruction included in the command set is acquired. and control means for executing,
A specific page in the flash memory stores a command set including at least a read processing command set that defines a read processing procedure, and a page other than the specific page includes a command set other than the read processing command set. Command set is stored,
The command set acquisition means reads a command set stored in the specific page of the flash memory at startup,
The control unit reads a command set stored in a page other than the specific page of the flash memory using the command set of the read process included in the command set read by the command set acquisition unit, Storing in the command set holding means;
A memory controller characterized by that. Command set acquisition means for acquiring a command set, which is a series of instructions that define a processing procedure for controlling the flash memory;
Command set holding means for holding the command set;
In response to an instruction from a host system that uses the flash memory as a storage medium, a command set corresponding to a process to be executed by the flash memory is acquired from the command set holding unit, and an instruction included in the command set is acquired. Control means to execute,
The command set acquisition unit, when starting, an external storage device, acquires the command set of the read process that defines the procedure for read processing that is previously stored in the external storage device,
The flash memory, command set other than the command set of the reading process is stored,
Wherein said control means uses the command set of the read processing of the command set acquisition unit has acquired, and read out the command set stored in the flash memory is stored in the command set hold means,
Memory controller you, characterized in that. Flash memory system comprising: the memory controller; and a flash memory to claim 1 or 2. A command set acquisition step for acquiring a command set, which is a series of instructions for defining a processing procedure for controlling the flash memory;
A command set holding step that holds the storage device the command set,
A control step of controlling the flash memory using a command set held in the storage device in response to a command from a host system that uses the flash memory as a storage medium ;
A specific page in the flash memory stores a command set including at least a read processing command set that defines a read processing procedure, and a page other than the specific page includes a command set other than the read processing command set. Command set is stored,
The command set acquisition step includes a step of reading a command set stored in the specific page of the flash memory at startup,
The control step reads a command set stored in a page other than the specific page using the command set of the read process included in the command set read by the command set acquisition step, and stores the memory Including storing in the device;
A method for controlling a flash memory.   A command set acquisition step for acquiring a command set, which is a series of instructions for defining a processing procedure for controlling the flash memory;
  A command set holding step for holding the command set in a storage device;
  A control step of controlling the flash memory using a command set held in the storage device in response to a command from a host system that uses the flash memory as a storage medium,
  The command set acquisition step includes a step of acquiring a command set of read processing defining a procedure of read processing stored in advance in the external storage device from an external storage device at startup,
  The flash memory stores a command set other than the command set for the reading process,
  The control step includes a step of reading a command set stored in the flash memory using the command set of the reading process acquired by the command set acquisition step, and storing the command set in the storage device.
  A method for controlling a flash memory.

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