JP2008097339A - Memory controller, flash memory system having memory controller, and control method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain the effect of reducing wasteful memory data transfer (duplication) between two physical blocks (pair block) having stored data corresponding to an identical logical address, and to restrain the decrease of the number of idle blocks accompanying the increase of the pair blocks within a predetermined range. <P>SOLUTION: A memory controller discriminates the relationship of correspondence between a logical address based on instruction information given from a host system 4 and a physical block in a flash memory 2 in which the data corresponding to the logical address is stored. When the physical block having the data corresponding to the logical address is already existent, the memory controller stores the data into a physical block different from the physical block concerned. There retained are the information related to the relationship of correspondence between the pair blocks having the data corresponding to the identical logical address and information for managing the number of pairs of the pair blocks. When the number of pairs of the pair blocks reaches a predetermined figure, in regard to the pair block having the earliest order of becoming a pair block state, the pair block state is canceled. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, NAND flash memories are often used for memory cards and silicon disks. This NAND flash memory is a non-volatile memory. When the stored data is erased, that is, when the memory cell is changed from the write state (logical value = 0) to the erased state (logical value = 1), a block is used. Stored data can be erased only in units. Therefore, when rewriting the stored data, after rewriting the rewritten data in a physical block (second physical block) different from the physical block (first physical block) in which the original data was stored, The stored data of 1 physical block was erased.

  In such rewriting processing, storage data that is not subject to rewriting stored in the first physical block must be transferred (copied) from the first physical block to the second physical block. However, if the host system gives an instruction to rewrite the storage data that has been transferred (copied) after the storage data that is not to be rewritten is transferred (copied), the storage data transfer (copy) that was executed before that instruction is wasted Become.

In order to avoid such a problem, after the rewrite data is written in the second physical block, the storage data that is not the rewrite target is not transferred (copied), and the first physical block and the second physical block are allowed to coexist. The technique is disclosed in Patent Document 1.
JP 2002-324008 A

  As disclosed in Patent Document 1, if the first physical block and the second physical block coexist, useless transfer (copying) of stored data can be reduced. However, if there are too many pair blocks such as the first physical block and the second physical block, it becomes impossible to secure an empty block. In addition, in order to avoid the fact that an empty block cannot be secured, when the number of physical blocks allocated to a certain logical address area is increased, the data stored in the flash memory having the same storage capacity can be stored. Substantial capacity is reduced.

  If there are too many pair blocks and an empty block cannot be secured, storage data is transferred (copied) from the first physical block to the second physical block for any pair block. If the data stored in the first physical block is erased, an empty block can be secured. However, Patent Document 1 does not disclose management of priority when such pair block cancellation is performed.

  Therefore, the present invention provides a memory controller and a memory controller for managing the number of pairs of pairs (number of pairs) so as not to exceed a predetermined range in order to effectively use the pair blocks while avoiding the above problems. A flash memory system and a flash memory control method are provided.

  In order to achieve the above object, a memory controller according to the present invention is a memory controller that controls access to a flash memory that erases stored data in units of physical blocks in accordance with instruction information given from a host system, Address management means for managing the correspondence between the logical address based on the instruction information and the physical block in which data corresponding to the logical address is stored; and data corresponding to the logical address based on the instruction information are stored. Writing means for writing data corresponding to a logical address based on the instruction information in a physical block different from the physical block when the physical block is present, and two pieces of data in which the same logical address is stored Correspondence between pair blocks consisting of physical blocks, and Pair block management means for managing the number of pairs of pair blocks, and when the number of pairs of pair blocks reaches a predetermined number, the pair block status of the pair block whose earliest is the pair block status is canceled And a pair block elimination means.

  According to such a configuration, it is possible to suppress the decrease in the number of empty blocks due to the increase in the pair blocks within a predetermined range while maintaining the effect of reducing the transfer (copying) of useless storage data between the pair blocks. it can. Furthermore, since the pair block state is canceled in the order of the pair block state from the previous pair block, even if the number of pairs of pair blocks is limited, transfer (copy) of storage data between the pair blocks is wasted. The decrease in the effect of reducing can be minimized.

  Further, it is preferable that the writing means writes a pair block serial number for determining a first-to-last relationship of the order of the pair block state in the redundant area of the different physical block.

  In this way, if a pair block serial number is read out when there are a plurality of pairs of pairs, the prior relationship in the order of the pair block state can be determined.

  Further, the pair block management means writes the new / old relationship between the two physical blocks in which the data having the same logical address is stored in the redundant area of the physical block in which the new data is stored. It is preferable to determine the order of the order of the pair block state based on the pair block serial number.

  It should be noted that a serial number for determining the new / old relationship of stored data may be written in the redundant area of the physical block in which data having the same logical address is stored.

  A flash memory system according to the present invention includes the memory controller and the flash memory.

  A flash memory control method according to the present invention is a flash memory control method for controlling access to a flash memory that performs erasure of stored data in units of physical blocks in accordance with instruction information given from a host system. A logical address based on the information, an address determination step for determining a correspondence relationship between the physical block in which the data corresponding to the logical address is stored, and the data corresponding to the logical address based on the instruction information is stored A write step of writing data corresponding to a logical address based on the instruction information to a physical block different from the physical block when the physical block exists, and two physical blocks in which data having the same logical address is stored And the correspondence of the pair block consisting of A pair block management step for holding information for managing the number of pairs of blocks, and the pair block of the pair block having the earliest pair block state when the number of pairs of pair blocks reaches a predetermined number And a pair block elimination step for eliminating the state.

  According to such a method, while maintaining the effect of reducing the transfer (copying) of useless storage data between the pair blocks, it is possible to suppress the decrease in the number of free blocks due to the increase in the pair blocks within a predetermined range. it can. Furthermore, since the pair block state is canceled in the order of the pair block state from the previous pair block, even if the number of pairs of pair blocks is limited, transfer (copy) of storage data between the pair blocks is wasted. The decrease in the effect of reducing can be minimized.

  Further, in the writing step, it is preferable to write a pair block serial number for judging a first-to-last relationship of the order of the pair block state in the redundant area of the different physical block.

  In this way, if a pair block serial number is read out when there are a plurality of pairs of pairs, the prior relationship in the order of the pair block state can be determined.

  In the pair block management step, the new / old relationship between the two physical blocks in which the data having the same logical address is stored is written in the redundant area of the physical block in which the new data is stored. It is preferable to hold information for determining the order of the order of the pair block state based on the pair block serial number.

  It should be noted that a serial number for determining the new / old relationship of stored data may be written in the redundant area of the physical block in which data having the same logical address is stored.

  According to the memory controller, the flash memory system, and the flash memory control method of the present invention, by managing the number of pairs of pairs (number of pairs) so as not to exceed a predetermined range, While maintaining the effect of reducing the transfer (copying) of useless storage data between two physical blocks in which data corresponding to the address is stored, a decrease in the number of free blocks due to an increase in the number of pair blocks is predetermined. Can be kept within the range.

  Furthermore, by managing the priority when the pair blocks are eliminated, the effect of managing the number of pairs of pairs (number of pairs) so as not to exceed a predetermined range (required storage data between pair blocks). The effect of reducing the transfer (copying) can be minimized.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a flash memory system according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is connected to the host system 4 via the external bus 13.

  The host system 4 is composed of a CPU (Central Processing Unit) for controlling the entire operation of the host system 4 and a companion chip responsible for exchanging information with the flash memory system 1. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a nonvolatile memory, and data is copied between a register in the flash memory 2 and a memory cell array, and data is written or read. The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via this word line, that is, data is written (duplicated) from the register to the selected memory cell, or from the selected memory cell to the register. Data reading (copying) is performed. That is, the data given from the memory controller 3 is written into the memory cell array via the register, and the data stored in the memory cell array is supplied to the memory controller 3 via the register.

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, one gate is called a control gate, and the other gate is called a floating gate. Data is written or erased by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. In addition, when electrons are discharged from the floating gate, a high voltage at which the control gate is on the low potential side is applied between the control gate and the floating gate. Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)” as shown in FIG. A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages. FIG. 2 shows a structure in the case of a large block. One page is composed of a user area 25 of 4 sectors (2048 bytes) and a redundant area 26 of 64 bytes, and one physical block is 64. It consists of pages.

  In the case of a small block, one page is composed of a user area of 1 sector (512 bytes) and a redundant area of 16 bytes, and one physical block is composed of 32 pages. In the case of a large block, a 512-byte area obtained by dividing the user area 25 into four is called a subpage, and a partial area in the redundant area 26 is assigned to each subpage. Therefore, in the case of a large block, one physical block includes 256 subpages.

  Next, the address space on the host system 4 side and the address space on the flash memory 2 side will be described with reference to FIG. As shown in FIG. 3A, the address space on the host system 4 side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). In the memory controller 3, a group of a plurality of sectors is a logical block, and a group of a plurality of logical blocks is a logical zone. Here, as shown in FIG. 3B, the serial number assigned to the logical block is referred to as a logical block number (LBN), and the serial number assigned to the logical zone is referred to as a logical zone number (LZN). In addition, a serial number in each logical zone of a logical block included in each logical zone is referred to as a logical zone block number (LZIBN).

  In the address space on the flash memory 2 side, as shown in FIG. 3C, a unique physical block address (PBA) is assigned to each physical block. Further, when the storage area is divided into a plurality of zones for management, a physical zone is constituted by a plurality of physical blocks, and a unique physical zone number (PZN) is assigned to each physical zone. A serial number in each physical zone of a physical block included in each physical zone is referred to as a physical zone block number (PZIBN).

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Therefore, the number of sectors included in one logical block is set according to the number of sector areas included in one physical block. However, when one logical block is assigned to a plurality of physical blocks, the plurality of physical blocks are regarded as one physical block, and the number of sectors included in one logical block is set.

  FIG. 3 shows a case where one logical block is allocated to one physical block composed of 256 subpages. Therefore, 256 sectors correspond to one logical block, and the logical zone of LZN # 0 composed of 500 logical blocks of LBN # 0 to # 499 is in the 128000 sector area of LBA # 0 to # 127999. It corresponds. Similarly, for the logical zones after LZN # 1, the logical zone of LZN # 1 corresponds to the 128000 sector area of LBA # 128000 to # 255999, and the logical zone of LZN # 2 is LBA # 256000 to # 383999. Corresponding to the 128000 sector area, the logical zone of LZN # 3 corresponds to the 128000 sector area of LBA # 384000 to # 511999.

  The logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 is assigned to the physical zone of PZN # 0 configured with 512 physical blocks of PBA # 0 to # 511. Yes. Similarly, for the logical zones after LZN # 1, the logical zone of LZN # 1 is assigned to the physical zone of PZN # 1, the logical zone of LZN # 2 is assigned to the physical zone of PZN # 2, and LZN # The third logical zone is assigned to the physical zone of PZN # 3.

  Here, the number of physical blocks included in the physical zone is larger than the number of logical blocks included in the logical zone because the pair blocks (new data and old data corresponding to the same logical block are stored) This is to allow a pair of physical blocks). Therefore, in order to increase the allowable number of pair blocks, the number of physical blocks included in the physical zone may be increased. In addition, the number of physical blocks included in the physical zone must be set in consideration of a case where a defective block in which data cannot be normally written occurs.

  In this embodiment, in each physical block, data corresponding to the sectors included in the logical block assigned to the physical block is written in the LBA order. Therefore, by managing the correspondence between the physical block and the logical block, the correspondence between the area managed by the LBA on the host system 4 side and the storage area in the flash memory 2 can be managed.

  The correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table showing the correspondence between physical blocks and logical blocks is created, and the address conversion table is updated each time the correspondence changes. This address conversion table is created for each logical zone (physical zone corresponding to the logical zone). This address conversion table may be created at the time of activation, but may be created each time for a logical zone that is an access target.

  When creating the address conversion table, information indicating the logical block written in the redundant area 26 of the first page of the physical block (hereinafter referred to as logical address information) is read. As the logical address information written in the redundant area 26, information for specifying a logical block such as LBN is used. If the correspondence between the logical zone and the physical zone is set in advance as in this embodiment, an address translation table can be created based on LZIBN. Therefore, LZIBN with a smaller data amount than LBN can be created. It is preferably used as logical address information.

  FIG. 6 shows an example of the address conversion table 31. The correspondence between logical blocks and physical blocks is shown as the correspondence between LZIBN and PZIBN. In this address conversion table 31, physical blocks corresponding to 500 logical blocks LZIBN # 0 to # 499 included in the logical zone are assigned to the physical blocks in the physical zone assigned to the logical zone. Is shown.

  Further, a block status (flag) indicating whether or not the physical block is a defective block is written in the redundant area 26 of the first page of the physical block. Further, additional information such as an error correction code (ECC) corresponding to user data written in each subpage is written in the area allocated to each subpage in the redundant area 26.

  Next, the memory controller 3 that performs access processing to the flash memory 2 will be described. The memory controller 3 performs each process such as a read process, a write process, and a block erase process by supplying data, address information, internal commands, and the like to the flash memory 2.

  Here, the internal command is a command for the memory controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates according to the internal command given from the memory controller 3. On the other hand, a command given from the host system 4 to the memory controller 3 is called an external command.

  As shown in FIG. 1, the memory controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block 11. And a ROM (Read Only Memory) 12. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip.

  The microprocessor 6 controls the overall operation of the memory controller 3 in accordance with a program stored in the ROM 12.

  Further, the microprocessor 6 controls the operation of the flash memory interface block 10 and the like based on the program stored in the ROM 12, thereby enabling each of the address management means, the writing means, the pair block management means, the pair block elimination means, etc. Realize the means.

  The ROM 12 is a nonvolatile storage element, and stores a sequence command or the like that is an operation program of the flash memory interface block 10 in addition to an operation program of the microprocessor 6.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells. The above address conversion table is created on this work area 8.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The host interface block 7 exchanges data, address information, external commands, and the like with the host system 4 via the external bus 13. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. The flash memory interface block 10 executes various processes according to sequence commands set for each process such as a write process and a read process.

  The host interface block 7 and the flash memory interface block 10 have various registers as shown in FIG. The host interface block 7 includes a command register R1, a sector number register R2, an LBA register R3, and the like. The flash memory interface block 10 includes a physical block address register R11, a sector number register R12, a counter R13, and the like.

  Information given from the host system 4 is written in the command register R1, the sector number register R2, and the LBA register R3. External commands such as a write command and a read command are written in the command register R1. The number of sectors in the access target area is written in the sector number register R2. In the LBA register R3, the head LBA of the access target area is written.

  In the physical block address register R11, the sector number register R12, and the counter R13, based on the information written in the sector number register R2 and the LBA register R3, the physical block address (PBA) of the physical block to be accessed, the sub that starts access The page number (0 to 255) and the number of sectors to be accessed (number of subpages) are set.

  Here, the physical block address (PBA), subpage number, and sector number (number of subpages) set in the physical block address register R11, sector number register R12, and counter R13 will be described. As shown in FIG. 3, when one logical block includes an area of 256 sectors in which LBAs are continuous, the lower 8 bits of the LBA are serial numbers (hereinafter referred to as sectors) assigned to the sectors included in the logical block. Number (SN)). On the other hand, the upper bits excluding the lower 8 bits correspond to a logical block number (LBN) which is a serial number assigned to the logical block.

  In the physical block address register R11, the physical block address (PBA) of the physical block corresponding to the logical block specified by the logical block number (LBN) obtained based on the information written in the LBA register R3 and the sector number register R2 Alternatively, a physical block address (PBA) of an empty block is set. Here, the physical block address (PBA) of the empty block is set when data is rewritten, that is, when rewritten data is written in the empty block.

  Next, the correspondence between sector numbers (SN) and subpage numbers will be described. In the present embodiment, data corresponding to each sector included in the logical block is written to subpages in the physical block in the LBA order. Therefore, the same number corresponds to the subpage number (0-255) and the sector number (SN), which are serial numbers assigned to 256 subpages in the physical block. That is, data corresponding to sector number # 0 is written to a subpage of subpage number # 0, data corresponding to sector number # 1 is written to a subpage of subpage number # 1, and sector number # 2 The data corresponding to is written in the subpage of subpage number # 2.

  Since the sector number (SN) and the subpage number have such a correspondence, the sector number register R12 stores the access target area obtained based on the information written in the LBA register R3 and the sector number register R2. The sector number (SN) of the first sector is set. That is, the sector number (SN) of the head sector of the access target area obtained based on the information written in the LBA register R3 and the sector number register R2 matches the subpage number of the subpage from which access is started.

  In the counter R13, the number of sectors included in the access target area obtained based on the information written in the LBA register R3 and the sector number register R2 is set. That is, the number of sectors included in the access target area matches the number of subpages to be accessed.

  When the access target area specified based on the information set in the LBA register R3 and the sector number register R2 extends over a plurality of logical blocks, the physical block corresponding to the access target area also has a plurality of physical blocks. Since it extends over blocks, information is set for each physical block address register R11, sector number register R12, and counter R13 for each logical block.

  The flash memory interface block 10 executes write processing and read processing based on the values set in the physical block address register R11, sector number register R12, and counter R13 in this way.

  In the writing process, every time data of one sector is supplied from the buffer 9 to the flash memory 2, the value set in the sector number register R12 is incremented (incremented by 1), and the value set in the counter R13 is decremented. (Decremented by one). When the value set in the counter R13 becomes 0, the writing process ends. Accordingly, data for the sub-page corresponding to the value initially set in the counter R13 is written from the sub-page corresponding to the value initially set in the sector number register R12.

  Similarly, in the read process, every time data of one sector is read from the flash memory 2 to the buffer 9, the value set in the sector number register R12 is incremented (incremented by 1), and the value set in the counter R13 Is decremented (decremented by 1). When the value set in the counter R13 becomes 0, the reading process ends. Therefore, data for the subpage corresponding to the value initially set in the counter R13 is read from the subpage corresponding to the value initially set in the sector number register R12.

  For example, when “10” is set in the sector number register R12 and “8” is set in the counter R13 and the writing process is started, user data is written in the subpages of the subpage numbers # 10 to # 17.

  Next, the empty block search will be described. When the data stored in the flash memory is rewritten, the rewritten data is written in a physical block different from the physical block in which the original data is stored. Therefore, when the data stored in the flash memory is rewritten, a search for an empty block to which the rewritten data is to be written is performed. FIG. 5 shows an example of an empty block search table 33 used when searching for empty blocks.

  This empty block search table 33 is composed of 64 bytes (512 bits) of data, and indicates the use status of the physical blocks included in the physical zone by the logical value of each bit. That is, each bit corresponds to one physical block included in the physical zone, and a logical value “1” is set to the bit corresponding to the empty block. A logical value “0” is set in the bit corresponding to the physical block in which data is written and the bit corresponding to the defective block.

  In FIG. 5, 8 bits (1 byte) in the top row indicate the usage status of physical blocks PZIBN # 0 to # 7 in order from the lower side. Similarly, the second row indicates the usage status of the physical blocks PZIBN # 8 to # 15, and the third row indicates the usage status of the physical blocks PZIBN # 16 to # 23. The bottom line shows the usage status of physical blocks PZIBN # 504 to # 511. Therefore, the least significant bit of the top row indicates the usage status of the physical block of PZIBN # 0, and the most significant bit of the bottom row indicates the usage status of the physical block of PZIBN # 511.

  When searching for an empty block using this empty block search table 33, 1-byte data of each row is read sequentially from the upper row, and when the read data is not 0 (binary number display: 0000 0000) The data is written to the shift register, and the shift register is shifted in the lower direction. It is determined how many bits from the lower order are “1” depending on how many times the shift has occurred. For example, if 0001 1000 (binary number display) in the fourth row (PZIBN # 24 to # 31) is written to the shift register and the shift register is shifted in the lower direction, a carry occurs in four shifts. The physical block of PZIBN # 27 corresponding to the fourth bit from the lower side is detected as an empty block.

  In the next empty block search, the search is started from the fifth bit from the lower side of the fourth row. When the search starts from the fifth bit from the lower side in this way, a mask process is performed so that the lower 4 bits of the data to be set become “0” before setting the data in the shift register. .

  When data is written in the detected empty block, the bit on the empty block search table 33 corresponding to the physical block is rewritten from “1” to “0”. Further, when the data stored in the physical block in which the original data is stored is erased by rewriting the data, the bit on the empty block search table 33 corresponding to the physical block is rewritten from “0” to “1”. . On the other hand, for the address translation table (the address translation table showing the correspondence between the logical block and the physical block by the correspondence between LZIBN and PZIBN), the PZIBN corresponding to the LZIBN of the logical block corresponding to the written data is the original Is changed from PZIBN of the physical block in which the data is stored to PZIBN of the physical block in which the rewrite data is written.

  Next, management of pair blocks according to the present invention will be described. This pair block is two physical blocks corresponding to the same logical block. As described above, when data stored in the flash memory 2 is rewritten, a physical block (second physical block) different from the physical block (first physical block) in which the original data is stored. Rewrite data is written in Here, if there is a subpage not included in the rewrite range after the subpage included in the rewrite range, the subpage not included in the rewrite range is changed from the first physical block to the second physical block. The two physical blocks (the first physical block and the second physical block) corresponding to the same logical block coexist without transferring (copying) the data. Here, for data having the same LBA stored in the pair block (data stored in a subpage having the same subpage number), the data stored in the second physical block is prioritized. For data stored only in one physical block, the data stored in the first physical block is valid.

  In this way, when the host system side gives a write instruction with continuous access target areas, that is, when the rewrite range based on the write instruction given from the host system side is continuous, Rewrite data can be continuously written to the second physical block without transferring (duplicating) useless data from one physical block to the second physical block. However, if the number of pair blocks becomes too large, it becomes impossible to secure empty blocks.

  Therefore, in the management of pair blocks according to the present invention, the maximum number of pair blocks is set, and when the number of pair blocks (number of pairs) reaches the maximum number, the oldest pair block (the pair block state is set). For the data stored only in the first physical block of the first paired block), the data is transferred (copied) from the first physical block to the second physical block, and this data is transferred. After the (copying) is completed, the storage data of the first physical block is erased, and the number of pairs of pairs (number of pairs) is managed so as not to exceed a predetermined maximum number.

  A method for managing the pair blocks will be described with reference to FIGS. In the present embodiment, the maximum number of pair blocks is 2. Also, in order to determine the new / old relationship of the pair block (first-to-last relationship in the order of the pair block state), the 2-bit pair block serial number (# 0 to # 3) is written in the redundant area of the first page of the physical block. It is out. The number of bits of the pair block serial number is appropriately set according to the maximum number of pair blocks. For example, if the maximum number of pair blocks is 3 or less, it is possible to determine the new / old relationship of the pair blocks with a 2-bit pair block serial number, but if the maximum number of pair blocks is 4, the pair block serial number Unless 3 is set to 3 bits (# 0 to # 7), it is impossible to determine the new / old relationship between the pair blocks.

  In the following description, it is assumed that the access target area based on the write (rewrite) instruction given from the host system 4 is included in the logical zone of LZN # 0. Assume that an address conversion table 31 as shown in FIG. 6 and an empty block search table 33 as shown in FIG. 5 have been created for this logical zone of LZN # 0. Further, it is assumed that there is no pair block at the time when the following processing is started, and no information is set in the pair block table described later.

  First, when the access target area based on the write (rewrite) instruction given from the host system is the area of 96 sectors of SN # 64 to # 159 of the logical block of LBN # 0 (= LZIBN # 0) Will be described (* 1 shown in FIG. 7A).

  First, by referring to the address conversion table 31, it can be seen that data corresponding to a logical block of LZIBN # 0 (= LBN # 0) is stored in a physical block of PZIBN # 22 (= PBA # 22). Furthermore, it can be seen that there is no pair block by referring to a pair block table described later.

  Subsequently, the write state of the physical block of PZIBN # 22 (= PBA # 22) is checked, and data is written in all the subpages, so that a free block search using the free block search table 33 is performed. In this empty block search, PZIBN # 27 (= PBA # 27) is detected, and writing (rewriting) processing for the physical block of PBA # 27 (PZIBN # 27) is started.

  In this writing (rewriting) process, first, the data stored in the subpages of subpage numbers # 0 to # 63 of the physical block of PZIBN # 22 (= PBA # 22) is converted to PZIBN # 27 (= PBA # 27). ) Are transferred (copied) to subpages of subpage numbers # 0 to # 63 of the physical block. Subsequently, the rewrite data (rewrite data A) corresponding to the sectors of SN # 64 to # 159 of the logical block of LBN # 0 (= LZIBN # 0) given from the host system 4 is PZIBN # 27 (= PBA # 27). ) Physical block sub-page numbers # 64 to # 159.

  Since no pair block exists at the time of starting this writing (rewriting) process, # 0 is written as the pair block serial number in the redundant area of the physical block of PZIBN # 27 (= PBA # 27). Further, in order to determine the new and old relationship between the physical block of PZIBN # 22 (= PBA # 22) and the physical block of PZIBN # 27 (= PBA # 27) corresponding to the same logical block, PZIBN # 27 (= PBA # 27 The serial number is written in the redundant area of the physical block. The serial number written in the physical block of PZIBN # 27 (= PBA # 27) becomes # 1 obtained by incrementing (adding 1) the serial number written in the physical block of PZIBN # 22 (= PBA # 22). . Further, the logical value of the bit corresponding to the physical block of PZIBN # 27 (= PBA # 27) in the empty block search table 33 is rewritten from “1” to “0”.

  After this, if a write (rewrite) instruction including a sector after SN # 160 of the logical block of LBN # 0 (= LZIBN # 0) is given to the access target area, PZIBN # 27 (= PBA # 27) The write (rewrite) processing is continued for the subpages after the subpage number # 160 of the physical block (). Therefore, the data stored in the subpages # 160 to # 255 of the physical block of PZIBN # 22 (= PBA # 22) is changed to the subpage number of the physical block of PZIBN # 27 (= PBA # 27). Data transfer (copying) to the subpages # 160 to # 255 is not performed. In other words, if there is a subpage not included in the rewrite range after the subpage included in the rewrite range, the storage data that is not the rewrite target is not transferred (duplicated) to the subpage not included in the rewrite range. .

  Here, since the physical block of PZIBN # 22 (= PBA # 22) and the physical block of PZIBN # 27 (= PBA # 27) become a pair block, information for managing the pair block is set in the pair block table. The

  FIG. 8 shows an example of the pair block table 32. In this pair block table 32, the logical block LZIBN corresponding to the pair block, the pair block new and old physical block PZIBN, and the old and new relationship are shown. The pair block serial number written in the newer physical block is set. Here, as shown in FIG. 8A, the LZIBN of the logical block corresponding to the physical block of PZIBN # 22 (= PBA # 22) and the physical block of PZIBN # 27 (= PBA # 27). # 0, # 27 which is the PZIBN of the physical block with the newer old / new relationship, and # 0 which is the pair block serial number written in the redundant area of the physical block of PZIBN # 27 (= PBA # 27) are set.

  Next, the access target area based on the write (rewrite) instruction given from the host system is the area of 96 sectors of SN # 32 to # 127 of the logical block of LBN # 2 (= LZIBN # 2). The writing (rewriting) process in this case will be described (* 2 shown in FIG. 7B).

  Also in the case of this writing (rewriting) process, first, the address conversion table 31 and the pair block table are referred to. By referring to the address conversion table 31, it can be seen that data corresponding to the logical block of LZIBN # 2 (= LBN # 2) is stored in the physical block of PZIBN # 6 (= PBA # 6). Further, by referring to the pair block table 32, it can be seen that a pair block exists and the pair block serial number corresponding to the pair block is # 0.

  Subsequently, the writing state of the physical block of PZIBN # 6 (= PBA # 6) is checked, and data is written in all the subpages, so that a free block search using the free block search table 33 is performed. In this empty block search, PZIBN # 28 (= PBA # 28) is detected, and writing (rewriting) processing for the physical block of PBA # 28 (PZIBN # 28) is started.

  In this writing (rewriting) process, first, data stored in subpages of subpage numbers # 0 to # 31 of a physical block of PZIBN # 6 (= PBA # 6) is stored in PZIBN # 28 (= PBA # 28). ) Are transferred (copied) to subpages of subpage numbers # 0 to # 31 of the physical block. Subsequently, rewrite data (rewrite data B) corresponding to the sectors of SN # 32 to # 127 of the logical block of LBN # 2 (= LZIBN # 2) given from the host system 4 is PZIBN # 28 (= PBA # 28). ) Physical block subpage numbers # 32 to # 127.

  In addition, in the redundant area of the physical block of PZIBN # 28 (= PBA # 28), # 0 is written as the serial number, and # 1 is written as the pair block serial number. Here, the serial number written in the redundant area of the physical block of PZIBN # 28 (= PBA # 28) is incremented from the serial number written in the redundant area of the physical block of PZIBN # 6 (= PBA # 6) ( 1). The pair block serial number written in the redundant area of the physical block of PZIBN # 28 (= PBA # 28) is the pair block serial number written in the redundant area of the physical block of PZIBN # 27 (= PBA # 27). The number is incremented (added 1). Further, the logical value of the bit corresponding to the physical block of PZIBN # 28 (= PBA # 28) in the empty block search table 33 is rewritten from “1” to “0”.

  Here, since the physical block of PZIBN # 6 (= PBA # 6) and the physical block of PZIBN # 28 (= PBA # 28) are pair blocks, there are two pair blocks. Therefore, in order to set the pair block information including the physical block of PZIBN # 6 (= PBA # 6) and the physical block of PZIBN # 28 (= PBA # 28) in the pair block table 32, set in the pair block table The pair block state of the physical block of PZIBN # 22 (= PBA # 22) and the physical block of PZIBN # 27 (= PBA # 27) must be canceled. In order to eliminate this pair block state, data transfer (copying) indicated by * 3 in FIG. 7A must be performed.

  In this data transfer (copying), the data stored in the subpages of subpage numbers # 160 to # 255 of the physical block of PZIBN # 22 (= PBA # 22) is PZIBN # 27 (= PBA # 27). Are transferred (copied) to subpages of subpage numbers # 160 to # 255 of the physical block. After this data transfer (copying) is completed, the storage data of the physical block of PZIBN # 22 (= PBA # 22) is erased. The PZIBN corresponding to LZIBN # 0 in the address conversion table 31 is rewritten from # 22 to # 27, and the logical value of the bit corresponding to the physical block of PZIBN # 22 (= PBA # 22) in the empty block search table 33 is It is rewritten from 0 to 1.

  On the other hand, in the pair block table 32, as shown in FIG. 8B, information on a pair block consisting of a physical block of PZIBN # 6 (= PBA # 6) and a physical block of PZIBN # 28 (= PBA # 28). Is set. That is, the physical block of PZIBN # 6 (= PBA # 6) and the physical block of PZIBN # 28 (= PBA # 28) are LZIBN of the logical block corresponding to # 2, and the physical block with the newer and older relationship is the newer Set # 1 which is the pair block serial number written in the redundant area of the physical block of PZIBN # 28 and PZIBN # 28 (= PBA # 28).

  Next, a description will be given of a case where the host system gives a write (rewrite) instruction to the 192 sector area of SN # 64 to # 255 of the logical block of LBN # 1 (= LZIBN # 1) (FIG. 9B). * 4).

  This writing (rewriting) process is started after data transfer (copying) (* 3 in FIG. 7A) for canceling the pair block state is completed. Therefore, a pair block existing when starting the rewriting process is a pair block composed of a physical block of PZIBN # 6 (= PBA # 6) and a physical block of PZIBN # 28 (= PBA # 28) (FIG. 9A )) Only.

  Also in the case of this writing (rewriting) process, first, the address conversion table 31 and the pair block table are referred to. By referring to the address conversion table 31, it can be seen that data corresponding to the logical block of LZIBN # 1 (= LBN # 1) is stored in the physical block of PZIBN # 12 (= PBA # 12). Further, by referring to the pair block table 32, it can be seen that a pair block exists and the pair block serial number corresponding to the pair block is # 1.

  Subsequently, the writing state of the physical block of PZIBN # 12 (= PBA # 12) is checked, and data is written in all the subpages, so that a free block search using the free block search table 33 is performed. In this empty block search, PZIBN # 50 (= PBA # 50) is detected, and writing (rewriting) processing for the physical block of PBA # 50 (PZIBN # 50) is started.

  In this writing (rewriting) process, first, the data stored in the subpages of subpage numbers # 0 to # 63 of the physical block of PZIBN # 12 (= PBA # 12) is PZIBN # 50 (= PBA # 50). ) Are transferred (copied) to subpages of subpage numbers # 0 to # 63 of the physical block. Subsequently, rewrite data (rewrite data C) corresponding to the sectors of SN # 64 to # 255 of the logical block of LBN # 1 (= LZIBN # 1) given from the host system 4 is PZIBN # 50 (= PBA # 50). ) Physical block subpage numbers # 64 to # 255.

  It should be noted that # 3 is written as the serial number and # 2 is written as the pair block serial number in the redundant area of the physical block of PZIBN # 50 (= PBA # 50). Here, the serial number written in the redundant area of the physical block of PZIBN # 50 (= PBA # 50) is incremented by the serial number written in the redundant area of the physical block of PZIBN # 12 (= PBA # 12) ( 1). The pair block serial number written in the redundant area of the physical block of PZIBN # 50 (= PBA # 50) is the pair block serial number written in the redundant area of the physical block of PZIBN # 28 (= PBA # 28). The number is incremented (added 1). Further, the logical value of the bit corresponding to the physical block of PZIBN # 50 (= PBA # 50) in the empty block search table 33 is rewritten from “1” to “0”.

  All data stored in the physical block of PZIBN # 12 (= PBA # 12) when this writing (rewriting) process is completed is stored in the physical block of PZIBN # 50 (= PBA # 50). Since it is replaced with data, the address conversion table 31 is updated, but the pair block table 32 is not updated. That is, after this write (rewrite) process is completed, the data stored in the physical block of PZIBN # 12 (= PBA # 12) is erased, and PZIBN corresponding to LZIBN # 1 in the address conversion table 31 is from # 12. The logical value of the bit corresponding to the physical block of PZIBN # 12 (= PBA # 12) in the empty block search table 33 is rewritten from 0 to 1.

  Thereafter, when a write (rewrite) instruction is given from the host system, the pair block set in the pair block table 32 is set in the redundant area of the physical block in which the rewrite data given from the host system 4 is written. A number obtained by incrementing (adding 1) the serial number, that is, a number obtained by incrementing (adding 1) the pair block serial number written in the redundant area of the physical block of PZIBN # 28 (= PBA # 28) is written. .

  In the embodiment described above, since the maximum number of pair blocks is 2, the information (LZIBN, PZIBN and pair block serial number) set in the pair block table 32 is one set. When the number is n, information that can be set in the pair block table 32 may be n-1 sets. For example, when the maximum number of pair blocks is 3, up to two sets of information are set in the pair block table 32 as shown in FIG.

  As shown in FIG. 10, when two sets of information are set in the pair block table 32, the pair block serials in the next order are included in the redundant area of the physical block with the newer relationship between the new pair block and the newer one. A number obtained by incrementing the number (adding 1) is written. That is, as shown in FIG. 10, when the pair block serial numbers set in the pair block table 32 are # 3 and # 0, # 1 obtained by incrementing # 0 (adding 1) is the new pair block. Are written in the redundant area of the newer physical block.

  When a new pair block is created, the pair block state of the pair block corresponding to the pair block serial number in the order is canceled. That is, as shown in FIG. 10, when the pair block serial numbers set in the pair block table 32 are # 3 and # 0, the pair block state of the pair block corresponding to the logical block of LZIBN # 7 is eliminated. Is done.

  As described above, in the memory controller of the present invention, the flash memory including the memory controller, and the flash memory control method, the number of pairs of pairs and the old and new relationships of the pair blocks (the order of the order of the pair blocks) When the number of pair blocks reaches the preset maximum number, the pair block status of the oldest pair block (the pair block status is the earliest pair block) is canceled. is doing. Accordingly, it is possible to suppress the decrease in the number of empty blocks accompanying the increase in the pair blocks within a predetermined range while maintaining the effect of reducing the transfer (copying) of useless storage data between the pair blocks.

  The memory controller of the present invention, the flash memory including the memory controller, and the flash memory control method are not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the claims. is there. For example, the pair block serial number, the pair block table, and the like can be variously modified and improved as long as the relationship between the order of the pair block state can be determined.

1 is a block diagram showing a schematic configuration of a flash memory system according to an embodiment of the present invention. It is a figure which shows the physical address space in flash memory. It is a figure explaining the address translation from LBA to a physical block address (PBA). It is a block diagram which shows the register structure of the host interface block and flash memory interface block by one embodiment of this invention. It is a figure which shows an example of a structure of an empty block search table. It is a figure which shows an example of a structure of an address conversion table. It is the schematic which shows the data storage state of the physical block in the data rewriting process. It is a figure which shows an example of a structure of a pair block table. It is the schematic which shows the data storage state of the physical block in the data rewriting process. It is a figure which shows an example of a structure of a pair block table.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus

Claims (7)

A memory controller that controls access to a flash memory that performs erasure of stored data in units of physical blocks in accordance with instruction information given from a host system,
Address management means for managing the correspondence between the logical address based on the instruction information and the physical block in which data corresponding to the logical address is stored;
Write means for writing data corresponding to the logical address based on the instruction information to a physical block different from the physical block when there is the physical block storing data corresponding to the logical address based on the instruction information;
A pair block management means for managing the correspondence between the pair blocks consisting of two physical blocks in which data having the same logical address is stored, and the number of pairs of the pair blocks;
When the number of pairs of the pair blocks reaches a predetermined number, a pair block canceling unit that cancels the pair block state of the pair block that is the earliest in the order of the pair block state;
A memory controller comprising:   2. The memory controller according to claim 1, wherein the writing unit writes a pair block serial number for determining a first-to-last relationship of the order of the pair block state in a redundant area of the different physical block.   The pair block management means is a pair in which the new / old relationship between two physical blocks in which data having the same logical address is stored is written in a redundant area of the physical block in which new data is stored The memory controller according to claim 1, wherein the first or second order of the pair block state is determined based on the block serial number.   A flash memory system comprising the memory controller according to claim 1 and the flash memory. A flash memory control method for controlling access to a flash memory that performs erasure of stored data in units of physical blocks in accordance with instruction information given from a host system,
An address determination step of determining a correspondence relationship between a logical address based on the instruction information and the physical block in which data corresponding to the logical address is stored;
A writing step of writing data corresponding to the logical address based on the instruction information in a physical block different from the physical block when there is the physical block storing data corresponding to the logical address based on the instruction information;
A pair block management step for holding a correspondence relationship between a pair block composed of two physical blocks in which data having the same logical address is stored, and information for managing the number of pairs of the pair block;
When the number of pairs of the pair blocks reaches a predetermined number, a pair block cancellation step of canceling the pair block state of the earliest pair block in the order of the pair block state,
A method for controlling a flash memory, comprising:   6. The flash memory control method according to claim 5, wherein, in the writing step, a pair block serial number for determining a first-to-last relationship of the order of the pair block state is written in a redundant area of the different physical block. .   In the pair block management step, the pair in which the new / old relationship between the two physical blocks in which the data having the same logical address is stored is written in the redundant area of the physical block in which the new data is stored 7. The flash memory control method according to claim 5 or 6, wherein information for determining the order of the order of the pair block state is retained based on the block serial number.

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