JP4661748B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory.

  Among flash memories that are particularly frequently used in the above memory system, there is a NAND flash memory. In the NAND flash memory, each memory cell can be changed from an erased state corresponding to a logical value “1” to a written state corresponding to a logical value “0” independently of other memory cells. . In contrast, when changing from the written state to the erased state, each memory cell cannot be changed independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”. The writing process or the reading process for the NAND flash memory is executed in units of a predetermined number of memory cells called pages. A block which is a unit of erasing processing is composed of a plurality of pages.

  In the NAND flash memory having the above-described configuration, data cannot be overwritten. Therefore, when data is rewritten, new data (data after rewriting) is erased in a block erased block. ) And erase the block in which the old data (data before rewriting) has been written.

  When such data rewriting is performed, the rewritten data is written in a different block from the data before rewriting. Accordingly, the correspondence between the logical block address given from the host system side and the physical block address in the flash memory dynamically changes every time data is rewritten. Therefore, when accessing the flash memory, an address conversion table showing the correspondence between the logical block address and the physical block address is required.

  That is, when accessing the flash memory, it is necessary to perform address processing for converting a logical block address to a physical block address and free block search for searching for an erased block.

  In order to avoid a decrease in the access speed due to the time required for this address conversion process, in Patent Document 1, when the access target of the flash memory extends over a plurality of logical blocks, it is divided into groups for each logical block, In each group, access to the flash memory and address conversion processing for obtaining the physical address of the access destination are executed in parallel. Thus, Patent Document 1 improves the processing efficiency when accessing the flash memory.

JP 2006-155335 A

  When the access to the flash memory and the address conversion process for obtaining the physical address of the access destination are executed in parallel as described above, the flash memory sequence block in the memory controller executes the access to the flash memory, and the microprocessor in the memory controller However, the address conversion process was executed. However, in Patent Document 1, it is difficult for the microprocessor to grasp the access status of the flash memory sequence block. In addition, after the flash memory sequence block starts operating, it is difficult for the microprocessor to stop the operation.

  Therefore, when the voltage applied to the flash memory system suddenly drops, it is impossible to stop writing, and there is a problem that the writing ends and the data in the flash memory becomes abnormal.

  Therefore, the present invention improves the processing efficiency when accessing the flash memory by executing the access to the flash memory and the address conversion process in parallel, and even if the voltage applied to the flash memory system is reduced, It is an object of the present invention to provide a memory controller, a flash memory system, and a flash memory control method capable of preventing memory data from becoming abnormal.

  In order to achieve the above object, a memory controller of the present invention is a memory controller that controls access to a flash memory that executes erasure of stored data in units of blocks in accordance with instruction information given from a host system. Code set storage means storing a plurality of sets of code sets including a plurality of operation instruction codes for instructing control operations to be executed to control access to the memory, and the operations stored in the code set storage means Address holding means for holding an address of an instruction code, and when the instruction information is given, the code set corresponding to an external command included in the instruction information is selected, and the operation instruction code included in the code set Code set for setting the address of the address in the address holding means Selection means, control operation execution means for reading the operation instruction code from the code set storage means in accordance with the address set in the address holding means, and executing a control operation based on the operation instruction code, and execution of the control operation Address update for changing the address set in the address holding means to the address of the operation instruction code corresponding to the next control operation to be executed each time the means executes a control operation based on the operation instruction code And means.

  Thus, the control operation execution means reads the operation instruction code from the code set storage means according to the address set in the address holding means, and operates based on the read operation instruction code. By referring to the address set in the address holding unit, the operation status of the control operation executing unit, that is, the access status to the flash memory can be easily grasped. Therefore, when stopping the control operation of the control operation executing means, the timing for stopping the control operation can be determined based on the address set in the address holding means.

  The memory controller of the present invention may change the address set in the address holding unit when the control operation executing unit executes a series of control operations based on the code set. It is preferable to provide forcible termination means for terminating the control operation.

  That is, the control operation execution means reads the operation instruction code from the code set storage means according to the address set in the address holding means, and operates based on the read operation instruction code. By changing the address set in the holding means, the operation of the control operation executing means can be easily controlled.

  The memory controller according to the present invention preferably includes address conversion means for obtaining a physical block address of the block in the flash memory corresponding to the access target area specified based on the instruction information.

  In order to achieve the above object, a flash memory system of the present invention includes the memory controller and a flash memory.

  In order to achieve the above object, a flash memory control method according to the present invention stores data in advance in order to control access to a flash memory that erases stored data in units of blocks in accordance with instruction information given from a host system. A flash memory control method for executing a series of control operations based on a code set including a plurality of operation instruction codes stored in a means, and included in the instruction information when the instruction information is given A code set selection step of selecting the code set corresponding to an external command and setting an address of the operation instruction code included in the code set in an address holding unit; and storing the memory according to an address set in the address holding unit Reading the operation instruction code from the means, based on the operation instruction code A control operation execution step for executing the control operation, and a control to be executed next to the address set in the address holding means each time the control operation based on the operation instruction code is executed in the control operation execution step And an address update step of changing to the address of the operation instruction code corresponding to the operation.

  Thus, in the control operation execution step, the operation instruction code is read from the storage unit according to the address set in the address holding unit, and the control operation is executed based on the read operation instruction code. By referring to the address set in the address holding means, the access status to the flash memory can be easily grasped. Therefore, when the access to the flash memory is stopped, the timing for stopping the control operation can be determined based on the address set in the address holding means.

  The flash memory control method of the present invention forcibly executes a series of control operations based on the code set selected in the code set selection step by changing the address set in the address holding means. Preferably, a forcible termination step is included.

  That is, in the control operation execution step, the operation command code is read from the storage unit according to the address set in the address holding unit, and the control operation is executed based on the read operation command code. By changing the address set in the address holding means, the access operation to the flash memory can be easily controlled.

  According to the present invention, it is possible to execute in parallel a read or write process for a flash memory, an address conversion process for obtaining an access destination physical address, and an empty block search. Thereby, the processing efficiency when accessing the flash memory can be improved.

  The microprocessor in the memory controller can easily grasp the operation status of the flash memory sequence block in the memory controller and can easily stop the operation of the flash memory sequence block. Therefore, when the voltage applied to the flash memory system decreases, the data in the flash memory can be prevented from becoming abnormal by stopping the writing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing the flash memory system 1. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

[Description of flash memory 2]
The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 performs data copying between the register and the memory cell array to write or read data.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the two gates are called a control gate and a floating gate. Data can be written or erased by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Done.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  FIG. 2 is an explanatory diagram showing the relationship between blocks and pages. Although the configuration of the block and page differs depending on the specifications of the flash memory, a small block flash memory as shown in FIG. 2A and a large block flash memory as shown in FIG. Has been used. In the small block configuration, as shown in FIG. 2A, one block includes 32 pages (P0 to P31), and each page includes a 512-byte user area and a 16-byte redundant area. In the large block configuration of the present embodiment, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. It consists of

  In the case of a large block configuration, data for 4 sectors is stored in the user area of each page, so if the area for 1 sector is a subpage, each page is composed of 4 subpages. Consists of 256 subpages. The physical address for specifying the storage area in the flash memory 2 includes a physical block address for specifying a block of the flash memory 2 (hereinafter referred to as a physical block) and a subpage for specifying a subpage in each physical block. Generated based on the number (0-255). For the flash memory 2, a row address for specifying a page and a column address for specifying an area in the page are given as address information for specifying a storage area. Each subpage is assigned an area obtained by dividing the redundant area into four.

  On the other hand, in the case of the small block configuration, since data for one sector is stored in the user area of each page, the subpage is the same as the page. Similar to the large block configuration, the physical address for specifying the storage area in the flash memory 2 includes the physical block address for specifying the physical block of the flash memory 2 and the page number (0 to 31) for specifying the page in each physical block. Is generated based on Similarly, to the flash memory 2, a row address specifying a page and a column address specifying an area in the page are given as address information specifying a storage area.

  Here, the user area is mainly an area where data supplied from the host system 4 is stored, and the redundant area is stored with additional data such as an error correction code, corresponding logical address information and block status. Area. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block 11 described later.

  Corresponding logical address information is written when data is stored in a physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the corresponding logical address information is not written, so it is determined whether or not the block is an erased block depending on whether the corresponding logical address information is written. can do. That is, if the corresponding logical block address is not written, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). When it is determined that the physical block is a bad block Is set with a flag indicating that it is a bad block.

[Description of controller 3]
As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12.

  The host interface block 7 exchanges data, address information, status information, external commands (commands given from the host system 4 to the flash memory system 3) and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 is a block that controls a writing process from the buffer 9 to the flash memory 2 and a reading process from the flash memory 2 to the buffer 9. A series of control operations when executing a writing process, a reading process, and the like are executed based on information instructing a series of control operations stored in the ROM 12. Information indicating each control operation included in the series of control operations is hereinafter referred to as an operation instruction code. A set of operation instruction codes corresponding to each control operation included in a series of control operations is referred to as a code set.

  The operation instruction code includes an instruction to output a control signal, a command, an address, write data, or the like to the flash memory 2, an instruction to specify a branch destination based on a branch condition, or a flash memory. There is an instruction to wait for the busy state of 2 to be released. In addition, the operation instruction codes are normally read in the order they are described. If an operation instruction code that indicates a branch destination is included, the operation instruction code that is read next in accordance with the operation instruction code that indicates the branch destination. To decide.

  FIG. 3 is a diagram showing a register configuration of the flash memory interface block 10. The physical block address register 21 is a register that designates a physical block in the flash memory 2, and the subpage number register 22 is a register that designates a subpage in the physical block. The counter 23 is a register that specifies the number of subpages to be read or written. The program counter 24 is a register for designating the address in the ROM 12 of the operation instruction code.

  The ECC block 11 generates an ECC added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the ECC added to the data read from the flash memory 2.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. The code set is stored in the ROM 12.

  FIG. 4 is a diagram for explaining a code set and an operation instruction code. A plurality of code sets are stored in the code set area in the ROM 12. The microprocessor 6 selects a code set to be given to the flash memory interface block 10 from a plurality of code sets stored in the ROM 12 according to an external command included in the instruction information from the host system.

  All the code sets include a branch instruction. Finally, a branch is made to the final operation instruction code in the code set area, and a series of control operations corresponding to the code set is completed. Thus, all code sets finally branch to the same operation instruction code, that is, branch to the same address and end. In the present embodiment, the final operation instruction code performs an operation for causing the microprocessor 6 to generate an interrupt, and notifies the microprocessor 6 that the access to the flash memory 2 has been completed.

[Description of address conversion process]
In the flash memory system 1 according to the present embodiment, a zone is formed by a plurality of physical blocks, and a predetermined logical address area is assigned to each zone.

  FIG. 5 is an explanatory diagram for explaining the address conversion process. The address conversion process will be specifically described with reference to FIG.

  The logical address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes) as shown in FIG. Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. Further, as shown in FIG. 5B, the serial numbers assigned to the logical blocks are called logical block numbers (LBN), and the serial numbers assigned to the logical zones are called logical zone numbers (LZN). In addition, a serial number in each logical zone of a logical block included in each logical zone is called a logical zone block number (LZIBN). On the other hand, as shown in FIG. 5C, each physical block is assigned a unique physical block address (PBA). Further, a physical zone is constituted by a plurality of physical blocks, and a serial number assigned to each physical zone is called a physical zone number (PZN). A serial number in each physical zone of a physical block included in each physical zone is called an intra-physical zone block number (PZIBN).

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Therefore, the number of sectors included in one logical block is set according to the number of sector areas included in one physical block. However, when one logical block is assigned to a plurality of physical blocks, the plurality of physical blocks are regarded as one physical block, and the number of sectors included in one logical block is set.

  In the example shown in FIG. 5, a flash memory in which one physical block is composed of 256 sector areas is assumed, and therefore 256 sectors correspond to one logical block. Therefore, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 corresponds to the 128000 sector area of LBA # 0 to # 127999. Similarly, the logical zone of LZN # 1 corresponds to the 128000 sector area of LBA # 128000 to # 255999, the logical zone of LZN # 2 corresponds to the 128000 sector area of LBA # 256000 to # 383999, The logical zone of LZN # 3 corresponds to the 128000 sector area of LBA # 384000 to # 511999.

  In addition, the logical zone of LZN # 0 configured with 500 logical blocks of LBN # 0 to # 499 is allocated to the physical zone of PZN # 0 configured with 512 physical blocks of PBA # 0 to # 511. It has been. Similarly, the logical zone of LZN # 1 is assigned to the physical zone of PZN # 1, the logical zone of LZN # 2 is assigned to the physical zone of PZN # 2, and the logical zone of LZN # 3 is assigned to PZN #. Assigned to three physical zones. Here, the reason why the number of physical blocks included in the physical zone is larger than the number of logical blocks included in the logical zone is that new data and old data corresponding to the same logical block coexist in different physical blocks. This is a case in which a case where a defective block in which data cannot be normally written is generated.

  In addition, since the data of the logical blocks assigned to the physical block are written in each physical block in the LBA order, the LBA given from the host system 4 is managed by managing the correspondence between the physical block and the logical block. And the access relationship in the flash memory 2 can be managed.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. When a physical block corresponding to a logical block does not exist in the address translation table and when a page in which data is written is rewritten, it is necessary to search for an erased block (or a physical block in which valid data is not stored). . For this reason, a table for searching for an erased block (hereinafter referred to as an empty block search table) is created together with the address conversion table.

  This address conversion table is created based on information (hereinafter referred to as logical address information) indicating a logical block written in the redundant area of the first page of the physical block. As the logical address information written in the redundant area, information that can specify a logical block such as LBN is used. If the correspondence between the logical zone and the physical zone is set in advance, the logical block can be specified based on the LZIBN, so that an address conversion table can be created. It is preferable to use less LZIBN.

  Further, no logical address information is stored in a physical block in which no data is written. Therefore, when the logical address information is not stored, it is determined that the block is an erased block.

[Description of access to flash memory]
Next, processing when instruction information is given from the host system 4 will be described.

  When the host system 4 executes reading or writing with respect to the flash memory 2, information related to the access target area is supplied together with external commands such as reading and writing. This access target area is specified by a sector-by-sector logical address (for example, LBA) and the number of sectors. Here, the logical address supplied from the host system 4 indicates the head address to be accessed, and the number of sectors supplied from the host system 4 indicates how many sectors from the head address are to be accessed. Show.

  Here, when the access area instructed from the host system 4 extends over a plurality of logical blocks, conversion processing from logical blocks to physical blocks must be performed for each logical block. Therefore, the instruction information from the host system 4 is divided into groups for each logical block, and the flash memory 2 is accessed for each group.

  That is, the microprocessor 6 uses the physical block address register 21, the subpage number register 22, the counter 23 of the flash memory interface block 10 as information for executing a series of control operations corresponding to each instruction information divided into groups. And the program counter 24 is set. The flash memory interface block 10 executes a series of control operations based on information set in the physical block address register 21, the sub page number register 22, the counter 23, and the program counter 24.

Processing performed by the microprocessor 6 when instruction information is given from the host system 4 will be described with reference to FIG. FIG. 6 is a flowchart showing processing performed by the microprocessor 6 for the flash memory interface block 10.
(S61) A logical block including the access target area is obtained based on the information indicating the access area included in the instruction information given from the host system 4, and further, the physical block address (PBA) of the physical block corresponding to the logical block Is obtained by address conversion processing. That is, in S61, first, the logical block number (LBN) of the logical block including the access target area is obtained. Subsequently, the physical block address (PBA) of the physical block corresponding to the logical block including the access target area is referred to by referring to the address conversion table showing the correspondence between the logical block number (LBN) and the physical block address (PBA). Is required.
(S64) When the flash memory interface block 10 is in operation, the process waits for the operation to end. When the operation has ended, the process proceeds to S62. Here, whether or not the flash memory interface block 10 is operating is determined by whether or not there is an interrupt from the flash memory interface block 10.
(S62) Information indicating an area in the flash memory is set in the physical block address register 21, the sub page number register 22, and the counter 23 of the flash memory interface block 10. Specifically, the physical block address (PBA) obtained in S 61 is set in the physical block address register 21. Next, the lower 8 bits (0 to 255) of the LBA corresponding to the head sector of the access target area are set in the subpage number register 22. Finally, the number of sectors included in the access target area is set in the counter 23. Here, when the access area does not extend over a plurality of logical blocks, the number of sectors included in the instruction information from the host system 4 matches the value set in the counter 23. On the other hand, when the access area specified by the host system 4 extends over a plurality of logical blocks, the number of sectors included in the access target area in each logical block is set in the counter 23.
(S63) The address of the operation instruction code is set in the program counter 24 of the flash memory interface block 10. Here, the address of the head operation instruction code of the code set corresponding to the command included in the instruction information from the host system 4 is set in the program counter 24. For example, when the command is a command that instructs reading, the address of the head operation instruction code of the code set corresponding to a series of control operations executed by the flash memory interface block 10 at the time of reading is set in the program counter 24. After the address of the operation instruction code is set in the program counter 24, the flash memory interface block 10 starts a series of control operations shown in FIG.

  After setting the operation instruction code in the program counter 24, the process returns to S61, and if there is an access target area based on the instruction information given from the host system 4, the physical block physical corresponding to the logical block including the access target area is returned. The block address (PBA) is obtained.

  As described above, the microprocessor 6 performs address conversion processing while the flash memory interface block 10 is accessing the flash memory 2. As a result, the address conversion process and the flash memory 2 are accessed in parallel.

Next, a series of control operations executed by the flash memory interface block 10 will be described. The flash memory interface block 10 reads the operation instruction code from the address set in the program counter 24 and executes a control operation corresponding to the operation instruction code. Each time the control operation ends, the address set in the program counter 24 is advanced by one step. When branching, the branch destination address is set in the program counter 24. FIG. 7 is a flowchart showing a series of control operations executed by the flash memory interface block 10 during the read process or the write process. These control operations are executed based on each operation instruction code read from the ROM 12. Each control operation is executed based on one or more operation instruction codes.
(S71) A command and an address are supplied to the flash memory 2 to transmit / receive data. For example, in the case of reading processing, first, an internal command (read command) for instructing reading to the flash memory 2 is supplied. Subsequently, a row address specifying a page in which data to be read is stored and a column address specifying a read start position (0 byte to 2111 bytes) in the page are supplied to the flash memory 2. When reading data from the first subpage, the column address specifies the address corresponding to the first subpage. Here, the flash memory 2 is in a busy state in order to read (copy) data from the memory cell array to the register. After the busy state of the flash memory 2 is released, a high level signal and a low level signal are alternately input to the read enable terminal of the flash memory 2, and data corresponding to the first subpage is read from the register in the flash memory 2. .

  Next, an internal command (random read command) for instructing the change of the reading start position in the page and a column address for specifying the position where the ECC corresponding to the head subpage is stored are supplied. Thereafter, high level and low level signals are alternately input to the read enable terminal of the flash memory 2, and the ECC corresponding to the first subpage is read from the register in the flash memory 2.

  Here, an internal command (read command) instructing reading is supplied only when data is first read from each page. For example, when data is read from the second subpage in the page after data is read from the first subpage (including ECC), the internal instructing the change of the read start position in the page is the same as described above. A command (random read command) and a column address corresponding to the second subpage are supplied.

  When the user area of one subpage is composed of four subpages, the physical page address (PBA) set in the physical block address register 21 is set in the subpage number register 22. The row address is generated by concatenating the upper 6 bits (0 to 63 in decimal) of the 8-bit value. The column address is generated based on the value of the lower 2 bits (0 to 3 in decimal) of the 8-bit value set in the subpage number register 22. That is, when the lower 2 bits of the 8-bit value stored in the subpage number register 22 are 00 (decimal 0), the column address is an address corresponding to the first subpage. Similarly, when the lower 2 bits are 01 (decimal 1), the column address is the address corresponding to the second subpage, and when the lower 2 bits is 10 (decimal 2), the column address Is the address corresponding to the third subpage. When the lower 2 bits are 11 (3 in decimal), the column address is the address corresponding to the fourth subpage.

  On the other hand, in the case of write processing, an internal command (input command) for instructing data transfer to a register in the flash memory 2, a row address, and a column address are supplied to the flash memory 2. Subsequently, a high level signal and a low level signal are alternately input to the write enable terminal of the flash memory 2, and one sector of data is supplied to the flash memory 2 in accordance with this signal. Next, an internal command (random input command) for instructing the change of the column address and a column address for designating the position of a redundant area in which additional data such as ECC is written are supplied to the flash memory 2. Subsequently, a high level signal and a low level signal are alternately input to the write enable terminal of the flash memory 2, and additional data such as ECC is supplied to the flash memory 2 in accordance with this signal.

  Here, an internal command (input command) for instructing data transfer is supplied only when write data is first transferred to each page. For example, when transferring data to be written to the second subpage within the page after transferring data to be written to the first subpage (including additional data), the internal addressing the column address change is the same as above. A column address corresponding to the command (random input command) and the second subpage is supplied.

When data held in a register in the flash memory 2 is written (copied) to the memory cell array, an internal command (program command) for instructing writing (copying) from the register to the memory cell array is sent to the flash memory 2. To supply. This internal command (program command) is supplied after the transfer of the data to be written to the fourth subpage and the additional data corresponding to this data is completed.
(S72) The values set in the subpage number register 22 and the counter 23 in the flash memory interface block 10 are updated. In this update, the value set in the subpage number register 22 is incremented (added by 1), and the value set in the counter 23 is decremented (subtracted by 1). That is, every time reading or writing for one sector is completed, the value set in the subpage number register 22 is increased by 1, and the value set in the counter 23 is decreased by 1.
(S73) If the value installed in the counter 23 is 0, the process proceeds to S74, and if it is not 0, the process proceeds to S71. For example, in the reading process in which the value m is set in the subpage number register 22 and the value n is set in the counter 23, data of n sectors stored in the subpages of the subpage numbers #m to # m + n−1 are read. Then, the process proceeds to S74.
(S74) An interrupt for notifying the microprocessor 6 that a series of control operations has been completed is generated. That is, when the value set in the counter 23 is 0, the process branches to the final operation instruction code and generates an interrupt.

  FIG. 8 is a diagram showing an example of a logical address space and a physical address space in the embodiment of the present invention. The access processing of the present invention will be specifically described with reference to this figure.

  A case will be described in which the instruction information from the host system 4 is a read process (1) of 4 sectors from LBA # 510. Since the read process (1) spans two logical blocks, it is grouped into a read process (1 ′) for two sectors from LBA # 510 and a read process (1 ″) for two sectors from LBA # 512.

  In S61, the microprocessor 6 performs an address conversion process for access of the read process (1 ′). As shown in FIG. 8B, LBA # 510 to # 511, which are access target areas of the read process (1 ′), are included in LBN # 1. Therefore, the physical block address (PBA) of the physical block corresponding to the logical block of LBN # 1 is obtained by referring to the address conversion table. As shown in FIG. 8C, when the logical block of LBN # 1 corresponds to the physical block of PBA # 4, the physical block address (PBA) obtained by this address conversion process is PBA # 4. The address conversion table can be created for each zone by reading the logical address information from the redundant area of the physical block included in each physical zone. The address conversion table is created at startup or before access.

  In S 63, the address of the head operation instruction code of the code set corresponding to the read command (external command) given from the host system 4 is set in the program counter 24. The flash memory interface block 10 starts a series of control operations corresponding to the read process (1 ′) based on information set in the physical block address register 21, the sub page number register 22, the counter 23, and the program counter.

  After the setting of the information corresponding to the read process (1 ′) is completed in S62 and S63, the process returns to S61 to perform the address conversion process for access of the read process (1 ″) as shown in FIG. As described above, LBA # 512 to # 513, which are access target areas of the read process (1 ″), are included in LBN # 2. Therefore, the physical block address (PBA) of the physical block corresponding to the logical block of LBN # 2 is obtained by referring to the address conversion table. As shown in FIG. 8C, when the logical block of LBN # 2 corresponds to the physical block of PBA # 1, the physical block address (PBA) obtained by this address conversion process is PBA # 1.

  If the flash memory interface block 10 is executing a series of control operations, the process waits for the end of the series of control operations, confirms the end of the series of control operations, and then, in S62, the physical block address register 1 is set to 21. In addition, since the top sector of the access target area for the read process (1) is LBA # 512 and is “10 0000 0000” in binary, the lower 8 bits are “0000 0000” in binary (0 in decimal) Accordingly, 0 is set in the subpage number register 22. Also, since the number of sectors included in the access target area of the read process (1 ") is 2, 2 is set in the counter 23.

  In S63, the address of the head operation instruction code of the code set corresponding to the read command (external command) given from the host system is set in the program counter 24. The flash memory interface block 10 starts a series of control operations corresponding to the read process (1 ″) based on the information set in the physical block address register 21, the subpage number register 22, the counter 23, and the program counter.

  Next, a series of control operations executed by the flash memory interface block 10 will be specifically described. Since the reading process (1 ′) and the reading process (1 ″) are the same process, only a series of control operations corresponding to the reading process (1 ′) will be described. Command) is supplied to the flash memory 2. Next, 4 (100 in binary number) set in the physical block address register 21 and 254 (1111 1110 in binary number) set in the subpage number register 22 are set. Is generated, and the generated row address is supplied to the flash memory 2. Subsequently, the sub page number register 22 is set. The lower 2 bits of 254 (1111 1110 in binary) are 10 (2 in decimal), so the third sub The column address of the page is supplied to the flash memory 2.

  After the busy state of the flash memory 2 is released, high level and low level signals are alternately input to the read enable terminal of the flash memory 2 to read data of one sector corresponding to the third subpage. Next, an internal command (random read command) for instructing the change of the reading start position in the page and a column address for specifying the position where the ECC corresponding to the third subpage is stored are supplied. Thereafter, a high level signal and a low level signal are alternately input to the read enable terminal of the flash memory 2, and the ECC corresponding to the third subpage is read.

  In S72, the value set in the subpage number register 22 is changed from 254 (binary 1111 1110) to 255 (binary 1111 1111), and the value set in the counter 23 is changed from 2 to 1. To do.

  Since the value set in the counter 23 is 1, the process returns to S71 (S73). Here, since the lower 2 bits of 255 (1111 1111 in binary number) set in the subpage number register 22 are 11 (3 in decimal number), an internal command (instruction for changing the read start position in the page) Random read command) and the column address of the fourth sub-page are supplied to the flash memory 2. Thereafter, a high level signal and a low level signal are alternately input to the read enable terminal of the flash memory 2 to read data of one sector corresponding to the fourth subpage. Next, an internal command (random read command) for instructing the change of the reading start position in the page and a column address for specifying the position where the ECC corresponding to the fourth subpage is stored are supplied. Thereafter, high level and low level signals are alternately input to the read enable terminal of the flash memory 2, and the ECC corresponding to the fourth subpage is read.

In S72, the value set in the subpage number register 22 is changed from 255 (binary 1111 1111) to 0 (binary 0000 0000), and the value set in the counter 23 is changed from 1 to 0. To do.
Since the value set in the counter 23 is 0, the process proceeds to S74 (S73), and an interrupt is generated to notify the microprocessor 6 that the series of control operations has been completed.

  As described above, in the flash memory system 1 of the present invention, the read process or the write process and the address conversion process can be executed in parallel.

  Furthermore, in the flash memory system 1 of the present invention, the operation status of the flash memory sequence block 10 can be easily grasped, and a series of control operations executed by the flash memory sequence block 10 can be easily stopped. be able to.

  That is, in the flash memory system of the present invention, the flash memory sequence block 10 reads the operation instruction code from the ROM 12 according to the address set in the program counter 24, and executes the control operation based on the read operation instruction code. By referring to the address set to 24, the control operation executed by the flash memory sequence block 10 can be grasped.

  Further, when the flash memory sequence block 10 is executing a series of control operations, when the voltage supplied to the flash memory system 1 becomes lower than a predetermined voltage value or when new instruction information is received from the host system. When given, a series of control operations executed by the flash memory sequence block 10 are forcibly terminated by changing the address set in the program counter 24 to an address corresponding to the final operation instruction code. Can do. In addition, when forcibly terminating a series of control operations executed by the flash memory sequence block 10, it is terminated at a timing at which a problem such as incomplete data being written to the flash memory 2 does not occur. Is preferred. For example, when the voltage drops, it is preferable to forcibly end the control operation without executing writing (copying) from the register to the memory cell array even if write data is held in the register in the flash memory 2. .

  Although the present embodiment has been described with respect to a large block flash memory, the present invention can be similarly applied to a small block flash memory.

  Moreover, all the embodiment described above shows the present invention exemplarily, and does not limit the present invention, and the present invention can be implemented in other various modifications and changes. Therefore, the scope of the present invention is defined only by the claims and their equivalents.

1 is a block diagram schematically showing a flash memory system in an embodiment of the present invention. FIG. It is explanatory drawing which shows the relationship between a block and a page. It is a figure which shows the register structure of the flash memory interface block of embodiment of this invention. It is a figure for demonstrating a code set and an operation instruction code. It is explanatory drawing for demonstrating an address conversion process. It is a flowchart which shows the process which a microprocessor performs to a flash memory interface block. It is a flowchart which shows the process which a flash memory interface block performs. It is a figure which shows an example of the logical address space in the embodiment of this invention, and a physical address space.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 21 Physical block address register 22 Subpage number register 23 Counter 24 Program counter

Claims (5)

A memory controller that controls access to a flash memory that performs erasure of stored data in units of physical blocks in accordance with instruction information given from a host system,
Code set storage means for storing a plurality of code sets including a plurality of operation instruction codes for instructing a control operation to be executed to control access to the flash memory;
Address holding means for holding an address of the operation instruction code stored in the code set storage means;
When the instruction information is given, a code set that selects the code set corresponding to the external command included in the instruction information and sets the address of the operation instruction code included in the code set in the address holding unit A selection means;
Logical block management means for managing areas of a plurality of sectors assigned logical addresses in units of sectors as logical blocks;
Indicating the logical address, sector number assigned to the logical block upper side of bits indicating a logical block number assigned to a region of the logical block of the first part of the access area designated by the instruction information Logical address dividing means for dividing into lower bits,
Address converting means for converting the logical block number obtained by the logical address dividing means into a physical block address of the physical block corresponding to the logical block number;
Access area information holding means for holding the physical block address obtained by the address conversion means, the sector number obtained by the logical address dividing means, and the number of sectors of the access area;
Control operation executing means for reading the operation instruction code from the code set storage means according to the address set in the address holding means and executing a control operation based on the operation instruction code;
Each time the control operation execution means executes a control operation based on the operation instruction code, the address set in the address holding means is changed to the address of the operation instruction code corresponding to the control operation to be executed next. An address update means to be changed;
An information updating means for updating the sector number and the number of sectors held in the access area information holding means each time access for one sector is completed,
The control operation executing means divides the sector number held in the access area information holding means into upper bits and lower bits, and converts the upper bits into the access area information holding means. To generate a row address for specifying a physical page in the flash memory by connecting to the lower side of the physical block address held in the sector, and based on the lower bit of the sector number, a sector in the physical page is generated. Generate a column address that identifies the area,
The information update means increases the sector number by 1 and decreases the number of sectors by 1 each time access for one sector is completed.   Forcibly ending means for ending the series of control operations by changing the address set in the address holding means when the control action execution means is executing a series of control operations based on the code set. The memory controller according to claim 1, further comprising:   A flash memory system comprising the memory controller according to claim 1 and a flash memory. In order to control access to the flash memory that executes erasure of stored data in units of physical blocks in accordance with instruction information given from the host system, a code set including a plurality of operation instruction codes stored in advance in the storage means A flash memory control method for performing a series of control operations based on
Code set selection for selecting the code set corresponding to the external command included in the instruction information when the instruction information is given, and setting the address of the operation instruction code included in the code set in the address holding means Steps,
The area of the plurality sectors logical addresses of sectors are assigned managed as logical blocks, the logical address of the head region of the access area designated by the instruction information, the logical block number assigned to the logical block A logical address dividing step of dividing the high-order bit indicating the bit and the low-order bit indicating the sector number assigned to the area in the logical block;
An address conversion step of converting the logical block number obtained by the logical address division step into a physical block address of the physical block corresponding to the logical block number;
An access area information setting step for setting the physical block address obtained by the address conversion step, the sector number obtained by the logical address division step, and the number of sectors of the access area in an access area information holding unit; and A control operation execution step of reading the operation instruction code from the storage unit according to an address set in the holding unit and executing a control operation based on the operation instruction code;
Each time the control operation based on the operation instruction code is executed in the control operation execution step, the address set in the address holding means is changed to the address of the operation instruction code corresponding to the control operation to be executed next. An address update step to be changed;
An information update step of updating the sector number and the number of sectors held in the access area information holding means each time access for one sector is completed,
In the control operation executing step, the sector number held in the access area information holding means is divided into upper bits and lower bits, and the upper bits are divided into the access area information holding means. To generate a row address for specifying a physical page in the flash memory by connecting to the lower side of the physical block address held in the sector, and based on the lower bit of the sector number, a sector in the physical page is generated. Generate a column address that identifies the area,
In the information updating step, the flash memory control method is characterized by incrementing the sector number by 1 and decrementing the number of sectors by 1 each time access for one sector is completed.   Including a forced termination step of forcibly terminating a series of control operations based on the code set selected in the code set selection step by changing an address set in the address holding unit. The method of controlling a flash memory according to claim 4.

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