JP4501881B2 - Memory controller and flash memory system - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed, and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased.

  Further, the flash memory is often used as an external storage device (flash memory system) of a host system such as a personal computer or a digital camera, and may be arbitrarily attached or detached. For this reason, for example, when the external storage device (flash memory system) is pulled out from the host system during the data write (save) operation to the flash memory, data that has not been written normally (abnormal data) remains. May end up.

  From this point of view, in Patent Document 1 and the like, a predetermined flag is set when updating the data stored in the flash memory, and when the update is completed, another flag is set and the update is normally completed. The technique shown is disclosed. If this technique is used, it is possible to detect the abnormal end when the writing process is ended halfway due to power interruption or the like (hereinafter referred to as abnormal end).

However, when the writing process ends abnormally due to power interruption or the like, the data stored in the flash memory cannot be separated into normal data and abnormal data.
JP 2005-174232 A

  When the writing process ends abnormally and normal data and abnormal data coexist in the physical block in the flash memory that was the data write destination, it is necessary to separate them and leave only normal data.

  In addition, the flash memory, which is a data write destination, has been increased in capacity, and a user area of one page has one sector (512 bytes), and one block has 32 pages (hereinafter referred to as a small block type). ), The user area of one page is shifting to a configuration of 4 sectors (2048 bytes) and 1 block of 64 pages (hereinafter referred to as a large block type). That is, from a small block type in which a user area included in one block is composed of 32 sector areas (512-byte areas), a user area included in one block is 256 sector areas (512 bytes). Are moving to the large block type.

  When the capacity (number of sectors) of one physical block is increased in this way, the number of times that the host system gives a write request for the same physical block as the write destination increases, and the write destination when the write processing ends abnormally. Since the amount of data written to the physical block increases, the process of discriminating between normal data and abnormal data becomes more complicated.

  The present invention has been made in view of the above circumstances, and when write processing ends abnormally, normal data and abnormal data coexisting in the physical block in the flash memory that was the data write destination are easily discriminated. An object of the present invention is to provide a memory controller that can be used, and a flash memory system including the memory controller.

In order to achieve the above object, the memory controller of the present invention accesses a flash memory in which the user area of each page included in a physical block is composed of one or a plurality of sector areas in response to an instruction from the host system. A memory controller for controlling
In response to a data write command from the host system, i) a series of data is sequentially written in the sector area, and ii) data is written in a redundant area corresponding to the sector area in which the series of data is written. Iii) writing means for writing an end mark indicating that end data of a series of data is written in a redundant area corresponding to the sector area in which end data of the series of data is written; ,
Abnormal end detection means for detecting that the writing of the series of data did not end normally based on the writing mark and the end mark;
Normal data detection means for detecting the end of a sector area in which the series of data is normally written based on the write mark and the end mark;
Equipped with a,
The write mark includes order information indicating what number of series of data written in the physical block,
Information indicating that the order information corresponding to the series of data that has not been normally written indicates the first when the abnormal end detection means detects that the series of data has not been written normally. The normal data detection means does not perform the process of detecting the end of the sector area in which the series of data is normally written, and determines that there is no series of data that is normally written.
It is characterized by that.

  A flash memory system according to the present invention includes the memory controller and a flash memory.

  According to the present invention, if a series of data write processing to the flash memory is abnormally terminated, that is, if a series of data write processing ends abnormally without writing the end data of the series of data, the last data The write mark is written in the redundant area corresponding to the sector area in which is written, but the end mark is not written. Therefore, when both the write mark and the end mark are not written in the redundant area corresponding to the sector area in which the data is written last, it can be determined that the series of data writing processes has ended abnormally. .

  Further, when it is determined that the series of data write processing has ended abnormally, the end of the sector area in which the series of data is normally written can be detected based on the end mark.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory 2 shown in FIG. 2, one page is composed of a user area 25 of 4 sectors (2048 bytes) and a redundant area 26 of 64 bytes, and one physical block is composed of 64 pages. Yes.

  Each physical block is assigned a unique physical block address (PBA). Further, when the storage area is divided into a plurality of zones for management, a physical zone is constituted by a plurality of physical blocks, and a unique physical zone number (PZN) is assigned to each physical zone. A serial number in each physical zone of a physical block included in each physical zone is referred to as a physical zone block number (PZIBN).

  On the other hand, the address space on the host system 4 side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. A serial number assigned to a logical block is called a logical block number (LBN), and a serial number in each logical block of sectors included in each logical block is called a sector number (SN). Further, the serial number assigned to the logical zone is called a logical zone number (LZN), and the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, information (hereinafter referred to as logical address information) that can identify a logical block corresponding to the data is written in the redundant area 26 of the physical block in which the data is written. As this logical address information, LZIBN with a small amount of data is generally written, but LBN may be written.

  The correspondence relationship between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created to manage the correspondence between the two at each time point, and is updated each time the correspondence changes. Since the correspondence relationship between the logical zone and the physical zone is set in advance, this address conversion is performed by referring to the logical address information written in the redundant area 26 of the physical block included in the physical zone to be accessed. A table can be created for each logical zone.

  Next, a page storage area composed of a user area 25 of 4 sectors (2048 bytes) and a redundant area 26 of 64 bytes will be described with reference to FIG. The user area 25 of each page is divided into four areas (hereinafter referred to as sector areas 25 '). Each sector area 25 ′ stores one sector (512 bytes) of user data supplied from the host system 4.

  On the other hand, the redundant area 26 is also divided into four areas (hereinafter referred to as a partial redundant area 26 '), and a 16-byte area is allocated to each of the partial redundant areas 26'. In the partial redundancy area 26 ′ of each page, an error correction (ECC) code of user data written in the corresponding sector area 25 ′, a write mark and an end mark indicating the write state of the corresponding sector area 25 ′, respectively. Is written. Further, logical address information and block status (flag) are written in the partial redundancy area 26 'of the first page of each physical block.

  The ECC code is data for detecting and correcting an error included in the user data stored in the sector area 25 '.

  The write mark is information indicating whether user data is written in the corresponding sector area 25 '. The end mark is information indicating the sector area 25 ′ in which the last user data is written in a writing process for writing a series of user data (hereinafter, a writing process for writing a series of user data is referred to as a sequence writing process). That is, when user data of a plurality of sectors is written by the sequence writing process, a write mark is written in the partial redundancy area 26 ′ corresponding to the sector area 25 ′ in which the user data is written by the sequence writing process, and the user data at the end is written. Is written in the partial redundancy area 26 'corresponding to the sector area 25'. Here, the sequence writing process refers to a series of user data writing processes executed based on information set in the flash memory interface block 10. When the access target area based on the write command given from the host system 4 does not extend over a plurality of physical blocks, one sequential write process is executed based on one write command given from the host system 4 Is done.

  The correspondence between each sector area 25 'and each partial redundancy area 26' can be set as appropriate. For example, as shown in FIG. 3, the first sector area 25 ′ in the user area 25 is used as the first partial redundant area 26 ′ in the redundant area 26, and the second sector area 25 ′ in the user area 25 is used as the redundant area. 26, the third sector area 25 ′ in the user area 25 corresponds to the third partial redundancy area 26 ′ of the redundancy area 26.

  Next, the controller 3 that controls access to the flash memory 2 will be described. The controller 3 performs various processes such as a read process, a write process, and a block erase process by supplying data, address information, internal commands, and the like to the flash memory 2.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. On the other hand, a command given from the host system 4 to the controller 3 is called an external command.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads out a command set (hereinafter referred to as a sequence command) defining various processes from the ROM 12, and causes the flash memory interface block 10 to execute processes according to the sequence command.

The ROM 12 is a non-volatile storage element and stores the above sequence commands and the like.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells. The above address conversion table is created on this work area 8.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The host interface block 7 exchanges data, address information, external commands and the like with the host system 4. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14.

  The host interface block 7 and the flash memory interface block 10 include various registers as shown in FIG. The host interface block 7 includes a command register R1, a sector number register R2, an LBA register R3, and the like. The flash memory interface block 10 includes a physical block address register R11, a sector number register R12, a counter R13, and a write mark register R14. And an end mark register R15.

  Information given from the host system 4 is written in the command register R1, the sector number register R2, and the LBA register R3. External commands such as a write command and a read command are written in the command register R1. In the LBA register R3, the head LBA of the access target area is written. The number of sectors in the access target area is written in the sector number register R2.

  Information indicating the access target area in the flash memory 2 is written in the physical block address register R11, the sector number register R12, and the counter R13 based on the information written in the sector number register R2 and the LBA register R3.

  When the access target area in the flash memory 2 is specified, the access target LBN and SN are specified based on the LBA set in the LBA register R3.

  For example, if an area of 256 sectors with consecutive LBAs is allocated to one physical block in flash memory (one block has 64 pages and one page has 4 sectors), as shown in FIG. The lower 8 bits correspond to SN, and the upper bits excluding the lower 8 bits correspond to LBN. That is, when an area of 256 sectors with continuous LBA is a logical block, the lower 8 bits of the LBA indicate the sector number SN (0 to 255) which is a serial number assigned to each sector in the logical block. The upper bits excluding 8 bits indicate LBN. Note that the number of bits of LBA, LBN, and SN is determined according to the capacity and specifications of the flash memory.

  Subsequently, based on the access-target LBN and SN, information indicating the access target area is set in the physical block address register R11 and the sector number register R12.

  In the physical block address register R11, the PBA of the physical block corresponding to the logical block specified based on the portion indicating the LBN of the LBA written in the LBA register R3 or the PBA of the empty block is written. That is, when reading user data from the physical block corresponding to the specified logical block, or when additional writing is performed on the block, the PBA of the physical block corresponding to the specified logical block is the physical block address register R11. When the user data corresponding to the specified logical block is written into the empty block, the PBA of the empty block is written into the physical block address register R11.

  In the sector number register R12, a portion corresponding to the SN of the LBA written in the LBA register R3 is written. Here, since user data is written in each physical block in the order of LBA, the SN corresponds to a serial number assigned to the sector area 25 ′ included in each physical block. Since the user area 25 of each page is composed of four sector areas 25 ′, the upper 6 bits of SN correspond to the page number PN (0 to 63) in the physical block, and the lower 2 bits of SN. Corresponds to the in-page sector number PISN (0 to 3) indicating the order of the sector area 25 ′ included in the user area 25.

  In the counter R13, the number of sectors of a series of user data written in the physical block specified by the PBA set in the physical block address register R11 is written. Therefore, when the access target area specified based on the information written in the sector number register R2 and the LBA register R3 does not extend over a plurality of physical blocks, the sector number set in the sector number register R2 is stored in the counter R13. Written.

  When the access target area specified based on the LBA register R3 and the sector count register R2 extends over a plurality of logical blocks, the physical block of the access target area also extends over a plurality of physical blocks. Information setting for the register R11, the sector number register R12, and the counter R13 is performed for each logical block. Therefore, when the access target area specified based on the LBA register R3 and the sector number register R2 extends over a plurality of logical blocks, it is set a plurality of times (for example, 2 based on one write command given from the host system 4). The sequence write process is executed twice if the logical block is straddled.

  In the case of the writing process, a write mark and an end mark written to the partial redundancy area 26 'are set in the write mark register R14 and the end mark register R15, respectively.

In the present embodiment, the write mark is 8 bits and the end mark is 4 bits. The setting of the writing mark is changed as follows depending on the number of sequential writing processes for the physical block.
Write mark at the time of the first sequence writing process: 00h (hexadecimal notation)
Write mark at the time of the second sequence write process: 05h (hexadecimal notation)
Write mark at the time of the third sequence writing process: 0 Ah (hexadecimal notation)
Write mark at the time of the fourth sequence write process: 0Fh (hexadecimal notation)
Write mark at the time of the fifth sequence writing process: 50h (hexadecimal notation)
Write mark at the time of 6th sequence write processing: 55h (hexadecimal notation)
Write mark at the time of the seventh sequence writing process: 5 Ah (hexadecimal notation)
Write mark for the 8th sequence write process: 5Fh (hexadecimal notation)
Write mark at the time of the 9th sequence writing process: A0h (hexadecimal notation)
Write mark for the 10th sequence write process: A5h (hexadecimal notation)
Write mark for the 11th sequence write process: AAh (hexadecimal notation)
Write mark for the 12th sequence writing process: AFh (hexadecimal notation)
Write mark for the 13th sequence writing process: F0h (hexadecimal notation)
Write mark for the 14th sequence writing process: F5h (hexadecimal notation)
Write mark for the 15th and subsequent sequence write processes: FAh (hexadecimal notation)

  For example, when the ninth sequence write process is performed on a physical block that has already been subjected to the sequence write process eight times, A0h (hexadecimal notation) is written in the write mark register R14, and Fh is written in the end mark register R15. After setting (hexadecimal notation), the sequence writing process is executed. When the sequence writing process is executed, based on information set in the physical block address register R11 and the sector number register R12, physical address information for specifying a user data write destination page, and sectors in the write destination page Information specifying the area 25 ′ is supplied to the flash memory 2. Further, user data to be written to the sector area 25 ′ is supplied from the buffer 9, and a write mark and an end mark to be written to the partial redundancy area 26 ′ are respectively supplied from the write mark register R14 and the end mark register R15. . Here, the physical address information for specifying the page to be written is generated based on the PBA set in the physical block address register R11 and the upper 6 bits of SN set in the sector number register R12. The information specifying the sector area 25 ′ is generated based on the lower 2 bits of SN.

  Each time user data of one sector is supplied from the buffer 9 to the flash memory 2, the value set in the sector number register R12 is incremented (incremented by 1), and the value set in the counter R13 is decremented (by 1). Reduced). When the value set in the counter R13 becomes 1, 0h (hexadecimal notation) is set in the end mark register R15, and when the value set in the counter R13 becomes 0, the sequence writing process is performed. finish. For example, when “8” is set in the counter R13 and the sequence writing process is started, user data of 8 sectors is written, and partial redundancy corresponding to the sector area 25 ′ in which user data of the 8th sector is written. In the area 26 ', 0h (hexadecimal notation) is written as the end mark.

  That is, in the sequence write process, the PBA of the write destination physical block is written to the physical block address register R11, the SN corresponding to the sector area 25 ′ to start writing is written to the sector number register R12, and the user data to be written to the counter R13 is written. Write the number of sectors, write a write mark to the write mark register R14, write Fh (hexadecimal notation) to the end mark register R15, and write user data for the number of sectors written to the counter R13. And finish.

  The write mark is composed of a combination (excluding FFh) of 0h, 5h, Ah and Fh (hexadecimal notation) in consideration of the occurrence of a bit error. If the portion of the partial redundancy area 26 'where the write mark is written is FFh (erased), it is determined that the write mark is not written.

  In the present embodiment, it is determined based on the write mark whether or not user data of 256 sector areas 25 ′ included in each physical block is stored, and the last sector area in which user data is stored It is determined whether or not the sequence writing process has been completed normally based on whether or not an end mark has been written in the partial redundancy area 26 ′ corresponding to 25 ′.

  Further, when no end mark is written in the partial redundancy area 26 'corresponding to the last sector area 25' in which user data is stored, normal data and abnormal data are discriminated. In this determination, the last partial redundancy in which the write mark immediately before the write mark written in the partial redundancy area 26 ′ corresponding to the last sector area 25 ′ in which user data is stored is written. The area 26 'is detected, and the user data stored up to the sector area 25' corresponding to the partial redundancy area 26 'is determined as normal data. However, since the same write mark FAh (hexadecimal notation) is written in the 15th and subsequent sequential write processes, the write mark is written in the partial redundant area 26 ′ corresponding to the last sector area 25 ′ in which user data is stored. When FAh (hexadecimal notation) is written, the user data written up to the sector area 25 ′ corresponding to the tail partial redundant area 26 ′ where the end mark is written is determined as normal data. The user data determined to be normal data is transferred (copied) to another erased physical block, and the stored data of the physical block in which normal data and abnormal data coexist after the transfer are deleted.

  Further, when the end mark is not written in the partial redundant area 26 ′ corresponding to the last sector area 25 ′ in which the user data is written, the write mark written in the partial redundant area 26 ′ is If it is the write mark 00h (hexadecimal notation) indicating the first sequence write process, it is determined that there is no normal data in the physical block. Note that the storage data of the physical block determined to have no normal data is erased.

  Next, processing for detecting the last sector area 25 ′ in which user data is written with reference to the write mark written in the partial redundancy area 26 ′ will be described with reference to FIG. 6. In the following description, the partial redundancy area 26 'is assumed to have the same SN as the corresponding sector area 25'. That is, the SN of the partial redundancy area 26 ′ corresponding to the sector area 25 ′ with SN “0” is “0”, and the SN of the partial redundancy area 26 ′ corresponding to the sector area 25 ′ with SN “1” is “ In the same manner, the SN of the partial redundancy area 26 ′ corresponding to the sector area 25 ′ of SN “255” is set to “255”.

  First, 0 (binary notation: 0000 0000), which is the SN of the first partial redundancy area 26 ', is set as the first sector number SS of the search range (step S51).

  Subsequently, 256 (binary notation: 1 0000 0000) obtained by adding 1 to the SN of the final partial redundant area 26 'is set as the final sector number ES of the search range (step S52).

Next, the SN value n of the partial redundant area 26 ′ to be referred to is calculated (step S53). This value n is obtained by the following equation.
n = (SS + ES) / 2
In other words, this value n is obtained by adding SS and ES and then shifting by 1 bit in the lower direction (deleting the least significant bit).

  Next, with reference to the partial redundancy area 26 'whose SN matches n obtained in step S53, it is determined whether or not a write mark is written in the referenced partial redundancy area 26' (step S54). That is, if the write mark is any one of 00h (hexadecimal notation) to FAh (hexadecimal notation), it is determined that the write mark is written, and the write mark is FFh (hexadecimal notation). In this case, it is determined that the write mark is not written.

  When a write mark is written in the referenced partial redundant area 26 ′ (step S54: Yes), the last partial redundant area 26 ′ in which the write mark is written is before the referenced partial redundant area 26 ′. Therefore, the head sector number SS is changed to the value of n obtained in step S53 (step S55).

  When the write mark is not written in the referenced partial redundant area 26 '(step S54: No), the last partial redundant area 26' in which the write mark is written is after the referenced partial redundant area 26 '. Therefore, the final sector number ES is changed to the value of n obtained in step S53 (step S56). Next, the head sector number SS and the last sector number ES are compared to determine whether or not the difference between the head sector number SS and the last sector number ES is greater than “1” (step S57). When the difference between the first sector number SS and the last sector number ES is larger than “1” (step S57: Yes), the process returns to step S53, and the SN value n of the partial redundant area 26 ′ to be referred to next is calculated. On the other hand, when the difference between the first sector number SS and the last sector number ES is “1” (step S57: No), the value set in the first sector number SS is the last part where the write mark is written. The detection process is terminated by determining the SN of the redundant area 26 '.

  If the end mark 0h (hexadecimal notation) is written in the tail partial redundant area 26 ′ where the write mark detected in this way is written, it is determined that the previous sequence writing process has ended normally. To do. On the other hand, when the end mark 0h (hexadecimal notation) has not been written in the tail partial redundant area 26 'where the write mark is written, it is determined that the previous sequence writing process has not ended normally.

  Next, when it is determined that the previous sequence writing process has not ended normally, a process for determining normal data written in the sequence writing process prior to the previous sequence writing process is performed. However, if the write mark written in the previous sequence write process that was determined not to have ended normally is the write mark 00h (hexadecimal notation) indicating the first sequence write process, the physical block Therefore, it is determined that there is no normal data, and processing for determining normal data is not performed.

  If the write mark written in the previous sequence write process that was determined not to have ended normally is FAh (hexadecimal notation), the part before the last partial redundant area 26 'where the write mark is written The redundant area 26 ′ is sequentially referred to, and the last partial redundant area 26 ′ in which the end mark is written is detected. The user data written up to the sector area 25 ′ corresponding to the partial redundancy area 26 ′ thus detected is determined as normal data. For example, reference is made in the order of a partial redundancy area 26 ′ with SN 243, a partial redundancy area 26 ′ with SN 242, a partial redundancy area 26 ′ with SN 241, and a partial redundancy area 26 ′ with SN 243 to 238. If there is no end mark and there is an end mark in the partial redundancy area 26 'with SN 237, the user data stored in the sector area 25' with SN 0 to 237 is determined as normal data.

  If the writing mark written in the previous sequence writing process that was determined not to have ended normally is a writing mark indicating the 2nd to 14th sequence writing processes, the writing mark written in the previous sequence writing process The user data written up to the sector area 25 ′ corresponding to the partial redundant area 26 ′ in which both the write mark and the end mark immediately before the embedded mark are written is determined as normal data. A process for detecting the partial redundancy area 26 ′ in which both the write mark one before the write mark written in the previous sequential write process and the end mark are written, that is, normal data is stored. Processing for detecting the last sector area 25 ′ will be described with reference to FIG.

  First, 0 is set as the SN of the first partial redundancy area 26 'as the first sector number SS of the search range (step S61).

  Subsequently, the SN value of the last partial redundant area 26 'where the write mark is written is set as the final sector number ES of the search range. Further, a write mark written in the last partial redundant area 26 'where the write mark is written is set as the final write mark EM. (Step S62). In other words, the last write mark EM is set with the write mark written in the previous sequence writing process that is determined not to have ended normally.

Next, the SN value n of the partial redundant area 26 ′ to be referred to is calculated (step S63). This value n is obtained by the following equation.
n = (SS + ES) / 2
In other words, this value n is obtained by adding SS and ES and then shifting by 1 bit in the lower direction (deleting the least significant bit).

  Next, the SN refers to the partial redundancy area 26 ′ that matches n obtained in step S63, and is set as the write mark written in the referenced partial redundancy area 26 ′ and the final write mark EM. Write marks are compared (step S64).

  If the write mark written in the referenced partial redundancy area 26 'is the same as the write mark set as the final write mark EM (step S64: Yes), it is set as the final write mark EM. Since the partial redundant area 26 ′ in which the write mark immediately before the write mark is written is not after the referenced partial redundant area 26 ′, the final sector number ES is changed to the value of n obtained in step S63. (Step S65). After changing the last sector number ES, the process returns to step S63 and the SN value n of the partial redundant area 26 'to be referred to is calculated again.

  When the write mark written in the referenced partial redundant area 26 ′ is different from the write mark set as the final write mark EM (step S64: No), that is, in the referenced partial redundant area 26 ′. When the written mark being written is one or more write marks before the write mark set as the final write mark EM, the write mark set as the final write mark EM is 1 Since the partial redundant area 26 ′ in which the previous write mark and end mark are written does not precede the referenced partial redundant area 26 ′, the head sector number SS is changed to the value of n obtained in step S 63. (Step S66).

  Subsequently, the write mark written in the referenced partial redundancy area 26 'is compared with the write mark immediately before the write mark set as the final write mark EM (step S67).

  When the write mark written in the referenced partial redundancy area 26 ′ is different from the write mark immediately before the write mark set as the final write mark EM (step S67: No), that is, If the write mark written in the referenced partial redundancy area 26 'is a write mark two or more prior to the write mark set as the final write mark EM, the process returns to step S63 for reference The SN value n of the redundant area 26 ′ is calculated again.

  When the write mark written in the referenced partial redundancy area 26 ′ is the same as the write mark immediately before the write mark set as the final write mark EM (step S67: Yes), the reference is made It is determined whether or not an end mark is written in the partial redundancy area 26 '(step S68).

  When the end mark is not written in the referenced partial redundant area 26 '(step S68: No), the process returns to step S63 to recalculate the SN value n of the referenced partial redundant area 26'.

  When the end mark is written in the referred partial redundant area 26 ′ (step S68: Yes), the value set in the head sector number SS is the SN of the last sector area 25 ′ in which normal data is stored. And the detection process is terminated.

  Next, processing for discriminating between normal data and abnormal data will be described based on a specific example. For example, as shown in FIG. 8, a case where a writing mark and an end mark are written will be described.

  In this example, the SN of the last partial redundant area 26 ′ where the write mark is written is 25, and the end mark indicating that the sequence writing process has been normally completed in the partial redundant area 26 ′ with SN 25 0h (hexadecimal notation) is not written. Therefore, it is determined that the previous sequence writing process did not end normally.

  Here, since the write mark written in the partial redundancy area 26 'with SN of 25 is 0Ah (hexadecimal notation), the write mark 05h (hexadecimal notation) immediately before 0Ah (hexadecimal notation) It is determined that the SN of the partial redundancy area 26 ′ in which the end mark 0h (hexadecimal notation) is written is the SN of the last sector area 25 ′ in which normal data is stored. That is, it is determined that the user data stored in the sector area 25 ′ whose SN is 0 to 17 is normal data.

Next, a case where a write mark and an end mark are written as shown in FIG. 9 will be described.
In this example, the SN of the last partial redundant area 26 ′ in which the write mark is written is 7, and the end mark indicating that the sequence write process has been normally completed in the partial redundant area 26 ′ with SN 7 0h (hexadecimal notation) is not written. Therefore, it is determined that the previous sequence writing process did not end normally.

  Here, since the write mark written in the partial redundancy area 26 'with SN 7 is 00h (hexadecimal notation) indicating the first sequence write processing for this physical block, normal data is stored in this physical block. Judge that it is not memorized.

  As described above, the same write mark is written in the partial redundancy area 26 ′ corresponding to the sector area 25 ′ in which a series of data is written in each sequence writing process, and the user data at the end of the series of data is written. By writing an end mark in the partial redundancy area 26 ′ corresponding to the area 25 ′, it is possible to easily determine whether or not an abnormal end has occurred and to distinguish between normal data and abnormal data.

  Note that the number of bits of the write mark, the bit pattern, and the type of the bit pattern can be set as appropriate. The type of bit pattern of the write mark is preferably made different for each sequence writing process, but may be determined as appropriate in consideration of the average number of times of sequential writing process for the same physical block. or. The number of bits and the bit pattern of the end mark can also be set as appropriate.

  Further, the configuration of the flash memory, for example, the number of sector areas 25 ′ included in each physical block can be implemented without any particular limitation. The access method and address management method for the flash memory can also be implemented without particular limitation.

1 is a block diagram schematically showing a flash memory system according to an embodiment of the present invention. It is a figure which shows roughly the structure of the address space of the flash memory of embodiment of this invention. It is a figure which shows the structural example of a user area | region and a redundant area. It is a block diagram which shows the structure of a host interface block and a flash memory interface block. It is a figure for demonstrating the structure of the logical address information LBA. It is a flowchart for demonstrating the process which detects the sector area of the end in which user data is written. It is a flowchart for demonstrating the process which detects the sector area of the end where normal data is memorize | stored. It is a figure which shows the example of the write mark and end mark which were written in the physical block. It is a figure which shows the example of the write mark and end mark which were written in the physical block.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area

Claims (2)

In response to a command from a host system, a memory controller that controls access to a flash memory in which a user area of each page included in a physical block includes one or more sector areas,
In response to a data write command from the host system, i) a series of data is sequentially written in the sector area, and ii) data is written in a redundant area corresponding to the sector area in which the series of data is written. Iii) writing means for writing an end mark indicating that end data of a series of data is written in a redundant area corresponding to the sector area in which end data of the series of data is written; ,
Abnormal end detection means for detecting that the writing of the series of data did not end normally based on the writing mark and the end mark;
Normal data detection means for detecting the end of a sector area in which the series of data is normally written based on the write mark and the end mark;
Equipped with a,
The write mark includes order information indicating what number of series of data written in the physical block,
Information indicating that the order information corresponding to the series of data that has not been normally written indicates the first when the abnormal end detection means detects that the series of data has not been written normally. The normal data detection means does not perform the process of detecting the end of the sector area in which the series of data is normally written, and determines that there is no series of data that is normally written.
A memory controller characterized by that. A flash memory system comprising the memory controller according to claim 1 and a flash memory.

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