JP2005292926A - Memory controller, flash memory system, and control method for flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine whether or not writing to consecutive pages of a flash memory has been completed even if the writing is interrupted. <P>SOLUTION: When data are written to consecutive pages P0 to P31 of the flash memory, (01011) and (11000) are set in redundant areas of writing start pages P0 and P11 as end point information corresponding to writing end pages, and (01011) and (11000) are set in redundant areas of the writing end pages P10 and P23 as writing completion information. If the writing is interrupted, (01011) and (11000) are not set as the writing completion information, so that, for example, a check on the redundant areas of the writing end pages P10 and P23 can determine whether or not the writing has been completed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of non-volatile memory, and data stored in the flash memory is required to be held even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored.

In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”.
The writing process or the reading process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  In a memory system using a NAND flash memory, the writing process may be interrupted due to a sudden power interruption or the like. In such a case, incomplete write data is left in the NAND flash memory. After that, when the power is turned on, it may be difficult to discriminate between such incomplete write data and normal write data.

In order to solve such a problem, in Patent Document 1 below, an invalid flag is provided in the first page (redundant area) of each block, and an valid flag is provided in the last page (redundant area), and the writing process is normally completed. In some cases, the setting process for enabling the valid flag is performed, and the setting process for enabling the invalid flag is performed when the data of the block becomes unnecessary. In this way, it is possible to determine whether the writing process has been normally completed or has been interrupted depending on whether or not the valid flag is set to be valid.
JP 2003-15929 A

  In Patent Document 1 (Japanese Patent Laid-Open No. 2003-15929), a setting process is performed in which the validity flag is valid when data is written to all pages in the block. However, data is written to all pages in the block. In some cases, the process may be terminated without being included. For example, in the first process, data may be written to some pages in the block to end the process, and the continuation may be written in the next process. In such a case, when the process of writing data to a part of the pages in the block ends normally, the setting process for enabling the valid flag is not performed. Therefore, it cannot be determined whether the process has been completed normally.

  Therefore, the present invention provides a memory controller that can determine whether or not the process has been performed normally even in the case of a process of writing data to some pages in a block, and a flash memory system including the memory controller, It is another object of the present invention to provide a flash memory control method.

  In order to achieve the above object, the memory controller according to the first aspect of the present invention continuously writes data to a plurality of consecutive pages belonging to the same block in the flash memory based on a request from the host system side. A write function, an end point information setting function for setting end point information indicating a write end page in the redundant area of the write start page of the plurality of pages, and a write area in the redundant area of the write end page of the plurality of pages. And a process completion information setting function for setting process completion information indicating that the writing process for the inclusion end page has been completed.

Note that the same information as the end point information may be used as the processing completion information.
The end point information may be set in a redundant area of all pages from the write start page to the write end page of the plurality of pages.

  In order to achieve the above object, a flash memory system according to a second aspect of the present invention comprises a memory controller according to the first aspect of the present invention and a flash memory.

  In order to achieve the above object, a flash memory control method according to a third aspect of the present invention provides data to a plurality of consecutive pages belonging to the same block in the flash memory based on a request from the host system side. A continuous writing process for writing, an end point information setting process for setting end point information indicating a write end page in the redundant area of the write start page of the plurality of pages, and a redundant area of the write end page of the plurality of pages. And a process completion information setting process for setting process completion information indicating that the writing process for the writing end page has been completed.

Note that the same information as the end point information may be used as the processing completion information.
The end point information may be set in a redundant area of all pages from the write start page to the write end page of the plurality of pages.

  According to the present invention, when data is written to a plurality of continuous pages belonging to the same block in the flash memory on the basis of a request from the host system side, in the redundant area of the write start page of the write process, End point information indicating the write end page is set, and process completion information indicating that the write process for the write end page is completed is set in the redundant area of the write end page. By doing so, the end point information set in the redundant area of the writing start page and the processing completion information set in the redundant area of the writing end page are determined depending on whether or not the writing is completed. It can be determined whether the process has been performed normally.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention.

  As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller (hereinafter simply referred to as a controller) 3 that controls the flash memory 2. The flash memory system 1 is normally used by being detachably attached to the host system 4 and used as a kind of external storage device for the host system 4.

  Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.

  The flash memory 2 is a device that executes reading or writing in units of pages and erasing in units of blocks. For example, one block is composed of 32 pages, and one page is a 512-byte user area and a 16-byte redundant area. It is configured.

  The controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, And a flash memory sequencer block 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. The function of each block will be described below.

The microprocessor 6 is a functional block that controls the operation of the entire functional blocks constituting the controller 3.
The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4.
That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13, and in this state, the host system 4 connects to the flash memory system 1. The supplied data and the like are taken into the controller 3 through the host interface block 7 as an entrance. Data or the like supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  Further, the host interface block 7 includes a task file register (not shown) for temporarily storing a host address and an external command supplied from the host system 4 and an error register (not shown) set when an error occurs. ) Etc.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is a functional block configured by a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive data, and data to be written into the flash memory 2 is held in the buffer 9 until the flash memory 2 is ready to write. The

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on internal commands. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information. Here, the “internal command” is a command given from the controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code to be added to data to be written to the flash memory 2, and detects and corrects errors included in the read data based on the error correction code added to the read data. Function block.

[Description of flash memory 2]
The flash memory 2 is a NAND flash memory, and is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). The NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the flash memory 2 has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data ( A process of erasing the block in which the data before rewriting) has been written is performed.

  When such data rewriting is performed, the data after rewriting is written in a block different from that before rewriting. Therefore, the logical block address based on the address given from the host system 4 side and the flash memory 2 The correspondence relationship with the physical block address, which is a block address, dynamically changes every time data is rewritten. The correspondence between the logical block address and the physical block address is normally managed by an address conversion table indicating the correspondence, and the address conversion table is created based on a corresponding logical block address described later.

Here, the relationship between the block and the page will be described with reference to FIG.
2A and 2B are explanatory diagrams for explaining the relationship between blocks and pages.
The relationship between the block and the page in the flash memory differs depending on the specification of the flash memory, but in a general flash memory, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31), Each page includes a 512-byte user area and a 16-byte redundant area.

As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.
The user area is mainly an area for storing data supplied from the host system 4, and the redundant area is an area for storing additional data such as an error correction code, a corresponding logical block address and a block status. is there. The error collection code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an external ECC block. The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block.

  If no data is stored in the block, the corresponding logical block address is not stored. Therefore, whether or not the block is an erased block depends on whether or not the corresponding logical block address is stored. It can also be judged. That is, if the corresponding logical block address is not stored, it is determined that the block is an erased block. The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  Next, the circuit configuration of the flash memory 2 will be described. The flash memory 2 includes a register for holding write data or read data and a memory cell array for storing data, as in a general NAND flash memory.

  The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from the register to the memory cell or copying from the memory cell to the register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate and the lower gate is called a floating gate. Data is written by injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate. Or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When electrons are injected into the floating gate, a high voltage is applied so that the control gate is on the high potential side. When electrons are injected from the floating gate, electrons are injected on the floating gate. A voltage is applied to discharge electrons. Here, the state in which electrons are injected into the floating gate (write state) corresponds to the data of the logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) is the logical value. Corresponds to the data of “1”.

[Description of operation]
In the flash memory system 1, when a write process for writing data to a plurality of continuous pages belonging to the same block in the flash memory 2 is performed based on a request from the host system 4, the write process is performed. End point information indicating the writing end page is set in the redundant area of the start page, and processing completion information indicating that the writing process for the writing end page is completed is set in the redundant area of the writing end page. To do. The end point information and processing completion information will be described below with reference to the drawings.

FIG. 3 is a diagram showing an example of end point information and processing completion information set in a redundant area of a page in the flash memory 2.
In FIG. 3, the writing process in steps 1 to 3 is performed on a block composed of 32 pages. For example, in step 1, data is written in the user area of pages 0 to 10 (11 pages P0 to P10), and in step 2, users of pages 11 to 23 (13 pages P11 to P23) are written. Data is written in the area, and in step 3, data is written in the user area of pages 24-31 (eight pages P24-P31).

  When data is written in the user area of each page, information corresponding to end point information or processing completion information is set in the redundant area. In the writing process in step 1, the next writing process (step 2) writes to all redundant areas from page 0 (P0), which is the writing start page, to page 10 (P10), which is the writing end page. 11 (binary number 01011b), which is the page number of the page on which is started. This 11 (binary number 01011b) is a value obtained by adding the number of pages to be written to the write start page, and corresponds to the write end page.

As in step 1, in the write process in step 2, the next write process (in the redundant area from page 11 (P11) as the write start page to page 23 (P23) as the write end page) In step 3), 24 (binary number 11000b), which is the page number where writing starts, is set.
In the write process in step 3, since data is written up to page 31 (P31) which is the last page of this block, page 24 (P24) which is the write start page to page 31 (P31) which is the write end page. ) Is set to 0 (binary number 00000b) in all the redundant areas up to. Here, when the writing end page of the writing process is the last page of the block, 0 (binary 00000b) is set as the page number where writing is started in the next writing process.

In this example, the page number where writing is started in the next writing process is used as the information corresponding to the end point information, and the writing corresponding to the processing completion information is also started in the next writing process. The page number is used.
In this case, the page number immediately before the page number set in the redundant area of the write start page corresponds to the write end page, so the page number set in the redundant area of the write start page If the same page number as the writing start page is set in the redundant area of the previous page, it can be determined that the writing process from the writing start page to the writing end page has been performed normally. .

  That is, if 11 (binary 01011b) is set in the redundant area of page 0 (P0), which is the write start page of step 1, in step 1, page 10 (P10) is written in step 1 Since it corresponds to the end page, if 11 (binary 01011b) is set in the redundant area of page 10 (P10), it can be determined that the writing process of step 1 has been performed normally. In step 2, if 24 (binary number 11000b) is set in the redundant area of page 11 (P11) which is the write start page of step 2, page 23 (P23) is the write end page of step 2 Therefore, if 24 (binary 11000b) is set in the redundant area of page 23 (P23), it can be determined that the writing process of step 2 has been performed normally.

  If 0 (binary 00000b) is set in the redundant area of page 24 (P24) which is the write start page of step 3 in step 3, page 31 (P31) is the write end page of step 3 Therefore, if 0 (binary number 00000b) is set in the redundant area of page 31 (P31), it is determined that the writing process in step 3 has been performed normally.

Next, a case where the writing process is interrupted will be described with reference to FIG.
FIG. 4 is a diagram showing a redundant area setting state (part 1) when the process is interrupted during the writing process.
In the writing process of step 2, data is written in the user area of pages 11 to 23 (P11 to P23), so that the page of which writing is started in the next writing process in the redundant area of pages 11 to 23 is written. The number 24 (binary 11000b) is set. Here, since the writing process for the user area and the writing process for the redundant area proceed simultaneously, when the writing process for the user area is interrupted, the writing process for the redundant area is similarly interrupted.

  In the example shown in FIG. 4, 24 (binary number 11000b), which is the page number where writing is started in the next writing process, is set in the redundant areas of pages 11 to 19 (P11 to P19). However, 24 (binary 11000b) is not set in the redundant areas of pages 20 to 23 (P20 to P23). Therefore, it can be determined that the writing process in step 2 is interrupted after the writing process for page 19 (P19) is completed. That is, if the process completion information is set in the redundant areas of pages other than the write end page, the progress of the process when the write process is interrupted can be detected.

  In the example of FIG. 3, the same value is set for all the redundant areas from the writing start page to the writing end page, but the redundant area of the page existing between the writing start page and the writing end page is set. May be configured not to set end point information or processing completion information (see FIG. 5).

FIG. 5 is a diagram showing a redundant area setting state (part 2) when the process is interrupted during the writing process.
In the example of FIG. 5, the processing completion information is not set in the redundant areas of pages other than the write end page (binary number 11111b). In this case, the progress of the process when the writing process is interrupted cannot be detected, but it can be determined whether or not the writing process has ended normally.

  That is, in the redundant area of page 11 (P11) which is the write start page of the write process in step 2, 24 (binary number 11000b) which is the page number where writing is started in the next write process is performed. Although it is set, 24 (binary number 11000b) is not set as the processing completion information in the redundant area of page 23 (P23) which is the writing end page. It can be determined that it has been interrupted.

  3 to 5, the end point information set in the redundant area of the write start page and the processing completion information set in the redundant area of the write end page have been described as being the same. The completion information may be different. Examples thereof will be described with reference to FIGS.

FIG. 6 is a diagram showing another example of the end point information and the processing completion information set in the page redundancy area in the flash memory.
In the example shown in FIG. 6, the page number where writing is started in the next writing process is used as information corresponding to the end point information, and 0 (binary number) is stored in the redundant area as information corresponding to the processing completion information. 00000b) is set, and data is written in the redundant areas of all pages up to the write end page except the write start page. In this case, if (binary number 00000b) is set in the redundant area of the previous page of the page number set in the redundant area of the writing start page, writing ends from the writing start page. It can be determined that the writing process up to the page has been performed normally.

  That is, if 11 (binary 01011b) is set in the redundant area of page 0 (P0) which is the write start page of step 1 in step 1, 0 (in the redundant area of page 10 (P10)) If the binary number 00000b) is set, it can be determined that the writing process in step 1 has been performed normally.

  In step 2, if 24 (binary number 11000b) is set in the redundant area of page 11 (P11) which is the write start page in step 2, 0 (binary number) is set in the redundant area of page 23 (P23). 00000b) is set, it can be determined that the writing process in step 2 has been performed normally.

  In step 3, if 0 (binary number 00000b) is set in the redundant area of page 24 (P24) that is the write start page in step 3, 0 (binary number) is set in the redundant area of page 31 (P31). 00000b) is set, it can be determined that the writing process in step 3 has been performed normally.

FIG. 7 is a diagram showing a redundant area setting state (part 3) when the process is interrupted during the writing process.
If the write processing in step 2 in FIG. 7 was to write data to the user area of pages 11 to 23 (P11 to P23), but the processing is interrupted when the writing of page 20 is completed, the page 0 (binary number 00000b) is set in the redundant area of 12 to 20 (P12 to P20), but 0 (binary number 00000b) is set in the redundant area of pages 21 to 23 (P21 to P23). Is not set. Therefore, it can be determined that the writing process in step 2 is interrupted after the writing process for page 20 (P20) is completed. That is, if the process completion information is set in the redundant areas of pages other than the write end page, the progress of the process when the write process is interrupted can be detected.

  In the example of FIG. 6, the same value is set for all the redundant areas up to the write end page except the write start page. However, the redundancy of the page existing between the write start page and the write end page is set. The area may be configured not to set end point information or processing completion information (see FIG. 8).

FIG. 8 is a diagram showing a redundant area setting state (part 4) when the process is interrupted during the writing process.
As shown in FIG. 8, processing completion information is not set in the redundant areas of pages other than the write end page. In this case, the progress of the process when the writing process is interrupted cannot be detected, but it can be determined whether or not the writing process has ended normally.

  That is, in the redundant area of page 11 (P11) which is the write start page of the write process in step 2, 24 (binary number 11000b) which is the page number where writing is started in the next write process is performed. Although it is set, 0 (binary number 00000b) is not set as the processing completion information in the redundant area of page 23 (P23) which is the writing end page. It can be determined that it has been interrupted.

  In the above description, the page number at which writing is started in the next writing process is used as the end point information. However, the end point information is information indicating the write end page directly or indirectly. Other information may be used. For example, the write end page number or the like may be used as the end point information. The processing completion information is not limited to the above example, and the number of the write end page may be used.

1 is a block diagram schematically showing a flash memory system according to the present invention. It is explanatory drawing explaining the relationship between a block and a page. It is a figure which shows an example of the end point information set to the redundant area | region of the page in flash memory, and process completion information. It is a figure which shows the setting state (the 1) of a redundant area when a process is interrupted during a writing process. It is a figure which shows the setting state (the 2) of a redundant area when a process is interrupted during a writing process. It is a figure which shows the other example of the end point information set in the redundant area | region of the page in flash memory, and process completion information. It is a figure which shows the setting state (the 3) of a redundant area when a process is interrupted during a write process. It is a figure which shows the setting state (the 4) of a redundant area when a process is interrupted during a write process.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system

Claims (7)

Based on a request from the host system side, a continuous writing function for writing data to a plurality of continuous pages belonging to the same block in the flash memory,
An end point information setting function for setting end point information indicating a write end page in a redundant area of the write start page of the plurality of pages;
A process completion information setting function for setting process completion information indicating that the writing process for the write end page is completed in the redundant area of the write end page of the plurality of pages;
A memory controller comprising:   The memory controller according to claim 1, wherein the same information as the end point information is used as the processing completion information.   3. The memory controller according to claim 1, wherein the end point information is set in a redundant area of all pages from the write start page to the write end page of the plurality of pages.   A flash memory system comprising the memory controller according to any one of claims 1 to 3 and a flash memory. Based on a request from the host system side, a continuous writing process for writing data to a plurality of continuous pages belonging to the same block in the flash memory;
End point information setting processing for setting end point information indicating a write end page in the redundant area of the write start page of the plurality of pages;
A process completion information setting process for setting process completion information indicating that the write process for the write end page is completed in the redundant area of the write end page of the plurality of pages;
A method for controlling a flash memory, comprising:   6. The flash memory control method according to claim 5, wherein the same information as the end point information is used as the processing completion information. 7. The flash memory control method according to claim 5, wherein the end point information is set in a redundant area of all pages from the write start page to the write end page of the plurality of pages.

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