JP2006221334A - Memory controller, flash memory system, and control method for flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flash memory system for suppressing the deterioration of a flash memory when using an error correction code whose error correcting capability is high. <P>SOLUTION: User data read from a flash memory 2 are inputted to an error correction coder/decoder 24, and an error correction code read from the redundant region of the flash memory 2 is inputted through a mask circuit 25 to the error correction coder/decoder 24. The error correction coder/encoder 24 performs the error detection and correction of user data on the basis of the error correction code, and provides user data to a buffer 9. Then, only when the number of errors of user data exceeds a set value, the user data of the flash memory 2 are rewritten to correct user data. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory has a logical value “0” from an erased state in which data indicating the logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored. In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”.

  The writing process or the reading process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  In the writing process to the NAND flash memory, first, write data is transferred to a register in the NAND flash memory, and the write data held in the register is copied to the memory cell array. When the memory cell is changed from the erased state to the written state by this copying (writing) process, a high voltage is applied to the control gate and electrons are injected to the floating gate. Since data is written into the memory cell array by such processing, a write error may occur in the write processing to the NAND flash memory.

  An error in read data due to a write error or the like is usually detected and corrected based on an error correction code written in a redundant area of each page. This error correction code is generated based on the data written in the user area of each page during the writing process, and is written in the redundant area of each page.

  As error correction codes for detecting and correcting data errors, Reed-Solomon codes, BCH codes, Hamming codes, and the like are known. The Hamming code does not have a high error correction capability, but error correction is generated based on the write data when all the bit data of the write data to be written in the user area is a logical value “1” (erased state). Since all the bit data of the code matches the logical value “1” (erased state), it is often used as an error correction code of the NAND flash memory.

  On the other hand, when the Reed-Solomon code is used as an error correction code, the error correction capability is enhanced. However, when all the bit data of the write data is a logical value “1” (erased state), All bit data of the generated error correction code does not match the logical value “1” (erased state). Therefore, when a Reed-Solomon code is used as the error correction code of the NAND flash memory, a process for eliminating this mismatch is necessary.

In order to eliminate the inconsistency, in Patent Document 1 below, write data is compared with erased data at the time of write processing, and if both data match, an error generated based on the write data is generated. The correction code is not written in the redundant area. On the other hand, during the read process, the read data is compared with the erased data. If the two data match, no error detection or correction is performed on the read data.
JP 2004-71012 A

  In Patent Document 1, when the write data matches the erased data, the error correction code is not written to the redundant area, and when the read data matches the erased data, an error is detected for the read data. No corrections have been made. Therefore, when a read error occurs and the read data matches the erased data, there is a problem that the error is not detected or corrected.

  In addition, when an error included in the read data is detected, it is preferable to rewrite the corrected data corrected based on the error correction code, but the detected error is compared with the error correction capability. Even if it is small, if rewriting is performed uniformly, deterioration of the flash memory is promoted.

  Therefore, even if the problem in the case of using the Reed-Solomon code as described above is solved, the problem of promoting the deterioration of the flash memory by rewriting is not solved.

  Accordingly, the present invention provides a memory controller capable of suppressing deterioration of the flash memory when an error correction code having a high error correction capability is used, a flash memory system including the memory controller, and a flash memory control method. The purpose is to provide.

In order to achieve the above object, a memory controller according to the first aspect of the present invention provides:
A memory controller that accesses a flash memory in which data is written and read in units of pages, and data is erased in units of blocks of a plurality of pages.
Data reading means for reading data written in the user area of each page of the flash memory and additional information written in the redundant area of each page;
Based on information on error correction included in the additional information, error correction means for detecting and correcting an error included in the data read from the user area;
Rewrite means for writing the corrected data to the user area of the erased page when the error detected by the error correction means exceeds a preset set value;
It is characterized by providing.

  By adopting such a configuration, when the error detected by the error correction unit does not exceed the set value, writing by the rewriting unit does not occur.

The error correction means is configured to correct a plurality of bits or a plurality of symbols errors included in the data read from the user area,
The set value may be a value set with respect to the number of bits or symbols of errors detected by the error correction means.
In this case, if the number of bits or symbols that can be corrected by the error correction means is N (N is an integer of 2 or more), the set value may be set to an integer of 1 or more and N or less. . Furthermore, a means for variably changing the set value may be provided.

  In addition, the error correction information included in the additional information may be an error correction code generated based on data written in the user area.

  Further, the error correction information included in the additional information may be information obtained by performing a conversion process on an error correction code generated based on data written in the user area.

In this case, the conversion process may be an exclusive OR process with preset mask data.
Similarly, the writing error correction code may be a Reed-Solomon code.

  In order to achieve the above object, a flash memory system according to a second aspect of the present invention includes a memory controller according to the first aspect of the present invention, and data is written and read on a page-by-page basis. And a flash memory that is performed in units of blocks each including a plurality of pages.

In order to achieve the above object, a flash memory control method according to a third aspect of the present invention includes:
A flash memory control method for controlling access to a flash memory in which data is written and read in units of pages, and data is erased in units of blocks of a plurality of pages.
A read process for reading data written in the user area of each page of the flash memory and additional information written in the redundant area of each page;
Based on information on error correction included in the additional information, an error correction process for detecting and correcting an error included in the data read from the user area;
When the error detected by the error correction process exceeds a preset value, a rewrite process for writing the corrected data to the user area of the erased page;
It is characterized by including.

The error correction process is a process of correcting an error included in data read from the user area in units of bits or symbols,
The set value may be a value related to the number of bits or symbols of errors detected by the error correction process.

  In this case, if the number of bits or symbols that can be corrected by the error correction processing is N (N is an integer of 2 or more), the setting value may be set to an integer of 1 or more and N or less. . Furthermore, a setting value change process for changing the setting value variably may be included.

  In addition, the error correction information included in the additional information may be an error correction code generated based on data written in the user area.

  Further, the error correction information included in the additional information may be information obtained by performing a conversion process on an error correction code generated based on data written in the user area.

In this case, the conversion process may be an exclusive OR process with preset mask data.
The error correction code may be a Reed-Solomon code.

  According to the present invention, when an error correction code having high error correction capability is used, it is determined whether or not the detected error exceeds a preset level, and exceeds the preset level. Only when corrected data is rewritten. Therefore, by appropriately setting an error level that is a criterion for determining whether or not to perform rewriting, it is possible to suppress the deterioration of the flash memory with almost no decrease in reliability.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram schematically showing the flash memory system 1.
As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is usually detachably attached to the host system 4 and used as a kind of external storage device for the host system 4.

Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
Details of the flash memory 2 and the memory controller 3 will be described below.

[Description of flash memory 2]
In this flash memory system 1, a flash memory 2 in which data is stored is composed of a NAND flash memory. The NAND flash memory is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data is written. A process of erasing a block in which (data before rewriting) has been written is performed.

  When rewriting such data, since the data after rewriting is written in a different block from before rewriting, the logical address given from the host system 4 side and the physical address in the flash memory 2 The correspondence between and changes dynamically every time data is rewritten. Therefore, when accessing the flash memory 2, an address conversion table showing the correspondence between logical addresses and physical addresses is usually created, and the flash memory 2 is accessed using this address conversion table.

FIG. 2 is an explanatory diagram showing the relationship between blocks and pages.
The configuration of the block and page differs depending on the specifications of the flash memory 2, but in the general flash memory 2, as shown in FIG. 2A, one block is configured with 32 pages (P0 to P31). Each page includes a 512-byte user area and a 16-byte redundant area. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided.

  Here, the user area is mainly an area where data supplied from the host system 4 is stored, and the redundant area is stored with additional data such as an error correction code, corresponding logical address information and block status. Area. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block described later.

  The corresponding logical address information is written when data is stored in a physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the corresponding logical address information is not written, so whether the corresponding logical address information is written or not is the erased block. Can be judged. That is, if the corresponding logical block address is not written, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). When the physical block is determined to be a bad block, Is set with a flag indicating that it is a bad block.

Next, the circuit configuration of the flash memory 2 will be described.
A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from register to memory cell or copying from memory cell to register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate, and the lower gate is called a floating gate. By injecting charges (electrons) into the floating gate and discharging charges (electrons) from the floating gate, Data is written or erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When injecting electrons into the floating gate, a high voltage is applied so that the control gate is at the high potential side. When electrons are injected from the floating gate, a high voltage at which the control gate is at the low potential side is applied. Applied to discharge electrons. The state in which electrons are injected into the floating gate (write state) corresponds to data having a logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) has a logical value “1”. Corresponds to data.

[Description of Memory Controller 3]
The memory controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block 11. And a flash memory sequencer block 12.

The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, the function of each functional block will be described.
The microprocessor 6 is a functional block that controls the operation of all the functional blocks constituting the memory controller 3.

  The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is mounted on the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. The data supplied to the host system is taken into the memory controller 3 using the host interface block 7 as an entrance, and the data supplied from the flash memory system 1 to the host system 4 is sent to the host using the host interface block 7 as an exit. Supplied to system 4.
The host interface block 7 has a register for holding a logical address, a sector number, and an external command supplied from the host system 4, an error register (not shown) that is set when an error occurs, and the like.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 is ready to write. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on an internal command. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information.

  The aforementioned “internal command” is a command given from the memory controller 3 to the flash memory 2, and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.

  The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to the data to be written to the flash memory 2 and detects an error included in the read data based on the error correction code added to the read data. This is a functional block to be corrected.

Here, the ECC block 11 will be described in detail.
FIG. 3 is an explanatory diagram for explaining the operation of the ECC block in the writing process.
4 and 5 are diagrams for explaining the operation of the ECC block in the reading process.

The ECC block 11 includes an ECC register 22, a management data register 23, an error correction code / decoder 24, and a mask circuit 25.
The ECC register 22 temporarily holds the error correction code read from the redundant area of the flash memory 2. The management data register 23 temporarily holds management data to be written into the redundant area of the flash memory 2 or management data read from the redundant area of the flash memory 2. The error correction code / decoder 24 generates an error correction code based on the write data during the write process, and detects and corrects an error in the read data based on the error correction code during the read process. The mask circuit 25 performs preset first conversion processing and second conversion processing on the input error correction code. User data, management data (MNG) and error correction code (ECC-M) are written in the flash memory 2.

  The operation of the ECC block 11 will be described below by taking a Reed-Solomon code having 10 bits as 1 symbol and 4 symbol error correction and 5 symbol error detection capability as an example.

First, the operation of the ECC block 11 in the writing process will be described (see FIG. 3).
512 bytes (4096 bits) of write data (user data) supplied from the host system 4 is temporarily held in the buffer 9 and then transferred to the flash memory 2 and the error correction code / decoder 24. The 512 bytes (4096 bits) of write data transferred to the flash memory 2 is written into the user area of the flash memory 2.

  4-bit dummy data is added to the 512-byte (4096 bits) write data transferred to the error correction code / decoder 24. The error correction code / decoder 24 generates an error correction code for 4100-bit write data to which 4-bit dummy data is added. The generated 80-bit error correction code is subjected to the first conversion process by the mask circuit 25, and the error correction code (ECC-M) subjected to the first conversion process is the redundant area of the flash memory 2. Written in.

  The error correction code / decoder 24 uses a Reed-Solomon code capable of detecting an error of 5 symbols and correcting an error of 4 symbols with respect to 418 symbols. Here, one symbol corresponds to 10 bits, 410 symbols out of 418 symbols are assigned to write data, and 8 symbols are assigned to error correction codes.

  Since 410 symbols allocated to write data correspond to 4100 bits, 4-bit dummy data is added to 512-byte (4096 bits) write data (user data) transferred to the error correction code / decoder 24. ing. What is necessary is just to set suitably about the logic value of this dummy data.

  In the mask circuit 25, when all the 4096-bit bit data written in the user area of the flash memory 2 is in the erased state (logical value “1”), 80 bits after the first conversion process is performed. The conversion processing is performed so that all the bit data of the above are in the erased state (logical value “1”). When the Reed-Solomon code is used, when the 4096-bit bit data is all “1”, the 80-bit bit data generated by the error correction code / decoder 24 is all the logic “1”. However, if the first conversion process performed by the mask circuit 25 is appropriately set, all the bit data of the error correction code after the first conversion process is logically “1”. Can be made to correspond.

  Note that the error correction code generated by the error correction code / decoder 24 changes depending on the setting of the dummy data. However, no matter how the 4-bit dummy data is set, the 80-bit bit data are all logical values. It will never be "1".

Next, the operation of the ECC block 11 in the reading process will be described with reference to FIG.
User data read from the user area of the flash memory 2 is held in the buffer 9 and also input to the error correction code / decoder 24. Similarly to the case of the writing process, 4-bit dummy data is added to the 4096-bit bit data input to the error correction code / decoder 24.

  On the other hand, the error correction code (ECC-M) read from the redundant area is held in the ECC register 22 after being subjected to the second conversion process by the mask circuit 25, and is also stored in the error correction code / decoder. 24 is also input. In the second conversion process, a conversion process is performed to return the error correction code read from the redundant area to the error correction code before the first conversion process. That is, at the time of the writing process, the same error correction code as the error correction code generated by the error correction code / decoder 24 (error correction code before the first conversion process) is read 4096-bit user data Are input to the error correction code / decoder 24.

  The error correction code / decoder 24 detects errors contained in the user data and the error correction code based on the input 4096-bit user data, 4-bit dummy data, and 80-bit error correction code. When a correctable error is detected, the user data held in the buffer 9 or the error correction code held in the ECC register 22 is corrected. At this time, error detection and correction are performed in units of symbols (10 bits).

FIG. 5 shows a case where the error correction code / decoder 24 includes data holding means capable of holding 4180 bits of data.
In this case, the user data read from the user area and the error correction code subjected to the second conversion process by the mask circuit 25 are input only to the error correction code / decoder 24, and the error correction code / decoder 24 is input. It is held in the data holding means.

  As in the case of FIG. 4, error detection based on user data, dummy data, and error correction code is performed, and if a correctable error is detected, data in error correction code / decoder 24 is retained. The user data and error correction code held in the means are corrected. Thereafter, the user data and the error correction code are transferred to the buffer 9 and the ECC register 22, respectively.

Next, a method for setting the mask circuit 25 will be described with reference to FIGS.
FIG. 6 is an explanatory diagram showing an overview of the first conversion process.
FIG. 7 is an explanatory diagram showing an overview of the second conversion process.

The mask circuit 25 includes a mask data output circuit 25a that outputs mask data and a logic circuit 25b that outputs an exclusive OR.
In the case of the first conversion process (see FIG. 6), the error correction code (ECC) output from the error correction code / decoder 24 is input to the logic circuit 25b, and the error correction code and mask data are input to the logic circuit 25b. Is calculated. The post-operation error correction code (ECC-M) output from the logic circuit 25 b is written in the redundant area of the flash memory 2.

  In the case of the second conversion process (see FIG. 7), the error correction code (ECC-M) read from the redundant area of the flash memory 2 is input to the logic circuit 25b, and is excluded from the mask data by the logic circuit 25b. A logical OR operation is performed. In this configuration, the same mask data is used in the first conversion process and the second conversion process. When the second error correction code is applied to the error correction code (ECC-M) subjected to the first conversion process using the same mask data, the error correction code ( ECC) is obtained. The error correction code (ECC) before the first conversion process is input to the error correction code / decoder 24.

Next, mask data when Reed-Solomon codes are used will be described.
FIG. 8 is a diagram showing the correspondence between ECC symbols and mask data.
FIG. 8 shows the mask data and the error correction code before and after the arithmetic processing when a Reed-Solomon code capable of detecting an error of 5 symbols and correcting an error of 4 symbols is used for 418 symbols. Here, the error correction code is shown for each symbol, and the mask data is also shown for every 10 bits accordingly. The illustrated 8-symbol error correction code is an error correction code when all 4096-bit bit data given as user data is in an erased state (logical value “1”), and the 4-bit dummy data is , All are set to logical value “0”.

  The error correction code symbols ECC0 to ECC7 are subjected to an exclusive OR operation with the mask data set for each of them. Mask data 36Bh (hexadecimal notation) is assigned to ECC0 symbol 094h (hexadecimal notation), and mask data 249h (hexadecimal notation) is assigned to ECC1 symbol 1B6h (hexadecimal notation).

  Mask data 344h (hexadecimal display) is assigned to the symbol 0BBh (hexadecimal display) of ECC2, and mask data 3C1h (hexadecimal display) is assigned to the symbol 03Eh (hexadecimal display) of ECC3. Mask data 348h (hexadecimal notation) is assigned to ECC4 symbol 0B7h (hexadecimal notation), and mask data 168h (hexadecimal notation) is assigned to ECC5 symbol 297h (hexadecimal notation). Mask data 2ACh (hexadecimal notation) is assigned to the ECC6 symbol 153h (hexadecimal notation), and mask data 12Bh (hexadecimal notation) is assigned to the ECC7 symbol 2D4h (hexadecimal notation).

FIG. 9 is a diagram for explaining an exclusive OR operation process, and shows an ECC symbol, master data, and a symbol after the operation process in binary numbers.
FIG. 9 shows the ECC0 symbol 094h (hexadecimal notation), the mask data 36Bh (hexadecimal notation) assigned to ECC0, and the symbol (ECC-M) after these arithmetic processings in binary notation. . In the exclusive OR operation, the error correction symbol symbol and the mask data are compared bit by bit. When the logical values are equal, a logical value of “0” is output, and when the logical values are different, The value “1” is output.

  Since 094h (hexadecimal notation) and 36Bh (hexadecimal notation) have different logical values of all bits, the symbol (ECC-M) after the arithmetic processing is 3FFh (hexadecimal notation). Since the symbols 1 to 7 and the respective mask data assigned to these also have different logical values of the corresponding bits, the symbols after the arithmetic processing (ECC-M) are all 3FFh (16 Decimal number display).

FIG. 10 is a diagram for explaining an exclusive OR operation process, and shows a symbol, a master data, and an ECC symbol after the operation process in binary numbers.
The second conversion process, that is, the exclusive OR operation of the mask data 36Bh (hexadecimal notation) assigned to ECC0 and the symbol (ECC-M) 3FFh (hexadecimal notation) after the arithmetic process was performed. In this case, the symbol 094h (in hexadecimal notation) of ECC0 is obtained. That is, when an arithmetic operation of an exclusive OR of the symbol (ECC-M) after the arithmetic processing and the mask data is performed, the symbol (ECC) before the arithmetic processing is obtained.

  In the first conversion process performed on the error correction code output from the error correction code / decoder 24 during the write process, all bit data of the user data is in the erased state (logical value “ If the conversion processing is such that all the bit data of the error correction code after the conversion processing is in the erased state (logical value “1”) at the time of 1 ″), there is no particular limitation. Further, the second conversion process performed on the error correction code read from the flash memory 2 during the read process is a conversion that can obtain an error correction code before the first conversion process. If it is processing, it will not be limited in particular.

  As described above, a Reed-Solomon code having 4-symbol error correction and 5-symbol error detection capability can be used as the error correction code. With this setting, errors of 4 symbols or less can be corrected, but errors of 5 symbols or more cannot be corrected. Accordingly, it is necessary to rewrite the corrected data while the error included in the data read from the flash memory 2 is 4 symbols or less.

  Temporarily, when the error included in the data read from the flash memory 2 is 4 symbols, the data is left without being rewritten, and after that, the deterioration of the flash memory 2 proceeds and the data is read next time. If the error included in the read data is 5 symbols, the error cannot be corrected.

  When rewriting the corrected data, after erasing the block in which the original data was written, the corrected data may be written in the block or in another erased block. . When the correspondence between logical addresses and physical addresses is managed in units of blocks, even if an error is detected only when data is read from a specific page in the block, it is written to another page. Often, the embedded data must also be rewritten.

  In such a case, the data is read sequentially from the page in the block where the original data was written, and the read data (or corrected data if an error is detected) is sequentially erased separately. After writing to the block and completion of all data transfer (data transfer from the block where the original data was written to another erased block), the block where the original data was written is erased (block erase) Alternatively, information indicating that the data written in the block in which the original data has been written is invalid is set).

  When error correction of 4 symbols is possible with the error correction code as described above, even if the corrected data is rewritten when the error included in the read data is 1 symbol, Even if the corrected data is rewritten when the error included is 2 symbols, the corrected data is rewritten or read when the error included in the read data is 3 symbols. If the error included in the data is 4 symbols, the corrected data may be rewritten.

  However, as the number of times of erasing and writing increases, the deterioration of the flash memory 2 progresses. Therefore, the number of times of erasing and writing is preferably as small as possible. Therefore, it is more erasure that rewriting is not performed when the error included in the read data is 1 symbol, and rewriting is performed when the error included in the read data is 4 symbols. Since the number of times of writing can be reduced, it is preferable in terms of suppressing deterioration of the flash memory 2.

  On the other hand, in terms of reliability of data written in the flash memory 2, it is preferable to perform rewriting while the number of erroneous symbols included in the read data is small.

  Therefore, the number of erroneous symbols included in the read data is rewritten when the number of error symbols becomes more than the aspect of suppressing the deterioration of the flash memory 2 and the data written in the flash memory 2. It is preferable to determine in consideration of both aspects of reliability.

  For example, when emphasizing the reliability of the data written in the flash memory 2, the flash memory 2 is set so that rewriting is performed when the error included in the read data becomes 2 symbols or more. If it is important to suppress the deterioration of the memory 2, the rewriting may be performed when the error included in the read data becomes 4 symbols or more.

  In addition, since the progress rate of deterioration may increase as the usage period of the flash memory 2 increases, it is preferable that the setting of the number of symbols to be rewritten can be changed as appropriate.

  For example, it is set so that rewriting is performed when the error included in the data read at the start of use becomes 4 symbols or more, and then the error included in the data read in consideration of the usage time and the like. The setting may be changed so that rewriting is performed when 3 becomes more than 3 symbols or when 2 becomes more than 2 symbols.

  When a Reed-Solomon code is used as an error correction code, an error is detected and corrected in symbol units. However, when a BCH code or a Hamming code is used as an error correction code, error detection is performed in bit units. Corrections are made. Therefore, when a BCH code or a Hamming code is used as an error correction code, it is set how many times the number of error bits included in the read data is rewritten.

  For example, when the BCH code is used as an error correction code and is set so that 3-bit error correction and 4-bit error detection can be performed for 256 bytes, the number of bits of error to be rewritten is as follows: Can be set to In this example, error correction of data read from each page is performed in 256 byte segments, so that if the user area of one page is 512 bytes, error correction is performed for each of the two segments. .

  Therefore, when setting the number of error bits included in the read data to be rewritten when the number of error bits exceeds, the number of error bits included in any section in one page is 3 You may set so that it rewrites when it becomes a bit. Further, it may be set such that rewriting is performed when the sum of errors included in the data read from each page becomes 3 bits or more without making a judgment for each section. However, when the number of error bits included in any of the sections becomes 4 bits, error correction cannot be performed and rewriting is not performed.

  Note that the number of symbols and the number of bits that can be corrected based on the error correction code can be appropriately set according to the size (number of bits) of the error correction code written in the redundant area. However, since the capacity of the error correction code increases as the number of symbols and bits that can be corrected based on the error correction code increases, correction is performed in consideration of the size of the area that can be allocated to the error correction code in the redundant area. The number of possible symbols and bits must be set.

1 is a block diagram of a flash memory system according to an embodiment of the present invention. It is a figure which shows the structure of the block and page of flash memory. It is a block diagram for demonstrating the process of an ECC block. It is a block diagram for demonstrating the process of an ECC block. It is a block diagram for demonstrating the process of an ECC block. It is explanatory drawing which shows the outline | summary of a 1st conversion process. It is explanatory drawing which shows the outline | summary of a 2nd conversion process. It is a figure which shows the correspondence of an ECC symbol and mask data. It is a figure for demonstrating the calculation process of exclusive OR. It is a figure for demonstrating the calculation process of exclusive OR.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus 22 ECC register 23 Management data register 24 Error correction code / decoder 25 Mask circuit 25a Mask data output circuit 25b Logic circuit

Claims (17)

A memory controller that accesses a flash memory in which data is written and read in units of pages, and data is erased in units of blocks of a plurality of pages.
Data reading means for reading data written in the user area of each page of the flash memory and additional information written in the redundant area of each page;
Based on information on error correction included in the additional information, error correction means for detecting and correcting an error included in the data read from the user area;
Rewrite means for writing the corrected data to the user area of the erased page when the error detected by the error correction means exceeds a preset set value;
A memory controller comprising: The error correction means is configured to correct errors of a plurality of bits or a plurality of symbols included in data read from the user area,
2. The memory controller according to claim 1, wherein the set value is a value set with respect to the number of bits or symbols of errors detected by the error correction unit.   When the number of bits or symbols that can be corrected by the error correction means is N (N is an integer of 2 or more), the setting value is set to an integer of 1 or more and N or less. The memory controller according to claim 2.   4. The memory controller according to claim 3, further comprising means for variably changing the set value.   The information regarding error correction included in the additional information is an error correction code generated based on data written in the user area. Memory controller.   2. The error correction information included in the additional information is information obtained by performing conversion processing on an error correction code generated based on data written in the user area. 6. The memory controller according to any one of items 1 to 5.   The memory controller according to claim 6, wherein the conversion process is an exclusive OR process with preset mask data.   8. The memory controller according to claim 6, wherein the error correction code is a Reed-Solomon code.   9. A memory controller according to any one of claims 1 to 8, and a flash memory in which data writing and reading are performed in units of pages and data is erased in units of blocks including a plurality of pages. A featured flash memory system. A flash memory control method for controlling access to a flash memory in which data is written and read in units of pages, and data is erased in units of blocks of a plurality of pages.
A read process for reading data written in the user area of each page of the flash memory and additional information written in the redundant area of each page;
Based on information on error correction included in the additional information, an error correction process for detecting and correcting an error included in the data read from the user area;
When the error detected by the error correction process exceeds a preset value, a rewrite process for writing the corrected data to the user area of the erased page;
A method for controlling a flash memory, comprising: The error correction process is a process of correcting an error included in data read from the user area in units of bits or symbols,
The flash memory control method according to claim 10, wherein the set value is a value related to the number of bits or symbols of errors detected by the error correction processing.   When the number of bits or symbols that can be corrected by the error correction processing is N (N is an integer of 2 or more), the setting value is set to an integer of 1 or more and N or less. The flash memory control method according to claim 11.   13. The flash memory control method according to claim 12, further comprising setting value change processing for changing the setting value variably.   The information on error correction included in the additional information is an error correction code generated based on data written in the user area, according to any one of claims 10 to 13. Flash memory control method.   11. The information regarding error correction included in the additional information is information obtained by performing conversion processing on an error correction code generated based on data written in the user area. 15. The flash memory control method according to any one of 1 to 14.   16. The flash memory control method according to claim 15, wherein the conversion process is an exclusive OR process with mask data set in advance. 17. The flash memory control method according to claim 15, wherein the error correction code is a Reed-Solomon code.

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