JP4273038B2 - Memory controller, flash memory system, and flash memory data transfer method - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory data transfer method.

  A semiconductor memory is used in a memory system such as a memory card or a silicon disk. In recent years, flash memories have been widely used as the semiconductor memory. A flash memory is a kind of nonvolatile memory, and is required to retain data even when power is not supplied.

  In particular, NAND flash memories are often used in the memory system. The NAND flash memory includes a plurality of memory cells, and each memory cell is in an erased state when data indicating a logical value “1” is stored. Further, when data indicating a logical value “0” is stored, each memory cell is in a write state.

  Each of the plurality of memory cells included in the NAND flash memory can be changed from the erased state to the written state independently of the other memory cells.

In contrast, each memory cell cannot change from a written state to an erased state independently of the other memory cells.
At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This collective erasure operation is generally called “block erase”.

  The writing process or the reading process for the NAND flash memory is performed in a predetermined number of memory units called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  Data written to the flash memory is once held in a register in the flash memory, and then copied from the register to each memory cell constituting the memory cell array. During this copying, the flash memory is busy and does not accept other processing. For this reason, the flash memory cannot be accessed until the busy state is released.

  In order to perform copying from a register to a memory cell or from a memory cell to a register, a high voltage must be applied to the memory cell to inject electrons. For this reason, the busy state period due to the execution of copying becomes longer, and the processing efficiency of the writing process decreases.

In order to solve such a problem, there is one in which a plurality of flash memories are provided and processing is performed in order from the flash memory in which the busy state is detected to be released (for example, see Patent Document 1). .
Japanese Patent Laid-Open No. 10-63442

  However, in the conventional memory, write processing and read processing are sequentially started with respect to the flash memory whose busy state has been released, so the processing time is shortened, but occurs when processing is executed in the flash memory. Variation occurs in the busy period. Due to this variation, the progress of processing in each flash memory is biased. If the writing process is performed while this state is left as it is, the writing process is preferentially performed on the flash memory that progresses quickly, and the order of data written to each flash memory is disturbed.

  The present invention has been made in view of such conventional problems, and provides a memory controller, a flash memory system, and a flash memory data transfer method capable of avoiding a bias in processing order in the flash memory. The purpose is to provide.

In order to achieve this object, a memory controller according to the first aspect of the present invention provides:
In a memory controller that transfers data to and from multiple flash memories that store data,
A data storage unit for storing data for performing data transfer with the plurality of flash memories;
Between the data storage unit and each flash memory, provided corresponding to each flash memory, transmitting a processing request signal requesting data transfer, receiving a permission signal permitting data transfer, and corresponding A plurality of data transfer units that perform data transfer between the flash memory and the data storage unit;
A plurality of processing request signals transmitted from the plurality of data transfer units are received, and a permission signal in which a transmission timing is set so that data transfer by each data transfer unit is performed in order is sent to each data transfer unit. And a transfer control unit for transmission.

Each flash memory performs data input / output in units of pages,
The data storage unit is provided with a plurality of data holding units capable of holding an amount of data corresponding to each page of each flash memory as holding the data to be transferred,
Each of the data holding units may be configured such that data is discharged in order from the data supplied.

  The transfer control unit determines the order of data transfer performed between the data storage unit and each of the flash memories, and the processing request signal from the data transfer unit that is determined to be later is the processing request signal from the first Is received prior to the processing request signal from the data transfer unit determined to be transmitted, the permission signal is transmitted to the data transfer unit determined to be the first in order and data transfer is performed between the corresponding flash memory. After that, the transmission timing of the permission signal to each data transfer unit may be set so that the permission signal is transmitted to the data transfer unit determined to be later in the order.

  The transfer control unit may set the order in which the data transfer unit that has performed data transfer with the flash memory is to perform data transfer next is the last.

A flash memory system according to a second aspect of the present invention includes:
A plurality of flash memories for storing data;
And a memory controller according to any one of claims 1 to 4.

A data transfer method for a flash memory according to a third aspect of the present invention is:
Receiving a processing request signal for requesting data transfer from a plurality of data transfer units provided corresponding to each of the flash memories in order to perform data transfer with a plurality of flash memories storing data; ,
Setting a transmission timing for transmitting a permission signal for permitting the data transfer so that data transfer with each of the flash memories is performed in order;
Transmitting the permission signal to each data transfer unit according to the transmission timing.

  According to the present invention, it is possible to avoid a deviation in processing order in the flash memory.

Hereinafter, a memory device according to an embodiment of the present invention will be described with reference to the drawings.
The configuration of the flash memory system according to the present embodiment is shown in FIG.
The flash memory system 1 according to the present embodiment is normally used by being detachably attached to the host system 2 and used as a kind of external storage device for the host system 2.

  The host system 2 processes various information such as characters, sounds, or image information, like a computer or a digital still camera. The host system 2 gives a logical address to the flash memory system 1 to access the flash memory 10.

  The flash memory system 1 includes a flash memory 10 and a controller 20. The flash memory 10 has been developed as a use for a storage device that replaces a hard disk, and includes a plurality of chips made of NAND flash memory.

  The NAND flash memory is a nonvolatile memory, and generally includes a register and a memory cell array. Data is copied between the register and the memory cell to write or read data.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When electrons are injected into the floating gate, electrons are injected by applying a high voltage at which the control gate is on the high potential side. Further, when electrons are discharged from the floating gate, electrons are discharged by applying a high voltage at which the control gate is on the low potential side.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  In a memory cell array of a general NAND flash memory, for example, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31). Each page includes a 512-byte user area and a 16-byte redundant area.

  However, the configuration of the NAND flash memory differs depending on the specifications. When the storage capacity is large, for example, as shown in FIG. 2B, the NAND flash memory has 64 pages (P0 to P63) for one block, a user area of 2048 bytes for each page, and a redundant area of 64 bytes. Consists of.

  The user area is mainly an area for storing data supplied from the host system 2, and the redundant area is for recording additional data such as an error collection code, a corresponding logical block address, and a block status (flag). It is an area.

  The error collection code is data for detecting and correcting an error included in the data stored in the user area.

  The corresponding logical block address is data indicating an address corresponding to a block in which data is stored.

  The block status is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a flag indicating a defective block is written in the redundant area.

  In the NAND flash memory configured as described above, random access cannot be performed, data writing and reading are performed in units of pages via a register, and erasing is performed in units of blocks. In addition, since data cannot be overwritten in the NAND flash memory, the data is written in an area where the data has been erased.

  Since the NAND flash memory has such a feature, when data is rewritten, normally, new data is written in a block from which data has been erased, and old data before rewriting is written in the block. Data is erased in blocks. When such data rewriting is performed, the rewritten data is written in a different block from that before rewriting.

  For this reason, the correspondence between the logical address that the host system 2 gives to the flash memory system 1 and the physical block address that is the block address in the flash memory 10 dynamically changes every time data is rewritten.

  Therefore, it is necessary to manage the correspondence between the logical block address and the physical block address, and this correspondence is usually managed by the address conversion table. This address conversion table is created based on the corresponding logical block address stored in the redundant area of each page.

  When no data is stored in the block, the corresponding logical block address corresponding to this block is not stored in the redundant area of the flash memory 10. Therefore, whether or not the corresponding logical block address is stored can determine whether or not the block is an erased block.

  The block status is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a flag indicating a defective block is written in the redundant area.

  Returning to FIG. 1, the controller 20 includes a host interface 21, a microprocessor 22, a work area 23, a buffer 24, an ECC block 25, and a flash memory interface 26.

  The host interface 21 is a functional block for exchanging data, address information, status information, external command information, and the like with the host system 2, and includes an operation setting register, a task file register, an error register, etc. (Not shown).

  Among these, the task file register is a register for temporarily storing a host address and an external command supplied from the host system 2. The error register is a register in which data is set when an error occurs.

  The flash memory system 1 mounted on the host system 2 is connected to the host system 2 via the external bus 31. When data or the like is supplied from the host system 2, the host interface 21 takes in the supplied data or the like as an entrance of the flash memory system 1 into the controller 20.

  When the flash memory system 1 supplies data or the like to the host system 2, the host interface 21 functions as an outlet of the flash memory system 1 that supplies data or the like to the host system 2.

  The microprocessor 22 is a functional block for controlling the operation of the entire functional blocks constituting the controller 20.

  The work area 23 is a work area for temporarily storing data necessary for controlling the flash memory 10, and includes a plurality of SRAM (Static Random Access Memory) cells. The work area 23 also stores the aforementioned address conversion table for managing the correspondence between logical block addresses and physical block addresses as necessary data.

  The ECC block 25 generates error correction data to be added to the data to be written to the flash memory 10, and performs error detection of the read data based on the error correction code added to the read data, and detects the detected error. This is a functional block for correction.

  The buffer 24 holds data read from the flash memory 10 until the host system 2 is ready to receive data, and temporarily holds data to be written to the flash memory 10 until it is ready to write to the flash memory 10. It is a functional block for

  The buffer 24 includes a plurality of data holding units that hold data to be transferred. Each data holding unit is assigned an area for holding data per page of each chip of the flash memory 10.

  For example, when one page of each chip of the flash memory 10 is composed of 512-byte data, the microprocessor 22 sets an area in which each 512-byte data can be held in each data holding unit. assign.

  When one page is composed of 2048 bytes of data, the microprocessor 22 allocates an area capable of holding 2048 bytes of data to each data holding unit. When the amount of data exceeds one page, the microprocessor 22 sets a plurality of data holding units corresponding to each page in the buffer 24.

  Each data holding unit is configured so that data is supplied in units of pages, and data is discharged in order from the data holding unit to which the data is supplied. The microprocessor 22 performs control related to such a data holding unit.

  The flash memory interface 26 is a functional block provided to exchange data, address information, status information, internal command information, device ID information, and the like with the flash memory 10 via the internal bus 32. The flash memory interface 26 includes a plurality of registers (not shown) for setting information necessary for executing an internal command.

  Here, the internal command is a command for the controller 20 to instruct the flash memory 10 to execute processing, and the flash memory 10 operates according to the internal command from the controller 20. In contrast, the external command is a command for the host system 2 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 3, the flash memory interface 26 includes interfaces 26-0 and 26-1 and a monitoring control unit 27. The interfaces 26-0 and 26-1 are provided as a plurality of interfaces that transfer data and the like independently with the flash memory 10.

  The interface 26-0 is an interface of CH (channel) 0 that is provided corresponding to the chip 10-0 of the flash memory 10 and performs data transfer with the chip 10-0 corresponding to the NAND flash memory.

  When performing data transfer with the chip 10-0, the interface 26-0 transmits a processing request signal REQ0 for requesting data transfer to the monitoring control unit 27 as shown in FIG. The interface 26-0 receives the permission signal ACK0 ′ transmitted from the monitoring control unit 27 in response to the processing request signal REQ0, and performs data writing or reading processing on the chip 10-0. Forward.

  The interface 26-1 is a CH1 interface that is provided corresponding to the chip 10-1 of the flash memory 10 and performs data transfer with the chip 10-1 corresponding to the NAND flash memory.

  When performing data transfer with the chip 10-1, the interface 26-1 transmits a processing request signal REQ1 for requesting data transfer to the monitoring control unit 27 as shown in FIG. The interface 26-1 receives the permission signal ACK1 ′ transmitted from the monitoring control unit 27 in response to the processing request signal REQ1, and receives data for performing a writing process or a reading process on the chip 10-1. Forward.

  The monitoring control unit 27 receives the two processing request signals REQ0 and REQ1 transmitted from the interfaces 26-0 and 26-1, and transmits the data so that the data transfer is sequentially performed by the interfaces 26-0 and 26-1. The permission signals ACK0 ′ and ACK1 ′ for which the timing is set are transmitted to the interfaces 26-0 and 26-1, respectively.

  When the monitoring control unit 27 receives the processing request signals REQ0 and REQ1 from the interfaces 26-0 and 26-1, respectively, whichever of the interfaces 26-0 and 26-1 is first, the chip 10-0. , 10-1 to determine whether or not to transfer data.

  For example, when the monitoring control unit 27 determines that the data transfer by the interface 26-0 is first, and receives the processing request signal REQ1 from the interface 26-1, the monitoring control unit 27 receives the processing request signal from the interface 26-0. Wait until REQ0 is received. When the monitoring control unit 27 receives the processing request signal REQ0, the monitoring control unit 27 transmits a processing request signal REQ0 'corresponding to the processing request signal REQ0 to the buffer 24.

  The buffer 24 transmits an enabling signal ACK0 to the monitoring control unit 27 in response to the processing request signal REQ0 '. The monitoring control unit 27 receives the permission signal ACK0 from the buffer 24 and transmits the permission signal ACK0 'to the interface 26-0. When the monitoring control unit 27 transmits the permission signal ACK0 'to the interface 26-0, the monitoring control unit 27 stores the order in which the interface 26-0 performs the next data transfer after the interface 26-1.

Then, the monitoring control unit 27 transmits the permission signal ACK0 ′ to the interface 26-0 after the next data transfer order becomes the interface 26-1, that is, the processing request corresponding to the processing request signal REQ1. The signal REQ1 ′ is transmitted to the buffer 24.
The buffer 24 transmits the permission signal ACK1 to the monitoring control unit 27 in response to the processing request signal REQ1 ′. The monitoring control unit 27 receives the permission signal ACK1 from the buffer 24 and transmits the permission signal ACK1 ′ to the interface 26-1. When transmitting the permission signal ACK1 ′ to the interface 26-1, the monitoring control unit 27 stores the order in which the interface 26-1 performs the next data transfer after the interface 26-0.

  For example, when the monitoring control unit 27 determines that the data transfer through the interface 26-1 is ahead, and receives the processing request signal REQ0 from the interface 26-0, the monitoring control unit 27 performs processing from the interface 26-1. Wait until the request signal REQ1 is received. Upon receiving the processing request signal REQ1, the monitoring control unit 27 transmits a processing request signal REQ1 'corresponding to the processing request signal REQ1 to the buffer 24.

  The buffer 24 transmits the permission signal ACK1 to the monitoring control unit 27 in response to the processing request signal REQ1 '. The monitoring control unit 27 receives the permission signal ACK1 from the buffer 24 and transmits the permission signal ACK1 'to the interface 26-1. When transmitting the permission signal ACK1 'to the interface 26-1, the monitoring control unit 27 stores the order in which the interface 26-1 performs the next data transfer after the interface 26-0.

Then, the monitoring control unit 27 transmits the permission signal ACK1 ′ to the interface 26-1 after the next data transfer order becomes the interface 26-0, that is, the processing request corresponding to the processing request signal REQ0. The signal REQ0 ′ is transmitted to the buffer 24.
The buffer 24 transmits the permission signal ACK0 to the monitoring control unit 27 in response to the processing request signal REQ0 ′. The monitoring control unit 27 receives the permission signal ACK0 from the buffer 24 and transmits the permission signal ACK0 ′ to the interface 26-0. When the monitoring control unit 27 transmits the permission signal ACK0 ′ to the interface 26-0, the monitoring control unit 27 stores the order in which the interface 26-0 performs the next data transfer after the interface 26-1.

  In this way, the monitoring control unit 27 sets the transmission timing of the permission signals ACK0 'and ACK1' so that data transfer is alternately performed between the interfaces 26-0 and 26-1.

Next, the operation of the flash memory system 1 according to the present embodiment will be described.
When the flash memory system 1 is attached to the host system 2, the flash memory system 1 is connected to the host system 2 via the external bus 31.

When writing data to the flash memory 10, the host system 2 supplies an address to the flash memory system 1 via the external bus 31 and supplies the data to be written to the flash memory system 1.
The flash memory system 1 takes the supplied data into the controller 20 via the host interface 21.

  For example, as shown in FIG. 5, the microprocessor 22 sets three data holding units 24 </ b> A, 24 </ b> B, and 24 </ b> C in the buffer 24. Assuming that the number of bytes per page of the flash memory 10 is 512 bytes, the microprocessor 22 assigns 512-byte areas to the three data holding units 24A, 24B, and 24C, respectively.

  The microprocessor 22 partitions the data supplied from the host system 2 so as to correspond to the allocated 512-byte area. Assuming that the divided data is data from Page1 to Page5 as shown in FIG. 5, first, the microprocessor 22 converts the data of Page1, Page2, and Page3 into the data as shown in FIG. The data is held in the data holding units 24A, 24B, and 24C of the buffer 24. The data holding units 24A, 24B, and 24C temporarily hold data to be written to the flash memory 10 until preparation for writing to the flash memory 10 is completed.

  The flash memory interface 26 and the buffer 24 transmit and receive processing request signals REQ0 'and REQ1' and permission signals ACK0 and ACK1. In this case, as shown in FIGS. 7A to 7C, three patterns are possible at the timing of transmitting and receiving data. The relationship between the patterns 1 to 3 is reversed when the interfaces 26-0 and 26-1 are replaced.

  First, in the pattern 1, as shown in FIG. 7A, the interface 26-0 that should transfer data first transmits the processing request signal REQ0 to the monitoring control unit 27 before the interface 26-1. It is.

  In the case of pattern 1, as shown in FIG. 7A, the monitoring control unit 27 receives the processing request signals REQ0 and REQ1 in this order from the interfaces 26-0 and 26-1, respectively. The monitoring control unit 27 outputs a processing request signal REQ0 ′ corresponding to the processing request signal REQ0 to the buffer 24. The buffer 24 outputs the permission signal ACK0 to the monitoring control unit 27. The monitoring control unit 27 receives the permission signal ACK0 and outputs the permission signal ACK0 'corresponding to the permission signal ACK0 to the interface 26-0.

  The monitoring control unit 27 outputs a processing request signal REQ1 'corresponding to the processing request signal REQ1 to the buffer 24. When the buffer 24 outputs the permission signal ACK1 to the monitoring control unit 27 in response to the processing request signal REQ1 ', the monitoring control unit 27 transmits the permission signal ACK1' corresponding to the permission signal ACK1 to the interface 26-1.

  As shown in FIG. 7B, the pattern 2 is a case where the interface 26-1 to which data transfer is to be performed later transmits the processing request signal REQ1 to the monitoring control unit 27 before the interface 26-0. .

  In the case of pattern 2, as shown in FIG. 7B, the monitoring control unit 27 receives the processing request signal REQ0 from the interface 26-0 even if the processing request signal REQ1 from the interface 26-1 is received first. Wait for reception. Upon receiving the processing request signal REQ0 from the interface 26-0, the monitoring control unit 27 transmits the processing request signal REQ0 'to the buffer 24.

  When the buffer 24 transmits the permission signal ACK0 to the monitoring control unit 27 in response to the processing request signal REQ0 ′, the monitoring control unit 27 receives the permission signal ACK0 and receives the permission signal ACK0 ′ corresponding to the permission signal ACK0. Is output to the interface 26-0.

  Next, the monitoring control unit 27 transmits a processing request signal REQ <b> 1 ′ to the buffer 24. When the buffer 24 outputs the permission signal ACK1 to the monitoring control unit 27 in response to the processing request signal REQ1 ′, the monitoring control unit 27 transmits the permission signal ACK1 ′ corresponding to the permission signal ACK1 to the interface 26-1. .

FIG. 8 shows the timing of writing data to the flash memory 10 in this pattern 2.
As shown in FIGS. 8A and 8C, the flash memory 10 connected to the interfaces 26-0 and 26-1 has a signal S12 as a busy signal at times t10 and t11 (t10 <t11), respectively. , Signal S10 is raised from L (low) level to H level (high level). Note that the L level of the busy signal indicates that processing is in progress, and the H level indicates that standby is in progress.

  When the signal S12 (BUSY_CH1) rises to the H level, the interface 26-1 sequentially outputs the command signal C and the address signal A to the flash memory 10 (chip 10-1) via the internal bus 32.

  Subsequently, the interface 26-1 raises the processing request signal REQ1 from the L level to the H level, as indicated by a signal S13 in FIG. However, even if the signal S13 (REQ1) rises to the H level, the monitoring control unit 27 waits until the processing request signal REQ0 rises.

  On the other hand, when the signal S10 rises, the interface 26-0 sequentially outputs the command signal C and the address signal A to the flash memory 10 (chip 10-0). The command signal C is a command for transferring data to be written to a register in the flash memory 10 (chip 10-0). Subsequently, the interface 26-0 raises the processing request signal REQ0 from the L level to the H level as indicated by a signal S11 in FIG. 8B.

  When the signal S11 (REQ0) rises to the H level, the supervisory control unit 27 raises the processing request signal REQ0 'from the L level to the H level as indicated by the signal S14 in FIG.

  When the processing request signal REQ0 'rises to the H level, the buffer 24 raises the permission signal ACK0 from the L level to the H level, as indicated by a signal S15 in FIG.

  When the signal S15 (ACK0) rises to the H level, the supervisory control unit 27 raises the permission signal ACK0 'from the L level to the H level as indicated by the signal S16 in FIG.

  When the signal S16 (ACK0 ') rises to the H level, the interface 26-0 transfers the data D held in the buffer 24 to the flash memory 10.

  Further, when the signal S16 (ACK0 ') rises to the H level, the monitoring control unit 27 raises the processing request signal REQ1' from the L level to the H level as indicated by the signal S17 in FIG.

  When the signal S17 (REQ1 ') rises to the H level, the buffer 24 responds and raises the permission signal ACK1 from the L level to the H level, as indicated by the signal S18 in FIG. 8 (i).

  When the signal S18 (ACK1) rises to the H level, the supervisory control unit 27 raises the permission signal ACK1 'from the L level to the H level as indicated by the signal S19 in FIG.

  When the signal S16 (ACK1 ') rises to the H level, the interface 26-1 transfers the data D held in the buffer 24 to the flash memory 10.

  When the transfer of the data D to the chip 10-0 of the flash memory 10 is completed, the interface 26-0 transmits a command signal C ′ to the flash memory 10 (chip 10-0) via the internal bus 32.

  When the transfer of the data D to the chip 10-1 of the flash memory 10 is completed, the interface 26-1 transmits a command signal C ′ to the flash memory 10 (chip 10-1) via the internal bus 32. . The command signal C ′ is a command for copying data held in the register in the flash memory 10 to the memory cell array in the flash memory 10.

  At such timing, data writing processing in pattern 2 is performed.

  As shown in FIG. 7C, the pattern 3 is a case where the interface 26-0 that has performed data transfer transmits the processing request signal REQ0 to the monitoring controller 27 again before the interface 26-1. is there.

  In the case of pattern 3, when receiving the processing request signal REQ 0, the monitoring control unit 27 transmits the processing request signal REQ 0 ′ to the buffer 24 as shown in FIG. The buffer 24 transmits the permission signal ACK0 to the monitoring control unit 27 in response to the processing request signal REQ0 '.

  When the monitoring control unit 27 receives the permission signal ACK0, the monitoring control unit 27 transmits the permission signal ACK0 'to the interface 26-0. In this case, the monitoring control unit 27 determines that the next data transfer is the interface 26-1. Even if the monitoring control unit 27 receives the processing request signal REQ0 from the interface 26-0 again, the monitoring control unit 27 stands by until the processing request signal REQ1 is received.

  Upon receiving the processing request signal REQ1 from the interface 26-1, the monitoring control unit 27 transmits the processing request signal REQ1 'to the buffer 24.

  When the buffer 24 transmits the permission signal ACK1 to the monitoring control unit 27 in response to the processing request signal REQ1 ′, the monitoring control unit 27 receives the permission signal ACK1 and receives the permission signal ACK1 ′ corresponding to the permission signal ACK1. Is output to the interface 26-1.

  Next, the monitoring control unit 27 transmits a processing request signal REQ0 'to the buffer 24. When the buffer 24 transmits the permission signal ACK0 to the monitoring control unit 27 in response to the processing request signal REQ0 ′, the monitoring control unit 27 receives the permission signal ACK0 and receives the permission signal ACK0 ′ corresponding to the permission signal ACK0. To the interface 26-0.

  In this way, the monitoring control unit 27 controls the timing so that the permission signals ACK0 'and ACK1' are alternately transmitted to the interfaces 26-0 and 26-1.

  For example, as shown in FIG. 5, when the interface 26-0 that should transfer data first transmits the processing request signal REQ0 to the monitoring control unit 27 before the interface 26-1, this pattern is the pattern 1 It corresponds to.

  In this case, the supervisory control unit 27 transmits the permission signal ACK0 ′ to the interface 26-0 according to the pattern 1 shown in FIG. 7A, and the interface 26-0 receives the permission signal ACK0 ′ and receives the chip 10 Start transferring Page1 data to -0. After transmitting the permission signal ACK0 ', the monitoring controller 27 transmits the permission signal ACK1' to the interface 26-1. The interface 26-1 receives the permission signal ACK1 'and starts transferring the data of Page2 to the chip 10-1.

  Next, as shown in FIG. 9, when the interface 26-1 to which data transfer is to be performed later transmits the processing request signal REQ 1 to the monitoring control unit 27 before the interface 26-0, this pattern is It corresponds to 2.

  In this case, the supervisory control unit 27 transmits the permission signal ACK0 'to the interface 26-0 and then transmits the permission signal ACK1' to the interface 26-1 according to the pattern 2 shown in FIG. 7B. The interface 26-0 starts transferring the data of Page1 to the chip 10-0. After the transfer is started, the interface 26-1 starts transferring the data of Page2 to the chip 10-1.

  Next, as shown in FIG. 10, the transferred Page1 data is copied from the register in the chip 10-0 to the memory cell array, and the interface 26-0 to which the Page1 data is transferred is ahead of the interface 26-1. When the processing request signal REQ0 is transmitted again to the monitoring control unit 27, this pattern corresponds to the pattern 3.

  In this case, the monitoring control unit 27 transmits the permission signal ACK1 'to the interface 26-1 and then transmits the permission signal ACK0' to the interface 26-0 according to the pattern 3 shown in FIG. 7C. The interface 26-1 starts transferring Page2 data to the chip 10-1. After this transfer is started, the interface 26-0 starts transferring Page3 data to the chip 10-0.

  In this manner, when the monitoring control unit 27 alternately transmits the permission signals ACK0 ′ and ACK1 ′ to the interfaces 26-0 and 26-1, the data captured in the data holding units 24A to 24C is as follows. In this order, the chips 10-0 and 10-1 of the flash memory 10 are alternately assigned.

Step 1: Data in data holding unit 24A → chip 10-0
Step 2: Data in the data holding unit 24B → chip 10-1.
Step 3: Data in the data holding unit 24C → chip 10-0
Step 4: Data in the data holding unit 24A → chip 10-1.
Step 5: Data in the data holding unit 24B → chip 10-0
...

Next, a process for reading data from the flash memory 10 will be described.
As for the data reading process from the flash memory 10, the monitoring control unit 27 performs the processing request signal and the permission signal according to the patterns 1 to 3 shown in FIGS. And adjust the transmission timing.

The timing for reading data from the flash memory 10 in pattern 2 is shown in FIG.
The interfaces 26-0 and 26-1 sequentially output the command signal C and the address signal A to the flash memory 10, respectively. The command signal C is a command for reading data from the flash memory 10.

  As shown in FIGS. 11A and 11C, the flash memory 10 causes the signal S22 (BUSY_CH1) and the signal S20 (BUSY_CH0) to fall from the H level to the L level as the busy signals, respectively, at time t20. Even when data is read, the L level of the busy signal indicates that processing is in progress, and the H level indicates that the processing is on standby.

  As shown in FIG. 11C, the flash memory 10 raises the signal S22 (BUSY_CH1) to the H level, and the interface 26-1 receives the processing request signal REQ1 as shown by the signal S23 in FIG. Is raised from L level to H level. However, even if the signal S23 (REQ1) rises to the H level, the monitoring control unit 27 waits until the processing request signal REQ0 rises.

  When time elapses, as shown in FIG. 11A, when the flash memory 10 raises the signal S20 (BUSY_CH0) to the H level, as shown by the signal S21 in FIG. 11B, the interface 26-0. Raises the processing request signal REQ0 to H level.

  When the signal S21 (REQ0) rises, the supervisory control unit 27 raises the processing request signal REQ0 'from the L level to the H level as indicated by a signal S24 in FIG.

  When the signal S24 (REQ0 ') rises to the H level, the buffer 24 raises the permission signal ACK0 from the L level to the H level, as indicated by the signal S25 in FIG.

  When the signal S25 (ACK0) rises to the H level, the supervisory control unit 27 raises the permission signal ACK0 'from the L level to the H level as indicated by the signal S26 in FIG.

  When the signal S26 (ACK0 ') rises to H level, the interface 26-0 transfers the data D of the chip 10-0 of the flash memory 10 to the buffer 24 at time t21.

  On the other hand, when the signal S26 (ACK0 ') rises to the H level, the supervisory control unit 27 raises the processing request signal REQ1' from the L level to the H level as indicated by the signal S27 in FIG.

  When the signal S27 (REQ1 ') rises to the H level, the buffer 24 raises the permission signal ACK1 from the L level to the H level, as indicated by the signal S28 in FIG.

  When the signal S28 (ACK1) rises to the H level, the supervisory control unit 27 raises the permission signal ACK1 'from the L level to the H level as indicated by the signal S29 in FIG.

  When the signal S29 (ACK1 ') rises to the H level, the interface 26-1 transfers the data D of the chip 10-1 of the flash memory 10 to the buffer 24 at time t22 (t21 <t22). At such timing, the data reading process in pattern 2 is performed.

  In this manner, the supervisory control unit 27 transmits the permission signals ACK0 'and ACK1' alternately to the interfaces 26-0 and 26-1. Then, if the monitoring control unit 27 first allocates the data of the chip 10-0 of the flash memory 10 to the data holding unit 24A of the buffer 24, the data of the chips 10-0 and 10-1 are as follows. As described above, the data holding units 24A to 24C are assigned.

Step 1: Data of chip 10-0 → data holding unit 24A
Step 2: Data of chip 10-1 → data holding unit 24B
Step 3: Data of chip 10-0 → data holding unit 24C
Step 4: Data of chip 10-1 → data holding unit 24A
Step 5: Data of chip 10-0 → data holding unit 24B
...

  As described above, according to the present embodiment, when the monitoring control unit 27 receives the processing request signals REQ0 and REQ1 from the interfaces 26-0 and 26-1, the processing request signals REQ0 ′ and REQ1 ′ are alternately displayed. The timing is adjusted so that it is transmitted to the buffer 24. Therefore, it is possible to avoid a deviation in processing order in the flash memory.

In carrying out the present invention, various forms are conceivable and the present invention is not limited to the above embodiment.
For example, in the above embodiment, the case where the interfaces 26-0 and 26-1 to the flash memory 10 are configured by two independent buses has been described. However, the number of systems is not particularly limited, and may be configured with three or more systems.

  When three or more interfaces are provided, the monitoring control unit 27 determines the order of data transfer performed between the buffer 24 and each chip, and transmits a permission signal to each interface in order. Then, the supervisory control unit 27 sets the order in which the data transfer with the flash memory 10 is to be performed next as the last data transfer.

  Further, the monitoring control unit 27 may control the transmission timing of the permission signals ACK0 'and ACK1' using a flag. For example, when the flash memory interface 26 has two systems as in the above-described embodiment, the permission signal is transmitted to the one corresponding to the flag value of the interfaces 26-0 and 26-1.

  That is, when the flag value is 0, if the processing request signals REQ0 and REQ1 are sequentially transmitted from the interfaces 26-0 and 26-1, respectively, the monitoring control unit 27 causes the interfaces 26-0 and 26, respectively. −1, permission signals ACK0 ′ and ACK1 ′ are transmitted in order.

  Further, when the flag value is 0, even if the processing request signals REQ1 and REQ0 are sequentially transmitted from the interfaces 26-0 and 26-1, respectively, the monitoring control unit 27 is not connected to the interfaces 26-0 and 26-, respectively. 1, the permission signals ACK0 ′ and ACK1 ′ are transmitted in this order. Even in this case, it is possible to control the data transfer alternately.

1 is a block diagram showing a configuration of a flash memory system according to an embodiment of the present invention. FIG. 2 is an explanatory diagram showing a configuration of a memory cell array of the flash memory of FIG. 1. FIG. 2 is a block diagram illustrating main configurations of a flash memory interface and a flash memory in FIG. 1. FIG. 2 is an explanatory diagram showing signals transmitted and received between the buffer of FIG. 1 and a flash memory interface (monitoring control unit, interface). It is explanatory drawing when a host system supplies data to flash memory at the time of write-in processing. FIG. 10 is an explanatory diagram when a buffer holds data supplied from a host system in a data holding unit when performing a writing process. It is explanatory drawing which shows the operation | movement pattern of a flash memory interface, (a)-(c) shows the patterns 1-3, respectively. It is a timing chart which shows the content of the write-in process in the case of the pattern 2 shown in FIG.7 (b). It is explanatory drawing which shows the specific example of the pattern 2 of FIG.7 (b). It is explanatory drawing which shows the specific example of the pattern 3 of FIG.7 (c). It is a timing chart which shows the content of the read-out process in the case of the pattern 2 of FIG.7 (b).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Host system 10 Flash memory 10-0,10-1 Chip 20 Controller 24 Buffer 26 Flash memory interface 26-0, 26-1 Interface 27 Monitoring control part

Claims (6)

In a memory controller that transfers data to and from multiple flash memories that store data,
A data storage unit for storing data for performing data transfer with the plurality of flash memories;
Between the data storage unit and each flash memory, provided corresponding to each flash memory, transmitting a processing request signal requesting data transfer, receiving a permission signal permitting data transfer, and corresponding A plurality of data transfer units that perform data transfer between the flash memory and the data storage unit;
A plurality of processing request signals transmitted from the plurality of data transfer units are received, and a permission signal in which a transmission timing is set so that data transfer by each data transfer unit is performed in order is sent to each data transfer unit. A transfer control unit for transmitting,
A memory controller characterized by that. Each flash memory performs data input / output in units of pages,
The data storage unit is provided with a plurality of data holding units capable of holding an amount of data corresponding to each page of each flash memory as holding the data to be transferred,
Each of the data holding units is configured such that data is discharged in order from the one supplied with data.
The memory controller according to claim 1. The transfer control unit determines the order of data transfer performed between the data storage unit and each of the flash memories, and the processing request signal from the data transfer unit that is determined to be later is the processing request signal from the first Is received prior to the processing request signal from the data transfer unit determined to be transmitted, the permission signal is transmitted to the data transfer unit determined to be the first in order and data transfer is performed between the corresponding flash memory. The transmission timing of the permission signal to each of the data transfer units is set so that the permission signal is transmitted to the data transfer unit that has been determined to be later.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The transfer control unit has a data transfer unit that has performed data transfer with the flash memory as the last order in which data transfer should be performed,
The memory controller according to claim 1, wherein the memory controller is a memory controller. A plurality of flash memories for storing data;
A memory controller according to any one of claims 1 to 4.
A flash memory system characterized by that. Receiving a processing request signal for requesting data transfer from a plurality of data transfer units provided corresponding to each of the flash memories in order to perform data transfer with a plurality of flash memories storing data; ,
Setting a transmission timing for transmitting a permission signal for permitting the data transfer so that data transfer with each of the flash memories is performed in order;
Transmitting the permission signal to each data transfer unit according to the transmission timing, and
A data transfer method for a flash memory.

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