JP4910426B2 - Non-volatile memory device writing method - Google Patents

Description

  The present invention relates to a method for writing data in a nonvolatile memory device using a semiconductor memory.

  In recent years, a memory card equipped with a non-volatile memory has been expanding its market as a recording medium used in digital cameras and mobile phones. As the storage capacity of the memory card increases, its use has expanded from recording a small volume of data files, still images, etc. to recording a moving image that requires a larger capacity.

  However, NAND-type flash memory, which is mainly used as a non-volatile memory for memory cards, has a physical block capacity of 16KB (mainly flash memory of 128MB or less) as a data erasing unit as its capacity increases. From 128 KB (mainly flash memory of 128 MB or more). Nevertheless, in the file system for writing data to the memory card, the cluster serving as a data writing unit remains 16 KB.

  For that reason, in the former small capacity memory card (mainly capacity up to 128MB), the capacity of the cluster when writing data to the memory card, and the erase unit of the NAND type flash memory installed in the memory card The physical blocks to be equal. However, as capacity increases, non-volatile memory with a capacity value exceeding 128 MB, such as cluster capacity of 16 KB, which is a unit for writing data to the memory card, and NAND mounted inside the memory card The physical block capacity 128 KB, which is an erase unit of the type flash memory, is different.

  FIG. 2 shows the internal structure of the flash memory. The flash memory includes a page buffer 202 and a plurality of physical blocks 201. The page buffer 202 is a buffer that temporarily stores data to be written to and read from the flash memory. The capacity of one physical block 201 consists of a total of 132 KB, which is 128 KB in the data area and 4 KB in the management area. Here, since there are 1024 physical blocks from PB0 to PB1023, the flash memory has a data area capacity of 128 MB (1 Gbit). The physical block 201 is a data erasing unit in the flash memory.

  FIG. 3 is a diagram showing the internal configuration of the physical block 201. The physical block 201 is composed of 64 physical pages 301 of PP0 to PP63. The capacity of one physical page 301 is 2 KB in the data area and 64 B in the management area. The physical page 301 is a data writing unit in the flash memory, and the capacity of the page buffer 202 shown in FIG. 2 is equal to the capacity of the physical page.

  As described above, since the data area of the physical block 201 which is a data erasing unit is 128 KB, even if writing is 16 KB which is a cluster unit, writing of 16 KB and copying of data of 112 KB (128 KB-16 KB) are performed. Writing of 128 KB, which is an erasing unit, was performed. At this time, as a method of copying data, a copy-back function of a NAND type flash memory can be used. This is also described in Patent Document 1. By using the copy back function, there is no need to transfer the data to be copied to the outside of the non-volatile memory, so that there is an advantage that the data can be copied at high speed.

  Data copying using the copy back function will be briefly described with reference to FIGS. FIG. 14 shows the internal configuration of the flash memory. 1401 is a flash memory, 1402 is a page buffer, 1403 and 1404 are physical blocks inside the flash memory 1401, respectively.

  In the state shown in FIG. 6A, data has been written to the physical block 1404 and the physical block 1403 has been erased.

  In FIG. 5B, when overwriting data is written from the outside of the flash memory to the first 2 KB of data already written in the physical block 1403, the data is first stored in the page buffer 1402, and then erased. It is written in the first page PP0 of the physical block, here the physical block 1403.

  In FIG. 6C, when overwriting from outside is only 2 KB, PP0 of the physical block 1404 is invalidated by the data written in PP0 of the physical block 1403, but PP1 to PP63 of the physical block 1404. Is valid data. In order to collect the valid data in one physical block by copying this valid data to the physical block 1403 written in FIG. 5B, the data of PP1 to PP63 of the physical block 1403 is PP1 of the physical block 1404. Copy one page at a time to PP63. FIG. 15 is a timing chart for copying one page at this time.

  In FIG. 15, a control signal indicates a command or address input by a signal line for controlling the flash memory from the outside of the flash memory, and ready / busy indicates data writing to the memory cell of the flash memory or data from the memory cell. A signal output to the outside of the flash memory during the period of reading is indicated as “L”, indicating that the flash memory is busy (data writing / reading). To copy a page, first issue a copy read command at time t1501, and then specify a copy read address. Here, it is assumed that the address of the physical page PP1 of the physical block 1404 is designated. Then, at time t1502, the flash memory reads the data from the physical page PP1 of the physical block 1404 and outputs the data to the page buffer 1402 as a busy period. When busy from the flash memory is canceled, a copyright start command, a copyright address designation, and a copyright execution command are issued from time t1503. The address specified here specifies PP1 of the physical block 1403. At time t1504, the flash memory writes the data in the page buffer 1402 to the physical page PP1 in the physical block 1403. The period required for the writing process is output to the outside as busy. Copying of data for one page is completed at time t1505 when the busy state from the flash memory is released. This process is repeated 63 times to copy data from PP1 to PP63.

  Finally, the data copy processing is completed by physically erasing the physical block 1404 in FIG.

  However, the copy-back function that can output the data to be copied outside the flash memory or can copy the data without inputting the data from the outside cannot be used between different flash memories.

  Data copying that does not use the copyback function will be briefly described with reference to FIGS. FIG. 16 is a diagram showing the internal configuration of the memory card, which includes two flash memories 1604 and 1607 and a controller 1601 that controls the flash memories 1604 and 1607. The controller 1601 has a save buffer 1602 having a capacity of 2 KB + 64 B used for copying data and a page buffer 1603 having a capacity of 2 KB used for reading / writing data from the outside of the memory card. The flash memory 1604 has a page buffer 1605 and a plurality of physical blocks, of which one physical data has already been written as a physical block 1606, and the flash memory 1607 has a page buffer 1608 and a plurality of physical blocks, one of which. The erased physical block is set to 1609.

  In the state shown in FIG. 16A, data has been written to the physical block 1606 and the physical block 1609 has been erased.

  In FIG. 5B, when overwriting data is written from the outside of the memory card to the first 2 KB of data already written in the physical block 1606, the data is first stored in the page buffer 1603, and then the controller 1601. The data is copied from the page buffer 1603 to the page buffer 1608 of the flash memory 1607 and written to the erased physical block, here the first page PP0 of the physical block 1609.

  (C) When the overwriting from the outside is only 2 KB, PP0 of the physical block 1606 is invalidated by the data written in PP0 of the physical block 1609, but PP1 to PP63 of the physical block 1606 are valid. It is a lot of data. In order to copy this valid data to the physical block 1609 written in FIG. 5B and collect valid data in one physical block, the data of PP1 to PP63 of the physical block 1606 is changed to PP1 of the physical block 1609. Copy one page at a time to PP63. FIG. 17 is a timing chart for copying one page at this time.

  In FIG. 17, a control signal indicates a command or address input by a signal line for the controller to control the flash memory, and ready / busy indicates data writing to the memory cell of the flash memory or data reading from the memory cell. The signal output to the controller during the execution period is “L”, indicating that the flash memory is busy (data writing / reading). To copy a page, first issue a read command to the flash memory 1604 at time t1701, and then specify a read address. Here, it is assumed that the address of the physical page PP1 of the physical block 1606 is designated. Then, at time t1702, the flash memory 1604 reads out data from the physical page PP1 of the physical block 1606 and outputs the data transfer period to the page buffer 1605 as busy. When busy from the flash memory 1604 is released, the controller 1601 reads and transfers data from the flash memory 1604 and stores it in the save buffer 1602 from time t1703. Next, at time t1704, a write start command is issued and a write address is designated. The address specified here specifies PP1 of the physical block 1609. Then, data is written and transferred from the save buffer 1602 to the page buffer 1608 of the flash memory 1607, and a write execution command is issued after the transfer is completed. At time t1705, the flash memory 1607 writes the data in the page buffer 1608 to the physical page PP1 in the physical block 1609. The period required for the writing process is output to the outside as busy. Copying of data for one page is completed at time t1706 when the busy state from the flash memory is released. This process is repeated 63 times to copy data from PP1 to PP63.

  Finally, the physical block 1606 is physically erased in FIG. 16D to complete the data copy process.

  When copying data between flash memories in this way, it is necessary to read and transfer data from the flash memory that contains the copy source data to the controller and to write and transfer data from the controller to the copy destination. . Processing time increases.

In addition, the address of the physical block of the flash memory that can use the copyback function in the same flash memory may be limited. Even in that case, in the data copy processing in the same flash memory, it is necessary to read and transfer data from the flash memory to the controller and write and transfer data from the controller to the flash memory. Processing time increases.
JP 2004-30784 A

  In the conventional nonvolatile storage device writing method, can the copyback function be used in the data copy operation using the copyback function performed when writing data smaller than the erase unit of the nonvolatile memory? It was necessary to judge whether.

  In order to solve the above-described problem, a nonvolatile memory device writing method according to the present invention is a nonvolatile memory device writing method including a nonvolatile memory and a controller, and the nonvolatile memory includes a plurality of regions, and The area comprises a plurality of independently erasable physical blocks and at least one volatile memory page buffer, the physical block comprises a plurality of independently writable physical pages, and the non-volatile memory is also When any two physical blocks in the same area are a first physical block and a second physical block, the data read from any physical page of the first physical block to the page buffer is A copy back function for writing to any page of the second physical block, the controller storing non-volatile memory In writing data designating an address from the outside, a first step of determining an area where a physical block in which data corresponding to the address has already been written exists, and an erased data in the determined area Consists of a second step of writing the data to the physical block

  According to the nonvolatile memory device writing method of the present invention, the write destination physical block is searched from a range where the flash memory copy back function can be used, so whether or not the copy back function can be used during data copy. Data can always be copied using the copyback function without making a determination.

  A writing method of the nonvolatile memory device according to the embodiment of the present invention will be described with reference to FIGS.

(Embodiment 1)
FIG. 1 is a block diagram showing a nonvolatile memory device according to Embodiment 1 of the present invention and an external host device connected thereto.

  In FIG. 1, 101 is a non-volatile storage device, and 102 is an external host. The nonvolatile storage device 101 includes 103 controllers and 104 flash memories.

  The flash memory 104 includes two flash memory chips, a 1 Gbit flash memory chip A110 and a 1 Gbit flash memory chip B111. The two flash memory ticks are combined into one package.

  FIG. 2 shows details of the flash memory chip A110. The flash memory chip A110 includes a total of 1024 physical blocks 201, PB0 to PB1023. Each physical block 201 is an erase unit in the flash memory 104, and each capacity has 128 KB (1024 Kbit) as a user data area and 4 KB (32 Kbit) as a management area. FIG. 2 shows only the capacity value of the data area.

  FIG. 3 shows details of the physical block 201. The physical block 201 is composed of a total of 64 physical pages 301 of PP0 to PP63. Each physical page 301 is a writing unit in the flash memory 104, and each capacity has 2 KB (2048 bits) as a user data area and 64 B (512 bits) as a management area.

  The flash memory chip B111 has the same configuration as the flash memory chip A110.

  The flash memory chip A110 and the flash memory chip B111 are sealed in the same semiconductor package. For example, as shown in FIG. 4, the flash memory chip A110 and the flash memory chip B111 are stacked and sealed in one package, or as shown in FIG. 5, the flash memory chip A110 and the flash memory chip B111 Are sealed in a back-to-back state.

  Both the flash memory chip A110 and the flash memory chip B111 have a copy back function, and can copy back from an arbitrary physical block 201 to an arbitrary different physical block 201 in the same flash memory chip. is there. However, copy back to a different flash memory chip, that is, copy back from the flash memory chip A110 to the flash memory chip B111 or copy back from the flash memory chip B111 to the flash memory chip A110 cannot be performed.

  As a result, when the flash memory 104 is considered, the range of the copy destination physical block 201 that can be used by the copy back function is limited by the position of the copy source physical block 201.

  On the other hand, the controller 103 transfers data between the external host 102 and the flash memory 104 from the flash memory 104 to the external host 102 (read operation from the nonvolatile storage device 101) and data from the external host 102 to the flash memory 104. Transfer (write operation to the nonvolatile memory device 101) is controlled. The controller 103 includes a control circuit 105, a page buffer 106, a save buffer 107, an address conversion table 108, and an entry table 109. Here, the control circuit 105 controls the operation of the controller 103.

  The page buffer 106 is configured by a volatile memory for temporarily storing data during data transfer between the external host 102 and the flash memory 104, and the capacity thereof includes at least a unit of user data included in the physical page 301. In the present embodiment, 2 KB which is a unit for writing user data in the flash memory 104 is provided.

  The save buffer 107 temporarily reads user data from a physical page 301 in a physical block 201 in the flash memory 104 and copies the user data to a physical page 301 in a physical block 201 different from the read block. For example, a volatile memory, the capacity of which includes at least a unit of user data included in the physical page 301. In the present embodiment, 2 KB which is a unit for writing user data in the flash memory 104 is provided.

  The address conversion table 108 is a table for converting a logical address designated to the nonvolatile storage device 101 as a target of reading or writing by the external host 102 into a physical address of the flash memory 104. Composed. When a logical address is an address value in the address conversion table, a physical address is stored as data at the address position. In the embodiment of the present invention, a logical address is converted into a physical address in units of physical blocks 201. Therefore, the 11-bit data necessary to designate one of 1024 × 2 physical blocks 201 is the number of physical blocks 201. Therefore, the capacity of the address conversion table 108 is 2.75 KB.

  The entry table 109 is a table for indicating a writable erased block 201 in the flash memory 104, and is configured by a volatile memory. It is necessary to have 1-bit data indicating “1” indicating erased in units of physical blocks 201 or “0” indicating that user data has been written. Therefore, the capacity of the entry table 109 is 1024 × 2 physical blocks 201. The bit capacity is equal to 256B (2048 bits).

  The erased physical block in which data can be written to the flash memory is specified by searching for data “1” in the entry table 109.

  FIG. 6 is a diagram showing the configuration of the entry table 109. An entry table having a capacity of 256 B is composed of 16 bits × 128 words, the range of bits 0 to 7 corresponding to the lower 8 bits corresponds to the flash memory chip A110, and the range of bits 8 to 15 corresponding to the upper 8 bits is the flash memory chip This corresponds to B111.

  Accordingly, the physical block PB0 of the flash memory chip A110 corresponds to bit0 of address 0, and bit0 of address 1 corresponds to the physical block PB8 of flash memory chip A110. The physical block PB1023 of the flash memory chip A110 corresponds to bit7 of address 127.

  By adopting such a configuration of the entry table 109, information on the physical block that can copy data from the physical block corresponding to the lower bits (bits 0 to 7) using the copy back function is the lower order of the entry table 109. The information of the physical block that exists only in the bits and can copy data from the physical block corresponding to the upper bits (bits 8 to 15) using the copy back function exists only in the upper bits of the entry table 109.

  FIG. 7 is a flowchart for determining a physical block as a write destination.

  When the external host 102 designates a logical address and writes data to the nonvolatile storage device 101, the control circuit 105 needs to determine the physical block address of the flash memory 104 to be written.

  First, in step 701, it is necessary to determine a flash memory chip to be written based on a logical address designated by the external host 102. Here, when the logical address designated by the external host 102 is changed to a 128 KB unit address having the same capacity value as the physical block 201, the flash to be written depends on whether the least significant bit is “0” or “1”. Determine the memory chip. When the least significant bit is “0”, the flash memory chip A110 is the flash memory chip to be written, and when the least significant bit is “1”, the flash memory chip B111 is the flash memory chip to be written. As an example, the first 128 KB from the first address “0” of the logical address is written to the flash memory chip A 110, and the next 128 KB is written to the flash memory chip B 111.

  In step 702, an area corresponding to the flash memory chip to be written in the entry table 109 is searched to obtain an erased physical block address. When the flash memory chip to be written is the flash memory chip A110, the erased physical block 201 is searched for only bits 0 to 7 corresponding to the lower 8 bits of the entry table 109. When the flash memory chip to be written is the flash memory chip B111, the erased physical block 201 is searched for only bits 8 to 15 corresponding to the upper 8 bits of the entry table 109.

  Since the flash memory chip to be written to is determined as described above, when copying data of an arbitrary logical address, the logical address of the copy source and the logical address of the copy destination are naturally the same. When the erased physical block 201 that is the write destination is acquired in the write destination determination flow shown in FIG. 7 based on the same logical address, it is naturally in the same flash memory chip, and as a result, data of an arbitrary logical address is stored. It is possible to always perform copy back processing when copying.

  In the above embodiment, FIG. 6 is shown as the configuration of the entry table, but a different configuration can be realized. FIG. 8 shows the configuration of the entry table 109 in a form different from the above embodiment.

  In FIG. 8, an entry table with a capacity of 256 B is configured by 16 bits × 128 words, and the range corresponding to the first 64 words (address 0 to 63) corresponds to the flash memory chip A110, and the latter 64 words (address 64 to 127). ) Corresponds to the flash memory chip B111.

  Therefore, the physical block PB0 of the flash memory chip A110 corresponds to bit0 of address 0, and bit0 of address 1 corresponds to the physical block PB16 of flash memory chip A110. The physical block PB1023 of the flash memory chip A110 corresponds to bit 7 of address 63.

  When the entry table 109 having the configuration shown in FIG. 8 is used, the search method in step 702 applies only to the first 64 words (addresses 0 to 63) of the entry table 109 when the write target flash memory chip is the flash memory chip A110. The erased physical block 201 is searched as follows. When the flash memory chip to be written is the flash memory chip B111, the erased physical block 201 is searched only for the last 64 words (addresses 64 to 127) of the entry table 109.

(Embodiment 2)
In the first embodiment described above, by determining the flash memory chip to be written on the basis of the logical address to be written, the address of the physical block 201 that can be subjected to the copyback process can always be obtained. Even when the flash memory chip to be written is not determined, the erased physical block 201 is preferentially searched from the range of the entry table 109 corresponding to the flash memory chip that can be copied back from the physical block 201 that is the copy source. As a result, the address of the physical block 201 that can always be copied back can be acquired.

  Specifically, description will be made using the write destination determination flow shown in FIG. 9 instead of the flowchart in FIG. 7 in the first embodiment.

  In step 901, based on the logical address to be written, the physical block address where the already written data of the logical address exists is acquired from the address conversion table 108.

  In step 902, an area of the entry table 109 corresponding to a physical block group to which data can be copied from the physical block address acquired in step 901 using the copy back function is determined.

  Finally, in step 903, the erased physical block address is obtained by searching the area determined in step 902.

  Since the flash memory chip to be written to is determined by the above flow, when copying data at an arbitrary logical address, the copy source physical block and the copy destination physical block must always be copied using the copy back function. Can be copied.

  The second embodiment has the same configuration as that of the first embodiment except that the flow for determining the write destination is different.

(Embodiment 3)
In the first embodiment and the second embodiment described above, the case where the copy back function can be used between the physical blocks inside the flash memory chip has been described. However, depending on the type of the flash memory, the physical block inside the flash memory chip In some cases, the copy back function may not be used. The case will be described.

  FIG. 10 is a block diagram showing a nonvolatile memory device according to Embodiment 3 of the present invention and an external host device connected thereto.

  10, the same components as those in FIG. 1 are given the same numbers as those in FIG. The flash memory 1001 and the entry table 1004 are different from FIG. The flash memory 1001 is configured by using two flash memory chips having a limited copy back function between physical blocks in the chip. The flash memory 1001 includes two flash memory chips, a 1 Gbit flash memory chip C1002 and a 1 Gbit flash memory chip D1003, which form two flash memory ticks in one package.

  FIG. 11 shows details of the flash memory chip C1002. The flash memory chip C1002 is composed of a total of 1024 physical blocks 1101 of PB0 to PB1023. Each physical block 1101 is an erasing unit in the flash memory 104, and each capacity has 128 KB (1024 Kbit) as a user data area and 4 KB (32 Kbit) as a management area. The physical block 1101 is divided into a first half physical block of PB0 to PB511 and a second half physical block of PB512 to PB1023. A page buffer 1102 is provided for the first half physical block, and a page is provided for the second half physical block. The buffer 1103 is associated, and the first half physical block can use the copyback function only via the page buffer 1102 between the first half physical blocks, and the second half physical block is the page buffer only between the second half physical blocks. The copy-back function can be used via 1103. The flash memory chip D1103 has the same configuration as the flash memory chip C1002.

  FIG. 12 shows the configuration of the entry table 1004 again. The configuration of the entry table 1004 is similar to that of FIG. However, in FIG. 6, the entry table is divided into two areas of lower bits (bits 0 to 7) and upper bits (bits 8 to 15) by the flash memory chip, but in FIG. 12, the flash memory lower bits (bits 0 to 7) and In addition to the distinction between the upper bits (bits 8 to 15), the former group (Address 0 to 63) and the latter group (Address 64 to 127) can be distinguished. As a result, the PB0 to 511 of the flash memory chip C1102 are represented by the lower bits (bit0 to 7). ) In the first half group (Address 0 to 63). The PBs 512 to 1023 of the flash memory chip C1102 are the lower half bits (bits 0 to 7) and the latter half group (Addresses 64 to 127). PB0 to 511 of the flash memory chip D1103 are areas of the first half group (Address 0 to 63) in the upper bits (bits 8 to 15). The PBs 512 to 1023 of the flash memory chip D1103 are the high-order bits (bits 8 to 15) and the latter half group (Addresses 64 to 127). It is divided into four areas.

  In the configuration of such an entry table 1004, in step 701 of the flowchart of FIG. 7, in the first embodiment, the entry table area is selected and determined from two areas. Select and decide.

  Further, in step 902 of the flowchart of FIG. 9, the entry table area selected from two areas in the second embodiment is selected and determined, but in this embodiment, it is selected from four areas and determined.

  By doing so, even if the physical block area where the copyback function can be used is limited in the flash memory chip, the data must be copied from the copy source physical block using the copyback function. Since the destination physical block is determined, when copying data at an arbitrary logical address, the copy source physical block and the copy destination physical block can always be copied using the copy back function. Become.

(Embodiment 4)
In the first to third embodiments described above, the case where a plurality of flash memory chips are targeted has been described. However, when the copyback function cannot be used between physical blocks inside the flash memory chip, a single flash memory is used. The concept of the present invention can also be applied to a chip. The case will be described.

  FIG. 13 is a block diagram showing a nonvolatile memory device according to Embodiment 3 of the present invention and an external host device connected thereto.

  In FIG. 13, the same reference numerals as those in FIG. The flash memory 1301, the entry table 1303, and the address conversion table 1304 are different from FIG. The flash memory 1301 is configured by using one flash memory chip with a limited copy back function between physical blocks inside the chip. The flash memory 1301 has a 1 Gbit flash memory chip C1302 therein.

  The details of the flash memory chip C1002 are the same as those shown in FIG.

  Although not specifically shown, the entry table 1304 is the same as that obtained by extracting only the lower bits (bits 0 to 7) of FIG. The entry table 1304 is divided into two areas: a first half group (Address 0 to 63) corresponding to the physical blocks PB0 to 511 and a second half group (Address 64 to 127) corresponding to the physical blocks PB512 to 1023.

  By applying step 701 in the flowchart in FIG. 7 and step 902 in the flowchart in FIG. 9 in the configuration of the entry table 1303, the physical block area in which the copyback function can be used in the flash memory chip is limited. Even if the data is copied, the copy destination physical block is determined from the area where data can be copied using the copy back function from the copy source physical block. Data can be copied between the original physical block and the copy destination physical block by using the copy back function.

  As described above, according to the embodiment of the present invention, the erased physical block 201 is preferentially searched from the entry table in the area corresponding to the physical block 201 within the copy-capable range from the copy source physical block 201. By doing so, the physical block 201 capable of copy back processing can be selected as a write target. Further, by limiting the address range of the physical block 201 to be written by the logical address, it is possible to select the physical block 201 that can be reliably copied back as the write target.

  As described above, the writing method of the nonvolatile storage device according to the present invention is a writing method used for a storage device that stores data of a device that handles music data or video data, for example, a portable device such as a digital camera or a digital video camera. Suitable for use.

The block diagram which shows the structure of the non-volatile memory | storage device and host apparatus which perform the writing method by Embodiment 1 of this invention Conceptual diagram showing details of flash memory in the same writing method Conceptual diagram showing details of physical block of flash memory in the same writing method Conceptual diagram showing the package configuration of the flash memory in the same writing method Conceptual diagram showing the package configuration of the flash memory in the same writing method Conceptual diagram showing the structure of the entry table in the writing method Flow chart for determining the write destination in the write method Conceptual diagram showing a different configuration example of the entry table in the writing method Flow chart for determining the write destination in the write method The block diagram which shows the structure of the non-volatile memory | storage device and host apparatus which perform the writing method by Embodiment 3 of this invention Conceptual diagram showing details of flash memory in the same writing method Conceptual diagram showing the structure of the entry table in the writing method The block diagram which shows the structure of the non-volatile memory device and host apparatus which perform the writing method by Embodiment 4 of this invention Schematic diagram showing the data copy operation in the flash memory chip Schematic diagram showing the data copy operation in the flash memory chip Schematic diagram showing the data copy operation in the flash memory chip Schematic diagram showing the data copy operation in the flash memory chip Timing chart of data copy in the flash memory chip Schematic diagram showing data copy operation between flash memory chips Schematic diagram showing data copy operation between flash memory chips Schematic diagram showing data copy operation between flash memory chips Schematic diagram showing data copy operation between flash memory chips Timing chart for copying data between flash memory chips

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Nonvolatile memory | storage device 102 External host 103 Controller 104 Flash memory 105 Control circuit 106 Page buffer 107 Saving buffer 108 Address conversion table 109 Entry table 110 Flash memory chip A
111 Flash memory chip B
201 physical block 202 page buffer 301 physical page 1001 flash memory 1002 flash memory chip C
1003 Flash memory chip D
1004 Entry table 1101 Physical block 1102, 1103 Page buffer 1301 Flash memory 1302 Flash memory chip C
1303 Entry table 1304 Address translation table 1401 Flash memory 1402 Page buffer 1403 and 1404 Physical block 1601 Controller 1602 Evacuation buffer 1603 Page buffer 1604 and 1607 Flash memory 1605 and 1608 Page buffer 1606 and 1609 Physical block

Claims (12)

  A non-volatile memory and a controller for controlling the non-volatile memory, a non-volatile memory device writing method comprising:
The nonvolatile memory is
  It consists of a plurality of areas, and the area has a plurality of physical blocks that are erasing units of information,
  The physical block includes a plurality of physical pages that are units for writing information,
  In the area, page data can be copied from an arbitrary physical page of a physical block to an arbitrary physical page of another physical block in the area.
  A first step in which the controller receives an instruction to partially rewrite data already stored in the nonvolatile memory from the outside;
  A second step in which the controller detects an area in which the received data to be rewritten is stored;
  A third step in which the controller writes the data to a writable physical block among the physical blocks in the detected area;
A writing method of a nonvolatile memory device. The third step writes the data to the writable physical block based on the page data for rewriting included in the partial rewriting instruction of the data and the page data included in the already stored data.
The writing method of the nonvolatile memory device according to claim 1. The nonvolatile memory has at least two nonvolatile memory chips, and the nonvolatile memory chip is the area.
The writing method of the nonvolatile memory device according to claim 1. The nonvolatile memory comprises two nonvolatile memory chips as one package.
The writing method of the non-volatile memory device according to claim 3. The nonvolatile memory is composed of one nonvolatile memory chip, the inside of the nonvolatile memory chip is divided into a plurality of areas, and the divided area is defined as the area.
The writing method of the nonvolatile memory device according to claim 1. The instruction to partially rewrite the data already stored in the nonvolatile memory is an addressing of arbitrary page data with respect to the data already stored in the nonvolatile memory from the outside,
The second step detects the area by an address designated from the outside.
The writing method of the nonvolatile memory device according to claim 1. A nonvolatile memory and a controller for controlling the nonvolatile memory,
The nonvolatile memory is
  It consists of a plurality of areas, and the area has a plurality of physical blocks that are erasing units of information,
  The physical block includes a plurality of physical pages that are units for writing information,
  In the area, page data can be copied from an arbitrary physical page of a physical block to an arbitrary physical page of another physical block in the area.
The controller is
  Receiving means for receiving an instruction to rewrite part of the data already stored in the nonvolatile memory from the outside;
  Detecting means for detecting an area in which the received data to be rewritten is stored;
  Writing means for writing the data to a writable physical block among physical blocks in the detected area;
Non-volatile storage device. The writing means includes
  Based on page data for rewriting included in a partial data rewriting instruction and page data included in the already stored data, the data is written to the writable physical block.
The nonvolatile memory device according to claim 7. The nonvolatile memory has at least two nonvolatile memory chips, and the nonvolatile memory chip is the area.
The nonvolatile memory device according to claim 7. The nonvolatile memory comprises two nonvolatile memory chips as one package.
The non-volatile memory device according to claim 9. The nonvolatile memory is composed of one nonvolatile memory chip, the inside of the nonvolatile memory chip is divided into a plurality of areas, and the divided area is defined as the area.
The nonvolatile memory device according to claim 7. The instruction to partially rewrite the data already stored in the nonvolatile memory is an addressing of arbitrary page data with respect to the data already stored in the nonvolatile memory from the outside,
The detection means detects the area by an address designated from the outside.
The nonvolatile memory device according to claim 7.

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