JP4213140B2 - Memory controller, flash memory system, and flash memory control method - Google Patents

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed and is widely used as a storage medium for information devices such as digital cameras.

  A memory controller is used to control access to the flash memory by information equipment. The flash memory has different access specifications (capacity, block size, data width, cell structure, read speed, etc.) depending on the type, so a memory controller corresponding to the specification of each type is required.

  If the memory controller is developed separately for each type of flash memory, there is a situation where the development of the memory controller cannot catch up with the diversification of the flash memory.

For this reason, a memory controller has been proposed that can identify the type of flash memory and control access to the flash memory with specifications corresponding to the type (see, for example, Patent Document 1). In many cases, such a memory controller reads identification information included in a flash memory. Then, device information corresponding to the identification information of the flash memory is acquired from the device information stored in the ROM provided in the memory controller, and access to the flash memory is controlled with specifications according to the acquired device information. To do.
Japanese Patent Laid-Open No. 10-336562

  However, when a new type of flash memory is developed, device information corresponding to the type may not be stored in the ROM of the memory controller. On the other hand, every time a new flash memory is developed, a countermeasure to replace the ROM can be considered, but it is very complicated to execute this.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory controller capable of handling a new flash memory, a flash memory system including the memory controller, and a flash memory control method.

  A memory controller according to a first aspect of the present invention is a memory controller that executes access to a flash memory by controlling the flash memory in response to a command from a host system that uses the flash memory as a storage medium. A flash memory interface means for executing access to the flash memory according to a specification determined by the set device information, and a read-only storage element, the device associated with the type of the flash memory A first device information storage means for storing information in advance; a second device information storage means for storing rewritable and nonvolatile storage elements in association with the type of the flash memory; The flash memory to be controlled has Type identification information acquisition means for acquiring type identification information, and device information corresponding to the type identification information acquired by the type identification information acquisition means are the first device information storage means or the second device information storage means. And device information setting means for setting the acquired device information in the flash memory interface means.

  The second device information storage means stores device information corresponding to a type of flash memory that is not stored in the first device information storage means, and the device information setting means includes the type identification information acquisition means. When device information corresponding to the acquired product type identification information is recorded in the first device information storage unit, the device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is stored in the first device information. If the device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is not recorded in the first device information storage unit, the product type identification information acquisition unit Acquires device information corresponding to the product type identification information acquired from the second device information storage means, and acquires the acquired device information. The chair information may be set to the flash memory interface unit.

  The first device information storage unit and the second device information storage unit store first device information including at least minimum device information among device information defining specifications for accessing the flash memory. And the flash memory stores, in a predetermined memory area, second device information not included in the first device information among device information, and the flash memory interface means includes the device information setting means. Accessing the flash memory with a specification determined by the first device information set by the first device information, reading the second device information from a predetermined memory area of the flash memory, and supplying the second device information to the device information setting means, The device information setting means is the flash memory interface. The second device information read by the scan unit may be set to the flash memories interface means.

  The first device information storage means and the second device information storage means store essential device information that is minimum device information among device information defining specifications for accessing the flash memory, The flash memory stores arbitrary device information that is not included in the essential device information in device information in a predetermined memory area, and the flash memory interface unit is set by the device information setting unit. Accessing the flash memory with a specification determined by information, reading the arbitrary device information from a predetermined memory area of the flash memory, and supplying the device information setting means to the device information setting means, wherein the device information setting means comprises the flash memory interface means Read by The arbitrary device information may be set to the flash memory interface unit that.

  A flash memory system according to a second aspect of the present invention includes a memory controller having at least one of the above characteristics and a flash memory.

  A flash memory control method according to a third aspect of the present invention includes a type identification information acquisition step for acquiring type identification information for specifying a type of the flash memory from the flash memory, and a read-only storage element. Whether the device information corresponding to the product type identification information acquired in the product type identification information acquisition step is stored in the first device information storage unit that stores device information associated with the product type of the flash memory in advance. A rewritable and non-volatile storage element when it is determined that it is not stored in the first determination step and the first determination step, and device information is stored in the flash memory type Stored in association with the second device information storage means, acquired in the type identification information acquisition step In the second determination step for determining whether device information corresponding to the species identification information is stored, and in the first determination step or the second determination step, the type identification information acquisition step acquires the device information. When it is determined that device information corresponding to product type identification information is stored, the product type identification acquired in the product type identification information acquisition step from the first device information storage unit or the second device information storage unit A device information acquisition step for acquiring device information corresponding to the information, and a device information setting step for setting the device information acquired in the device information acquisition step in an interface means for accessing the flash memory. It is characterized by that.

  According to the present invention, the memory controller includes a rewritable nonvolatile storage medium, and device information corresponding to the new flash memory is stored in the nonvolatile storage medium. Therefore, the memory controller, the flash memory system, and the flash memory control method of the present invention can be applied to a new flash memory.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (Error Collection Code) block 11, and a ROM (Read Only Memory) 12. And an FRAM (Ferroelectric Random Access Memory) 15. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 according to the program recorded in the ROM 12. For example, the microprocessor 6 controls each unit to execute a device information setting process for setting device information corresponding to the type of the flash memory 2 when the flash memory system 1 is activated.

  The host interface block 7 exchanges data, address information, status information, external command information, and the like with the host system 4. That is, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, the data supplied from the host system 4 to the flash memory system 1 is taken into the controller 3 through the host interface block 7 and the data supplied from the flash memory system 1 to the host system 4 is The host interface block 7 is supplied to the host system 4 as an exit.

  More specifically, the host interface block 7 is a command register that temporarily stores a host address and an external command supplied from the host system 4, a sector number register that stores the size of data to be written or read, and a write or read command. An LBA (Logical Block Addressing) register for storing an address of data to be executed. Information is exchanged with the host system 4 via these registers.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2.

  The flash memory interface block 10 exchanges data, address information, status information, internal command information, and the like with the flash memory 2 via the internal bus 14. The flash memory interface block 10 is set with device information such as a block size, a data width, a cell structure, a reading speed, and a storage capacity, thereby enabling access to various types of flash memories 2. .

The device information will be briefly described below.
The block size is device information that defines the size of a block that is a data erasing unit in the flash memory 2, and for example, a small block (S) and a large block (L) can be set.
The data width is device information that defines the number of bits of data that can be transmitted and received by the flash memory 2 via the internal bus 14, and can be set to, for example, 8 bits and 16 bits.
The cell structure is device information that defines the structure of the memory cells constituting the flash memory 2, and for example, a single level cell (SL) and a multilevel cell (ML) can be set.
The read speed is device information that defines the speed at which data written in the flash memory 2 is read (more specifically, the pulse cycle of the read enable signal). For example, 30 ns and 50 ns can be set as the reading speed.
The storage capacity is device information that defines the storage capacity of the flash memory 2, and can be set to 32 Mb, 64 Mb, 128 Mb, for example.

  Further, the flash memory interface block 10 sends a device ID read command to the flash memory 2 under the control of the microprocessor 6 when the flash memory system 1 is activated. In response to this, the device ID (manufacturer code, device code, and extension code) output from the flash memory 2 is received and supplied to the microprocessor 6.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element, and stored data cannot be rewritten. The ROM 12 stores a program that defines the procedure of processing performed by the microprocessor 6. The ROM 12 stores, for example, a program that defines a device information setting process procedure to be described later.

  In addition to the above program, the ROM 12 stores a first device information table in which device information that needs to be set when accessing the flash memory 2 is associated with the type of the flash memory 2. As shown in FIG. 3, the first device information table is associated with the type of the flash memory 2 and is the minimum device information necessary for accessing the flash memory 2. The block size and data width And the cell structure.

  Here, if only the minimum device information is known, the storage capacity and read speed, which are optional device information not included in this, can be set to the flash memory 2 by setting the following temporary values. Access is possible. That is, the minimum capacity value is set as the storage capacity, and the minimum reading speed is set as the reading speed. At this time, the memory space accessible by the controller 3 is a memory space corresponding to the minimum capacity value among the memory spaces of the flash memory 2. Even when a flash memory 2 of a type capable of reading at a higher speed is connected, the lowest reading speed is obtained.

  The FRAM 15 is a non-volatile storage medium, and can rewrite stored data or add data. As shown in FIG. 3, the FRAM 15 stores a second device information table that records information of the same type as the first device information table stored in the ROM 12. The second device information table is updated by the host system 4 when, for example, a new flash memory 2 is developed or when error information is notified in a device information setting process described later.

The flash memory 2 cannot be accessed efficiently with only the minimum device information stored in the first or second device information table. In general, in order to efficiently access the flash memory 2, in addition to the above-mentioned minimum device information, device information such as the storage capacity and read speed of the flash memory 2 is required. In the device information setting process described later, the controller 3 according to the present embodiment reads device information other than the minimum device information from a predetermined page of the flash memory 2, resets the read device information, and thereafter Execute access.
Note that, even for device information other than the minimum device information, the storage capacity uniquely determined based on the device code may be stored in the first and second device information tables.

[Description of flash memory]
Next, the flash memory 2 will be described. As shown in FIG. 2, the flash memory 2 includes a memory unit 21 that is a storage area used by the host system 4 and a device ID holding unit 22 that holds a device ID for identifying the type of the flash memory 2. Composed.

  FIG. 4 is a diagram schematically showing the memory structure of the memory unit 21. As shown in FIG. 4, the flash memory 2 is composed of a page which is a processing unit for reading and writing data and a block which is a data erasing unit.

  The page is composed of a 512-byte user area 25 and a 16-byte redundant area 26, for example. The user area 25 is an area for mainly storing data supplied from the host system 4, and the redundant area 26 is an area for storing additional information such as an error collection code and a block status.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25 and is generated by the ECC block 11. Based on the error collection code, if the number of errors included in the data stored in the user area 25 is equal to or less than a predetermined number, the error is corrected.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  The flash memory 2 stores device information (in this embodiment, storage capacity and read speed) other than the minimum device information necessary for accessing the flash memory 2 in a predetermined page of the memory unit 21. That is, device information that is not stored in the first and second device information tables is stored in a predetermined page of the memory unit 21. The device information is read by the controller 3 when the flash memory system 1 is activated.

  The device ID holding unit 22 holds a manufacturer code, a device code, and an extension code for specifying the type of the flash memory 2. When the flash memory 2 receives the device ID read command from the controller 3, in response to this, the flash memory 2 supplies the device ID stored in the device ID holding unit 22 to the controller 3 via the internal bus 14.

  Next, the operation of the flash memory system 1 configured as described above will be described.

[Description of startup operation]
When the flash memory system 1 is activated, the controller 3 executes device information setting processing for setting device information corresponding to the type of the flash memory 2.

Hereinafter, the procedure of the device information setting process will be described with reference to the flowchart shown in FIG.
The device information setting process is started when the flash memory system 1 is turned on.

  When the device information setting process is started, the microprocessor 6 of the controller 3 controls the flash memory interface block 10 to send a device ID read command to the flash memory 2 and output from the flash memory 2 in response thereto. Device code (device code included in the device ID) is acquired (step S100).

  Next, the microprocessor 6 searches the first device information table stored in the ROM 12 and determines whether or not there is device information corresponding to the device code acquired in step S100 (step S110).

  If there is device information corresponding to the acquired device code in the first device table (step S110; Yes), the microprocessor 6 advances the process to step S140.

  On the other hand, when there is no device information corresponding to the acquired device code in the first device table (step S110; No), the microprocessor 6 searches the second device information table stored in the FRAM 15 and performs step S100. It is determined whether or not there is device information corresponding to the device code acquired in step S120.

  If there is device information corresponding to the acquired device code in the second device table (step S120; Yes), the microprocessor 6 advances the process to step S140.

  On the other hand, when there is no device information corresponding to the acquired device code in the second device table (step S120; No), the microprocessor 6 connects the flash memory connected via the host interface block 7 and the external bus 13. Error information indicating that 2 is an unsupported product type is notified to the host system 4 (step S130), and the device information setting process is terminated.

  The host system 4 that has received the error information may acquire the device information corresponding to the flash memory 2 and update the second device information table in response to the error information.

  When there is device information corresponding to the acquired device code in the first or second device information table, the microprocessor 6 corresponds to the device code from the first or second device information table in step S140. Device information is acquired (step S140). The device information acquired at this time includes the minimum device information (block size, data width, and cell structure) necessary for accessing the memory unit 21 of the flash memory 2. That is, the first and second device information tables store at least device information necessary for accessing the memory unit 21 of the flash memory 2.

  Next, the microprocessor 6 sets the acquired minimum device information in the flash memory interface block 10. In addition, the device information defining the reading speed is set to be the lowest reading speed, and the storage capacity is set to the minimum storage capacity (step S150). At this time, the read speed and storage capacity to be set are provisional set values. In the case where the storage capacity is stored in the first and second device information tables, the storage capacity is set to a value stored in the device information table.

  Next, the microprocessor 6 receives device information (reading speed and storage capacity) other than the minimum device information from a predetermined page of the memory unit 21 of the flash memory 2 via the flash memory interface block 10 and the internal bus 14. Is read (step S160). Then, the microprocessor 6 resets the read device information in the flash memory interface block 10 (step S170), and ends the device information setting process.

  When the device information is appropriately set by the device information setting process, the controller 3 controls the subsequent access to the flash memory 2 based on the set device information.

  As described above, since the flash memory system 1 according to the present embodiment includes the nonvolatile storage medium (FRAM 15) that can add device information to the controller 3, a new product type can be used without updating the ROM 12. Can be used.

  Also, in the flash memory system 1 of the present embodiment, the device information stored in the first or second device information table is limited to the minimum necessary device information, and other device information is stored in the flash memory 2 in a predetermined manner. Read from the page. For this reason, the storage capacity per type of flash memory in the ROM 12 and the FRAM 15 can be minimized. From another point of view, the ROM 12 and the FRAM 15 having a certain storage capacity can cope with the most types of flash memories.

  In the above embodiment, the case where only the minimum device information is stored in the first or second device information table has been described as an example, but other device information is stored in the first or second device information table. May also be stored. In this case, in the device information setting process, the procedure for acquiring other device information recorded on a predetermined page of the flash memory 2 can be omitted.

  In the above embodiment, the case where the first device information table is provided in the ROM and device information corresponding to a known type of flash memory is stored in advance has been described as an example. However, the device information for all types may be recorded in the second device information table of the FRAM without providing the first device information table in the ROM.

  In the above-described embodiment, the case where the memory controller includes the FRAM as a nonvolatile storage medium that stores the second device information table has been described as an example. However, the nonvolatile storage medium is not limited to the FRAM. For example, it may be configured by an MRAM (Magnetoresistive Random Access Memory), a hard disk, or the like.

1 is a block diagram schematically showing a flash memory system according to the present invention. It is a block diagram which shows the structure of flash memory. It is a figure which shows the format of the 1st and 2nd device information table. It is a figure which shows roughly the memory structure of the memory part of flash memory. It is a flowchart for demonstrating the procedure of a device information setting process.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 15 FRAM
21 Memory Unit 22 Device ID Holding Unit 25 User Area 26 Redundant Area

Claims (6)

A memory controller that executes access to the flash memory by controlling the flash memory in response to an instruction from a host system that uses the flash memory as a storage medium,
Flash memory interface means for executing access to the flash memory in a specification determined by the set device information;
A first device information storage means, which is a read-only storage element and stores in advance device information associated with the type of flash memory;
A rewritable and non-volatile storage element that stores device information in association with the type of the flash memory;
Product type identification information acquisition means for acquiring product type identification information of the flash memory to be controlled;
Device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is acquired from the first device information storage unit or the second device information storage unit, and the acquired device information is stored in the flash memory. Device information setting means for setting in the interface means,
A memory controller characterized by that. The second device information storage means stores device information corresponding to a type of flash memory that is not stored in the first device information storage means,
When the device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is recorded in the first device information storage unit, the device information setting unit acquires the product type identification information acquisition unit. The device information corresponding to the product type identification information is acquired from the first device information storage unit, and the device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is the first device information storage unit. If not recorded in the means, device information corresponding to the product type identification information acquired by the product type identification information acquisition unit is acquired from the second device information storage unit, and the acquired device information is acquired by the flash memory interface unit. Set to
The memory controller according to claim 1. The first device information storage unit and the second device information storage unit store first device information including at least minimum device information among device information defining specifications for accessing the flash memory. Remember,
The flash memory stores, in a predetermined memory area, second device information that is not included in the first device information among device information,
The flash memory interface means accesses the flash memory with a specification determined by the first device information set by the device information setting means, and obtains the second device information from a predetermined memory area of the flash memory. Read and supply to the device information setting means,
The device information setting means sets the second device information read by the flash memory interface means in the flash memory interface means;
The memory controller according to claim 1, wherein the memory controller is a memory controller. The first device information storage means and the second device information storage means store essential device information that is minimum device information among device information defining specifications for accessing the flash memory,
The flash memory stores arbitrary device information not included in the essential device information in device information in a predetermined memory area,
The flash memory interface means accesses the flash memory with a specification determined by the essential device information set by the device information setting means, reads the arbitrary device information from a predetermined memory area of the flash memory, and reads the device To the information setting means,
The device information setting means sets the arbitrary device information read by the flash memory interface means in the flash memory interface means;
The memory controller according to claim 1, wherein the memory controller is a memory controller.   A flash memory system comprising: the memory controller according to claim 1; and a flash memory. A type identification information acquisition step for acquiring type identification information for identifying the type of the flash memory from the flash memory;
Corresponding to the product type identification information acquired in the product type identification information acquisition step in a first device information storage means, which is a read-only storage element that prestores device information associated with the product type of the flash memory. A first determination step of determining whether or not device information to be stored is stored;
A second device information storage that is a rewritable and non-volatile storage element that stores device information in association with the type of the flash memory when it is determined that it is not stored in the first determination step. A second determination step of determining whether or not device information corresponding to the type identification information acquired in the type identification information acquisition step is stored in the means;
In the first determination step or the second determination step, when it is determined that device information corresponding to the product identification information acquired in the product identification information acquisition step is stored, the first device information storage unit Alternatively, a device information acquisition step for acquiring device information corresponding to the type identification information acquired in the type identification information acquisition step from the second device information storage unit;
A device information setting step for setting the device information acquired in the device information acquisition step in an interface means for accessing the flash memory,
A method for controlling a flash memory.

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