JP4710918B2 - MEMORY CONTROLLER, FLASH MEMORY SYSTEM HAVING MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD - Google Patents

Description

  The present invention relates to a memory controller, a flash memory system including the memory controller, and a flash memory control method.

  In an information storage device (flash memory system) using a flash memory as a storage medium, data other than user data given together with an access instruction from a host system is often written to the flash memory. Examples of data other than user data written to the flash memory include information necessary for managing user data such as an address conversion table (management information) and firmware of a controller that controls access to the flash memory. For example, Patent Document 1 discloses a technique for writing firmware into a flash memory. Patent Document 2 discloses a technique for writing an address conversion table indicating a correspondence relationship between a logical block and a physical block into a flash memory.

JP 2004-280287 A JP 2001-142774 A

  By the way, in order to improve the access speed from the host system to the flash memory system, there is known a flash memory system which includes a plurality of flash memories and can access these flash memories in parallel or in an interleaved manner. Yes. In such a flash memory system, for example, a virtual block is formed by a plurality of physical blocks belonging to different flash memories, and a logical block is allocated to the virtual block. In this case, the number of user data blocks (physical blocks that can be used as user data write destinations) included in each flash memory is preferably equal.

  Even when the virtual block as described above is not formed, if a logical area of the same capacity is allocated to each flash memory, the user data block included in each flash memory The number is preferably equal.

  Accordingly, an object of the present invention is to provide a technique for managing storage areas so that the number of user data blocks included in each flash memory is equal.

A memory controller according to a first aspect of the present invention is a memory controller that controls access to a plurality of flash memories to be erased in physical block units in accordance with an access instruction given from a host system,
Counting means for counting the number of defective blocks included in each of the flash memories;
System block management means for allocating some physical blocks in the plurality of flash memories to system blocks in which system data for controlling or managing access to the plurality of flash memories is written;
System data writing means for writing the system data into one or a plurality of the system blocks as one data or divided into a plurality of data;
System data reading means for reading the system data from the system block;
Access control means for controlling access to the plurality of flash memories based on the system data;
Is provided. The system block management means assigns the system blocks so that the sum of the number of defective blocks and the number of system blocks included in each flash memory is equalized.

  In a preferred embodiment, the system data includes firmware for controlling access to the plurality of flash memories. The system data reading means reads the firmware from the system block at startup.

  In a preferred embodiment, the access control means controls access to the plurality of flash memories in a group unit including a plurality of physical blocks belonging to different flash memories.

  In a preferred embodiment, when the number of defective blocks included in a plurality of the flash memories is changed, the system block management unit is configured to determine the number of defective blocks and the number of system blocks included in each of the flash memories. The allocation of the system blocks is changed so that the sum of the system blocks is equalized.

  A flash memory system according to a second aspect of the present invention includes the above-described memory controller and a plurality of flash memories accessed by the memory controller.

A control method according to a third aspect of the present invention is a method for controlling a plurality of flash memories that are erased in units of physical blocks in accordance with an access instruction given from a host system,
A counting step for counting the number of defective blocks included in each of the flash memories;
A system block management step for allocating some physical blocks in the plurality of flash memories to system blocks in which system data for controlling or managing access to the plurality of flash memories is written;
A system data writing step of writing the system data into one or a plurality of system blocks as one data or divided into a plurality of data;
A system data read step for reading the system data from the system block;
An access control step for controlling access to the plurality of flash memories based on the system data;
Is provided. In the system block management step, the system blocks are allocated so that the sum of the number of defective blocks and the number of system blocks included in each flash memory is equalized.

  The number of user data blocks included in each flash memory can be made equal.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to an embodiment of the present invention.

As shown in FIG. 1, the flash memory system 1 is composed of two flash memories 2A and 2B and a memory controller 3 for controlling the flash memories 2A and 2B. The number of flash memories may be greater than two (for example, preferably 2 ^m (m is a natural number)). In the following description, the two flash memories 2A and 2B may be collectively referred to as “flash memory 2”.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 is composed of a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  As shown in FIG. 1, the memory controller 3 includes a microprocessor 6, a host interface block 7, an SRAM 8, a buffer 9, a flash memory interface block 10, an ECC (Error-correcting code) block 11, and a ROM ( Read Only Memory) 12. The memory controller 3 is connected to the flash memory 2 via the internal bus 14. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, each functional block will be described.

  The host interface block 7 exchanges data, address information, status information, external commands and the like with the host system 4. The external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  An SRAM (Static Random Access Memory) 8 is a volatile storage element and is used as an area for storing firmware or an area for temporarily storing data necessary for controlling the flash memory 2. . For example, as shown in FIG. 2, a firmware area A in which a program code read by the microprocessor 6 is stored, a firmware area B in which a sequence code read by the flash memory interface block 10 is stored, an address conversion table and an empty block search A work area in which a table or the like is held is allocated on the SRAM 8. Here, the address conversion table is a table showing the correspondence between logical blocks and physical blocks, and the free block search table is an erased physical block (or a physical block in which valid data is not stored). This is a table for searching.

  The ROM 12 is a non-volatile storage element, and in this embodiment, only the minimum program code and sequence code required at the time of activation are stored. All program codes and sequence codes necessary for controlling the flash memory 2 are stored in the flash memory 2. Accordingly, all program codes and sequence codes necessary for controlling the flash memory 2 are read from the flash memory 2 and stored in the firmware area on the SRAM 8 at the time of activation. In other words, the ROM 12 stores the program code and sequence read by the microprocessor 6 and the flash memory interface block 10 until the program code and sequence code read from the flash memory 2 are stored in the firmware area on the SRAM 8. Only the code is stored.

  In the case where all program codes and sequence codes necessary for controlling the flash memory 2 are stored in the ROM 12, a firmware area may not be allocated on the SRAM 8.

  The buffer 9 temporarily holds data given from the host system 4 or data read from the flash memory 2. For example, data written to the flash memory 2 is held in the buffer 9 until the flash memory 2 is in a writable state. The data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data.

  The flash memory interface block 10 executes various processes for the flash memory 2 according to the sequence code read from the firmware area B on the SRAM 8 or the ROM 12. In this process, data, address information, status information, internal commands, etc. are exchanged between the flash memory interface block 10 and the flash memory 2 via the internal bus 14. Here, the internal command is a command for the memory controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the memory controller 3.

  The ECC block 11 generates an error correction code (ECC) added to the data to be written to the flash memory 2 and reads the read data based on the error correction code added to the read data. Detect and correct errors contained in.

  The microprocessor 6 controls the entire operation of the memory controller 3 in accordance with the program code read from the firmware area A on the SRAM 8 or the ROM 12.

  Each of the flash memories 2A and 2B is a NAND flash memory. The NAND flash memory includes a register and a memory cell array in which a plurality of memory cells are two-dimensionally arranged. The memory cell array includes a plurality of memory cell groups and word lines. Here, the memory cell group is a group in which a plurality of memory cells are connected in series. Each word line is for selecting a specific memory cell in the memory cell group. Data is written from the register to the selected memory cell or data is read from the selected memory cell to the register between the selected memory cell and the register via the word line. Each flash memory 2A, 2B inputs an internal command or the like while data is written from the register to the memory cell, data is read from the memory cell to the register, or data stored in the memory cell is being erased. Is in a busy state.

  In the NAND flash memory, data reading and writing are performed in units of pages (physical pages), and data erasing is performed in units of blocks (physical blocks). A physical block is composed of a plurality of pages (physical pages). For example, one physical page is composed of a 2048-byte user area and a 64-byte redundant area, and one physical block is composed of 64 physical pages. The redundant area is an area for storing additional data such as error-correcting code (ECC), logical address information, and block status (flag).

  The logical address information written in the redundant area is information for determining the correspondence between the physical block and the logical block. The block status (flag) is a flag indicating pass / fail of the physical block. In addition, a defective block that is a physical block to which data cannot be normally written includes an initial defective physical block that is defective from the time of shipment, and a late defective physical block that has deteriorated to become a defective block after use. There are blocks. For an initial defective physical block, a block status (flag) indicating a defective block is written by the manufacturer. Some manufacturers also write a block status (flag) indicating the initial defective physical block in the user area.

  In this embodiment, a virtual block is formed by two physical blocks belonging to different flash memories 2A and 2B, and a logical block is assigned to this virtual block. Accordingly, when an access instruction for instructing writing is given from the host system 4, the memory controller 3 identifies a virtual block corresponding to the logical block to which the area to be accessed designated by the access instruction belongs, Data corresponding to the access instruction is written into the two physical blocks forming the virtual block. In this data writing process, the memory controller 3 may perform the writing of data to the physical block belonging to the flash memory 2A and the writing of data to the physical block belonging to the flash memory 2B in parallel, or the physical controller belonging to the flash memory 2A. Data writing to a block and data writing to a physical block belonging to the flash memory 2B may be alternately performed. The latter is a so-called interleave method. In this method, when one flash memory is busy, data is written to the other flash memory that is not busy.

  Next, firmware stored in the firmware area of the SRAM 8 will be described with reference to FIG. In the following description, the minimum firmware necessary for startup stored in the ROM 12 in advance is referred to as “startup firmware” in order to distinguish it from firmware stored in the flash memory 2.

  In the present embodiment, only the minimum firmware (startup firmware) necessary at the time of startup is stored in the ROM 12. Therefore, the memory controller 3 must read the firmware stored in the flash memory 2 by executing the startup firmware at the time of startup and store it in the firmware area of the SRAM 8. Thereafter, the memory controller 3 operates based on the firmware stored in the firmware area of the SRAM 8. Whether the firmware is stored in the ROM 12 or the flash memory 2 can be appropriately determined by the designer when designing the memory controller 3. In this embodiment, firmware including a program code read by the microprocessor 6 and a sequence code read by the flash memory interface block 10 is stored in the flash memory 2, but only the program code or the sequence of the firmware is stored. Only the code may be stored in the flash memory 2.

  The program code stored in the firmware area A of the SRAM 8 is firmware that is read into the microprocessor 6, and the microprocessor 6 operates based on this program code. For example, the microprocessor 6 obtains the logical block to which the access target area specified by the access instruction given from the host system belongs and the physical block corresponding to the logical block based on the program code, or writes the data write destination. Search for free blocks.

  The sequence code stored in the firmware area B of the SRAM 8 is firmware that is read into the flash memory interface block 10, and the flash memory interface block 10 operates based on this sequence code. The sequence code includes a plurality of code sets composed of a plurality of codes set for each sequence process executed by the flash memory interface block 10, and the flash memory interface block 10 uses the flash memory 2A based on this code set. , 2B, various sequence processes are executed. When the flash memory interface block 10 executes a sequence process, a code set corresponding to the process to be executed is selected, and a code included in the selected code set is read into the flash memory interface block 10.

  Each code set corresponds to sequence processing such as formatting processing and writing processing. Each code included in the code set is for instructing the flash memory 2A, 2B to output a control signal, command, address, write data, or the like, or for instructing a branch destination based on the branch condition, There is an instruction to wait for the busy state of the flash memories 2A and 2B to be released.

  In addition, codes included in the code set are normally read in the order of addresses, but when a code indicating a branch destination is included, a code to be read next is determined according to a command code indicating a branch destination. .

  Every code set finally branches to an exit code. By branching to this end code, the sequence processing corresponding to each code set ends.

  Hereinafter, the operation of the memory controller 3 of the present embodiment will be described.

  At startup, the memory controller 3 operates based on the startup firmware stored in the ROM 12, and determines whether the firmware is written in the flash memory 2A and / or 2B. For example, information indicating the location where the firmware is written in the first block of the flash memory 2A or 2B (for example, the chip number of the flash memory to which the physical block to which the firmware is written and the physical block address of the physical block) Hereinafter, this is referred to as “firmware location information”). That is, when the firmware location information is written, it is determined that the firmware is written in the flash memory 2A and / or 2B. When the firmware location information is not written, the firmware is stored in the flash memory 2A and the flash memory 2A. It is determined that data is not written in 2B. Note that the firmware location information is written in the first block of the flash memory 2A or 2B because, in general, the manufacturer guarantees that the first block is not a defective block. For this reason, usually, attribute information (for example, information indicating what the flash memory system 1 is and how many flash memories are mounted) is written in the first block. User data (data written according to an access instruction given from the host system) is rarely written to the block.

  Hereinafter, the subsequent operation will be described separately for the case where it is determined that the firmware is written in the flash memory 2A and / or 2B and the case where it is determined that the firmware is not written.

  <When it is determined that the firmware has not been written in the flash memory 2A and / or 2B>.

The memory controller 3 enters a standby state waiting for the firmware from the host system 4.
As shown in FIG. 3A, when the firmware is given from the host system 4, the memory controller 3 writes the firmware into the firmware area in the SRAM 8 via the buffer 9. Thereafter, the memory controller 3 operates based on the firmware written in the SRAM 8.

  Next, (Processing A) to (Processing C) performed when it is determined that the firmware has not been written in the flash memory 2A and / or 2B will be described.

  (Processing A) It is determined whether or not the formatting process of the flash memory 2 has been completed. If the formatting process of the flash memory 2 has not been completed, the formatting process of the flash memory 2 is performed. In this formatting process, management information (for example, a defective block table) necessary for managing access to the flash memory 2 is created, and the created management information is written to the flash memory 2. For example, a case where a bad block table is created as management information will be described. In this creation process, the block status (flag) stored in the redundant area of each physical block in the flash memory 2A, 2B is sequentially read, and the flash memory 2A, 2A, 2B is read based on the read block status (flag). It is determined whether each physical block in 2B is a bad block. The physical block address of the physical block determined to be a bad block and information indicating the flash memory 2 to which the physical block belongs are written in the work area of the SRAM 8. In this way, a bad block table for managing bad blocks is created. From this defective block table, defective blocks in the respective flash memories 2A and 2B are specified, and the number of defective blocks included in the respective flash memories 2A and 2B is obtained.

  (Processing B) As shown in FIG. 3A, the firmware and management information are one or more in the two flash memories 2A and 2B via the buffer 9 as one data or as a plurality of data. Written to the physical block. Here, as for the firmware, the program code and the sequence code may be written in the same physical block, but the program code and the sequence code may be written in different physical blocks. Regarding the management information, each table such as a bad block table, a free block search table, and an address conversion table may be written in a different physical block for each table. Furthermore, a large table such as an address conversion table may be divided into a plurality of tables and written in different physical blocks. When writing firmware and management information, management is performed so that the sum of the number of defective blocks included in each of the flash memories 2A and 2B and the number of physical blocks to which management information and / or firmware is written is equalized. A physical block in the flash memory 2A or 2B to which information and firmware are written is determined. In other words, the management information and the firmware are written so that the total in the flash memory 2A and the total in the flash memory 2B are equalized with respect to the number of defective blocks and the management information and / or the number of physical blocks to which the firmware is written. The allocation of the physical block ahead is determined.

  For example, as shown in FIG. 4, it is assumed that two defective blocks exist in the flash memory 2A and one defective block exists in the flash memory 2B. Further, it is assumed that two physical blocks are used for storing firmware and three physical blocks are used for storing management information. The firmware is divided into two data (firmware parts # 0 and # 1) according to the capacity of the physical block, and the management information is divided into three data (management information parts # 0 to # 2). . However, frequently updated management information is divided in accordance with the physical page capacity, and each time the management information is updated, the updated management information is divided into empty pages (physical pages in which no data is written) in the same physical block. It is preferable to write sequentially.

  In this example, the flash memory 2A has one more defective block than the flash memory 2B. Therefore, the firmware blocks so that the physical block belonging to the flash memory 2B is one more than the physical block belonging to the flash memory 2A. Alternatively, a physical block used as a management information write destination is determined. That is, among these five physical blocks, two physical blocks belong to the flash memory 2A and the remaining three physical blocks belong to the flash memory 2B. It is determined. When the physical block to which the firmware and management information is written is thus determined, the sum of the number of defective blocks and the number of physical blocks to which the management information and / or firmware is written is determined by the flash memory 2A and the flash memory 2B. Will also be four.

  If the number of defective blocks in the flash memory 2A is three more than the number of defective blocks in the flash memory 2B, the number of physical blocks belonging to the flash memory 2B is three more than the physical blocks belonging to the flash memory 2A. In addition, a physical block to be used as a firmware or management information write destination is determined.

  For the physical block that becomes the write destination of the management information (for example, the address conversion table) that has not been created at the time of the format process, only the write destination physical block is reserved, and the management information at the time of the format process Is not written. With respect to such management information, the management information may be written into the reserved physical block when the management information is created.

  When the entire firmware is stored in the ROM 12, the management information is set so that the sum of the number of defective blocks included in the flash memories 2A and 2B and the number of physical blocks to which management information is written is equalized. The physical block in the flash memory 2A or 2B to be written to is determined.

  Further, when the management information is stored in a non-volatile memory provided separately from the flash memory 2, the number of defective blocks included in the flash memories 2A and 2B, the number of physical blocks in which firmware is written, The physical block in the flash memory 2A or 2B to which the firmware is to be written is determined so that the sum of the two is equalized.

  (Process C) Information indicating the location where management information is written in the first block of the flash memory 2A or the flash memory 2B (hereinafter referred to as management information location information) and firmware location information indicating the location where the firmware is written Written. The management information location information is information for specifying the physical block determined as the management information write destination. For example, the information indicating the chip number of the flash memory to which the physical block belongs and the physical block address of the physical block. included. The firmware location information is information for determining a physical block determined as a firmware write destination, and includes, for example, information indicating the chip number of the flash memory to which the physical block belongs and the physical block address of the physical block. .

  Note that the attribute information stored in the head block of the flash memory 2 is also included in the management information. However, in this embodiment, the head blocks of both the flash memory 2A and the flash memory 2B are used as attribute information write destinations. The description of the physical block in which the attribute information is stored has been omitted (because one physical block to which attribute information is written is assigned to each flash memory 2).

  <When it is determined that the firmware is written in the flash memory 2A and / or 2B>.

  As shown in FIG. 3B, the location where the firmware is written is specified based on the firmware location information written in the first block of the flash memory 2A or the flash memory 2B, and the firmware is read out from the specified location. Written to the firmware area.

  As for the management information, only the necessary management information is read from the flash memory 2A and / or 2B each time and written into the work area of the SRAM 8. When the content of the read management information is updated on the SRAM 8, the updated management information is written to the flash memories 2A and / or 2. Since such update processing is performed for management information, the number of physical blocks that can be used as the write destination of management information is usually larger than the minimum number of physical blocks necessary for storing management information. Is assigned more. That is, for the management information write destination physical block, the management information write destination physical block including the spare physical block is determined.

  As mentioned above, although embodiment of this invention was described, this is an illustration for description of this invention, Comprising: It is not the meaning which limits the scope of the present invention only to this embodiment. Of course, various modifications can be made without departing from the scope of the present invention.

  For example, after management information and firmware are written in the flash memories 2A and / or 2B, the number of defective blocks in the flash memories 2A and 2B increases, and the number of defective blocks included in the flash memory 2A and the flash memory 2B are included. The difference in the number of bad blocks may change. Therefore, the memory controller 3 changes the difference between the number of defective blocks included in the flash memory 2A and the number of defective blocks included in the flash memory 2B after management information and firmware are written into the flash memories 2A and / or 2B. In this case, the total sum of the number of defective blocks included in the respective flash memories 2A and 2B and the number of physical blocks in which management information and / or firmware is written is equalized. Management information and / or allocation of a physical block to which firmware is written may be changed. In this change, it is preferable that only the minimum number of physical blocks necessary for equalization is changed. Also, the storage data of the physical block that is no longer the management information and / or firmware write destination due to this change is transferred to or related to the physical block that is newly the management information and / or firmware write destination due to this change. It is preferable that the management information and / or the firmware is transferred to the physical block that has remained the writing destination.

  As described above, the defective blocks include an initial defective physical block that is defective from the time of shipment, and a late defective physical block that has deteriorated into a defective block after the start of use. The criteria for determining the physical block of the subsequent failure can be appropriately set by the designer at the time of designing. For example, when the processing status given from the flash memory at the time of writing or erasing is “fail”, when the read data includes an error exceeding a predetermined threshold, or a combination of these errors causes a late failure It may be determined that the physical block is.

1 is a block diagram showing a schematic configuration of a flash memory system according to an embodiment of the present invention. The structure of SRAM and firmware is shown. FIG. 3A shows the writing of firmware to the flash memory. FIG. 3B shows the reading of firmware from the flash memory. A state is shown in which the sum of the number of defective blocks and the number of physical blocks in which firmware and management information are written is equalized between the flash memories when the writing of the firmware and management information is completed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Flash memory system, 2A, 2B ... Flash memory, 3 ... Memory controller, 6 ... Microprocessor

Claims (6)

A memory controller for controlling access to a plurality of flash memories to be erased in physical block units in accordance with an access instruction given from a host system,
Counting means for counting the number of defective blocks included in each of the flash memories;
System block management means for allocating some physical blocks in the plurality of flash memories to system blocks in which system data for controlling or managing access to the plurality of flash memories is written;
System data writing means for writing the system data into one or a plurality of the system blocks as one data or divided into a plurality of data;
System data reading means for reading the system data from the system block;
Access control means for controlling access to the plurality of flash memories based on the system data;
With
The system block management means assigns the system blocks so that the sum of the number of defective blocks and the number of system blocks included in each flash memory is equalized.
A memory controller characterized by that. The system data includes firmware for controlling access to the plurality of flash memories,
2. The memory controller according to claim 1, wherein the system data reading unit reads the firmware from the system block at the time of activation. The access control means controls access to the plurality of flash memories in a group unit including a plurality of physical blocks belonging to different flash memories.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The system block management means equalizes the sum of the number of defective blocks and the number of system blocks included in each flash memory when the number of defective blocks included in the plurality of flash memories changes. To change the allocation of the system blocks,
The memory controller according to claim 1, wherein the memory controller is a memory controller. A memory controller according to any one of claims 1 to 4,
A flash memory system comprising a plurality of flash memories accessed by the memory controller. A method for controlling a plurality of flash memories in which erasure is performed in units of physical blocks in accordance with an access instruction given from a host system,
A counting step for counting the number of defective blocks included in each of the flash memories;
A system block management step for allocating some physical blocks in the plurality of flash memories to system blocks in which system data for controlling or managing access to the plurality of flash memories is written;
A system data writing step of writing the system data into one or a plurality of system blocks as one data or divided into a plurality of data;
A system data read step for reading the system data from the system block;
An access control step for controlling access to the plurality of flash memories based on the system data;
With
In the system block management step, the system blocks are allocated so that the sum of the number of defective blocks and the number of system blocks included in each of the flash memories is equalized.
A method for controlling a flash memory.

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