JPS60164244U

JPS60164244U - analog input device

Info

Publication number: JPS60164244U
Application number: JP4689384U
Authority: JP
Inventors: 関口　稔; 大森　和男
Original assignee: 横河電機株式会社
Priority date: 1984-03-30
Filing date: 1984-03-30
Publication date: 1985-10-31

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来のアナログ入力装置の第１の例を示すブロ
ック図、第２図は第１図におけるアナログ・デジタル変
換回路のタイミング図、第３図は従来のアナログ入力装
置の第２の例を示すブロック図、第４図は第３図におｉ
るアナログ・デジタル変換回路のタイミング図、第５図
は本考案の実施例を示すブロック図、第６図は第５図に
おけるタイミング制御回路のタイムチャート図、第７図
〜第９図は第５図におけるタイミング制御回路の他の切
換状態を示すタイムチャート図である。１・・・・・・マルチプレクサ、３・・・・・・アナロ
グ・デジタル変換回路、５・・・・・・ｃｐｕ、　６・
・・・・・バス、１４・・・・・・バッファメモリコン
トロール回路、１５・・・・・・　　　。制御回路、１６・・・・・・全点格納メモリ、１７・・
・・・・制御回路、１９・・・・・・バッファ、２１・
・・・・・読み出し制御回路。Figure 1 is a block diagram showing a first example of a conventional analog input device, Figure 2 is a timing diagram of the analog-to-digital conversion circuit in Figure 1, and Figure 3 is a second example of a conventional analog input device. The block diagram shown in Figure 4 is similar to Figure 3.
FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is a time chart diagram of the timing control circuit in FIG. 5. FIGS. FIG. 7 is a time chart diagram showing another switching state of the timing control circuit in the figure. 1...Multiplexer, 3...Analog-to-digital conversion circuit, 5...CPU, 6.
...Bus, 14...Buffer memory control circuit, 15... Control circuit, 16... All points storage memory, 17...
...Control circuit, 19...Buffer, 21.
...Reading control circuit.

Claims

[Scope of utility model registration request]

By multiplexing multiple analog inputs,
In the analog input device, the output is converted into a digital signal by an analog-to-digital conversion circuit and then sent to a computer, the first control means for controlling the multiplexing means and the analog-to-digital conversion circuit; a first memory in which the digital signal selected and controlled by the control means is stored; a second control means for controlling the multiplexing means and the analog-to-digital conversion circuit; A second memory in which the selected digital signal is stored; and a timing control circuit that determines which of the first control means and the second control means to use, and an analog input device for outputting data in the first memory or the second memory to the computer.