JPH0191955U

JPH0191955U -

Info

Publication number: JPH0191955U
Application number: JP18793187U
Authority: JP
Priority date: 1987-12-10
Filing date: 1987-12-10
Publication date: 1989-06-16

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるＲＡＭを用
いたＩ／Ｆ装置を示す概観図、第２図はこの考案
によるＲＡＭを用いたＩ／Ｆ装置のタイミングチ
ヤート図、第３図は従来のＲＡＭを用いたＩ／Ｆ
装置を示す概観図、第４図は従来のＲＡＭを用い
たＩ／Ｆ装置のタイミングチヤート図である。図において、１は第１の機器、２は第２の機器
、３はバスコントローラ、４は第１のＲＡＭ、５
は第２ＲＡＭ、６は第１のセレクタ、７は第２セ
レクタである。なお図中、同一符号は同一、又は
相当部分を示す。 FIG. 1 is an overview diagram showing an I/F device using RAM according to an embodiment of this invention, FIG. 2 is a timing chart of an I/F device using RAM according to this invention, and FIG. 3 is a conventional one. I/F using RAM
An overview diagram showing the device, FIG. 4 is a timing chart of a conventional I/F device using a RAM. In the figure, 1 is the first device, 2 is the second device, 3 is the bus controller, 4 is the first RAM, and 5 is the first device.
is a second RAM, 6 is a first selector, and 7 is a second selector. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

In an interface device that uses a RAM to transfer data between first and second devices having different processing times, a first RAM;
and read/write processing works in reverse while the above first
, a second RA that performs data communication between the second devices
M, a first selector that switches and connects a data bus of data output from the first device to either the first or second RAM, and a RAM that is switched and connected by the first selector. is another RAM
a second device that connects the data bus of the second device to
an interface device comprising: a selector; and control means for generating a bus switching control signal to the first and second selectors at a timing when communication between the first and second devices is completed. .