JPH0284954U - - Google Patents
Info
- Publication number
- JPH0284954U JPH0284954U JP16461788U JP16461788U JPH0284954U JP H0284954 U JPH0284954 U JP H0284954U JP 16461788 U JP16461788 U JP 16461788U JP 16461788 U JP16461788 U JP 16461788U JP H0284954 U JPH0284954 U JP H0284954U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- data bus
- transfer
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Retry When Errors Occur (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来のデータバス端末装置を示す図である。
図においては、１はデータバス端末装置、２は
制御回路、３はデータ変換回路、４はシリアルマ
ルチプレツクスバス、５はドライバ、６は外部機
器、７はインターフエイス回路、８は入力データ
一時記憶回路、９は逆変換回路、１０は比較回路
、１１は再転送回路である。なお、各図中同一符
号は同一あるいは相当部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional data bus terminal device. In the figure, 1 is a data bus terminal device, 2 is a control circuit, 3 is a data conversion circuit, 4 is a serial multiplex bus, 5 is a driver, 6 is an external device, 7 is an interface circuit, and 8 is an input data temporary storage. 9 is an inverse conversion circuit, 10 is a comparison circuit, and 11 is a retransfer circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
バス制御装置とが、シリアルデータバスラインを
介して接続された前記データバス端末装置と前記
バス制御装置間のデータ転送を前記バス制御装置
から発信するコマンド信号と、このコマンド信号
を受信した前記データバス端末装置から応答する
レスポンス信号とを前記バス制御装置が制御して
実行するコマンドレスポンスシリアルマルチプレ
ツクスデータ転送方式の前記データバス端末装置
において、入力されたデータをデータバスの転送
形式に適合する様波形を変換する際、正確に変換
されているかを監視するために入力データを一時
保持する入力データ一時記憶回路と、変換された
データを元の波形に戻す為の逆変換回路と、前記
入力データ一時記憶回路と前記逆変換回路からの
データを比較する比較回路と変換が不正確だつた
時に再度転送を行う為の再転送回路を備えるデー
タバス端末装置。 A plurality of data bus terminal devices and at least one bus control device are connected via a serial data bus line, and a command signal is sent from the bus control device to initiate data transfer between the data bus terminal devices and the bus control device. and a response signal from the data bus terminal device that has received this command signal. When converting a waveform to match the data bus transfer format, there is an input data temporary storage circuit that temporarily holds the input data to monitor whether it has been converted accurately, and the converted data is returned to the original waveform. A data bus terminal device comprising: an inverse conversion circuit for data transfer, a comparison circuit for comparing data from the input data temporary storage circuit with the data from the inverse conversion circuit, and a retransfer circuit for performing transfer again when the conversion is inaccurate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16461788U JPH0284954U (en) | 1988-12-20 | 1988-12-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16461788U JPH0284954U (en) | 1988-12-20 | 1988-12-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284954U true JPH0284954U (en) | 1990-07-03 |
Family
ID=31450384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16461788U Pending JPH0284954U (en) | 1988-12-20 | 1988-12-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284954U (en) |
-
1988
- 1988-12-20 JP JP16461788U patent/JPH0284954U/ja active Pending
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