JPH0444790U

JPH0444790U -

Info

Publication number: JPH0444790U
Application number: JP8778590U
Authority: JP
Priority date: 1990-08-20
Filing date: 1990-08-20
Publication date: 1992-04-16

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例によるデータ転送
処理装置を示すブロツク図、第２図及び第３図は
この考案の他の実施例を示すブロツク図、第４図
は従来のデータ転送処理装置を示すブロツク図で
ある。図において、１は出力データ、２はデータ・サ
ンプリング回路、３はサンプリング・データ、４
はデータ記憶回路、５は制御回路、６は中央処理
装置（ＣＰＵ）、７はデータサンプリング・タイ
ミング信号、８は転送用データ・サンプリング回
路、９は転送用サンプリング・データ、１０はパ
ラレル・シリアル変換回路、１１はシリアルサン
プリング・データ、１２はシリアル・パラレル変
換回路、１３はデータ収集指示信号、１４は入出
力回路、１５はバスラインを示す。なお、図中、
同一符号は同一、又は相当部分を示す。 FIG. 1 is a block diagram showing a data transfer processing device according to one embodiment of this invention, FIGS. 2 and 3 are block diagrams showing other embodiments of this invention, and FIG. 4 is a conventional data transfer processing device. FIG. In the figure, 1 is output data, 2 is data sampling circuit, 3 is sampling data, 4 is
is a data storage circuit, 5 is a control circuit, 6 is a central processing unit (CPU), 7 is a data sampling timing signal, 8 is a data sampling circuit for transfer, 9 is sampling data for transfer, 10 is a parallel-serial conversion 11 is a serial sampling data circuit, 12 is a serial/parallel conversion circuit, 13 is a data collection instruction signal, 14 is an input/output circuit, and 15 is a bus line. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

In a plurality of systems that collect various data, a central processing unit that centrally controls the master side system, and a master side control circuit that generates data sampling timing to sample data of all the systems according to instructions from the central processing unit;
A data sampling circuit on the master side that samples data of the master side system according to the data sampling timing, and a data sampling circuit on the slave side that samples data of the slave side system according to the data sampling timing from the master side system.・Based on the control of the sampling circuit and the control circuit of the master side system, the data on the slave side is
A parallel-to-serial conversion circuit on the slave side converts sampling data from a sampling circuit into serial data, and the serial data from the parallel-to-serial conversion circuit on the slave side is converted into required parallel data based on the control circuit of the master side system. A serial-to-parallel conversion circuit converts the parallel data from the master-side serial-to-parallel conversion circuit to the slave-side sampling data, and the sampling data from the master-side data sampling circuit together. 1. A data transfer processing device comprising: a data storage circuit of a master side system that stores data based on control of a control circuit of the master side system.