JPH01116844U - - Google Patents
Info
- Publication number
- JPH01116844U JPH01116844U JP1042788U JP1042788U JPH01116844U JP H01116844 U JPH01116844 U JP H01116844U JP 1042788 U JP1042788 U JP 1042788U JP 1042788 U JP1042788 U JP 1042788U JP H01116844 U JPH01116844 U JP H01116844U
- Authority
- JP
- Japan
- Prior art keywords
- address
- register
- state
- processing unit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000010365 information processing Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例を示す図、第２図
は従来の情報処理装置を示す図である。
図において、１は中央処理装置、２は演算回路
、３はアドレスステート、４はアドレス変換レジ
スタグループ、５は主記憶装置、６は入出力装置
、７はアドレス変換レジスタ、８はインターフエ
ース回路、９はバスライン、１１はアドレスステ
ートレジスタ、１２は比較回路、１０は制御回路
である。なお、各図中同一符号は同一または相当
部分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional information processing apparatus. In the figure, 1 is a central processing unit, 2 is an arithmetic circuit, 3 is an address state, 4 is an address conversion register group, 5 is a main storage device, 6 is an input/output device, 7 is an address conversion register, 8 is an interface circuit, 9 is a bus line, 11 is an address state register, 12 is a comparison circuit, and 10 is a control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
スラインを介して接続され構成される情報処理装
置において、前記入出力装置内に論理アドレスを
物理アドレスに変換するアドレス変換レジスタと
、前記アドレス変換レジスタの内容に対応する中
央処理装置のアドレスステートを保持するアドレ
スステートレジスタと、中央処理装置のアドレス
ステートと入出力装置のアドレス変換レジスタの
内容に対応するアドレスステートを保持するアド
レスステートレジスタの内容とを比較する比較回
路と、前記比較回路の結果からアドレスステート
に対応する中央処理装置のアドレス変換レジスタ
グループの内容を入出力装置のアドレス変換レジ
スタへ読み込む手段とを備えたことを特徴とする
情報処理装置。 In an information processing device configured by connecting a central processing unit, a main storage device, and an input/output device via a bus line, an address conversion register for converting a logical address into a physical address in the input/output device, and an address conversion register for converting a logical address into a physical address, and an address conversion register for converting a logical address into a physical address. An address state register that holds the address state of the central processing unit corresponding to the contents of the register, and an address state register that holds the address state of the central processing unit and the address state that corresponds to the contents of the address translation register of the input/output device. and a means for reading the contents of an address translation register group of a central processing unit corresponding to an address state from the result of the comparison circuit into an address translation register of an input/output device. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042788U JPH01116844U (en) | 1988-01-28 | 1988-01-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042788U JPH01116844U (en) | 1988-01-28 | 1988-01-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116844U true JPH01116844U (en) | 1989-08-07 |
Family
ID=31218080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1042788U Pending JPH01116844U (en) | 1988-01-28 | 1988-01-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116844U (en) |
-
1988
- 1988-01-28 JP JP1042788U patent/JPH01116844U/ja active Pending
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