JPS62158558U - - Google Patents

Info

Publication number
JPS62158558U
JPS62158558U JP4385386U JP4385386U JPS62158558U JP S62158558 U JPS62158558 U JP S62158558U JP 4385386 U JP4385386 U JP 4385386U JP 4385386 U JP4385386 U JP 4385386U JP S62158558 U JPS62158558 U JP S62158558U
Authority
JP
Japan
Prior art keywords
adder
sign bit
addition data
determination
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4385386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4385386U priority Critical patent/JPS62158558U/ja
Publication of JPS62158558U publication Critical patent/JPS62158558U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示すブロツク図
、第2図はこの考案の他の実施例を示すブロツク
図、第3図は第2図のブロツクをさらに具体的に
示す回路図、第4図は第3図の回路の動作を説明
するのに示したタイミングチヤート、第5図はV
TRのサーボ回路を示すブロツク図、第6図は第
5図のフイルタの構成を示す図、第7図は第6図
の加算器の例を示す図である。 43……加算器、44……判定回路、45……
レジスタ。
FIG. 1 is a block diagram showing one embodiment of this invention, FIG. 2 is a block diagram showing another embodiment of this invention, FIG. 3 is a circuit diagram showing the block of FIG. 2 in more detail, and FIG. Figure 4 is a timing chart shown to explain the operation of the circuit in Figure 3, and Figure 5 is a timing chart for explaining the operation of the circuit in Figure 3.
6 is a block diagram showing the servo circuit of the TR, FIG. 6 is a diagram showing the configuration of the filter shown in FIG. 5, and FIG. 7 is a diagram showing an example of the adder shown in FIG. 6. 43... Adder, 44... Judgment circuit, 45...
register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1、第2の加算データがシリアルに供給され
る加算器と、前記第1、第2の加算データの符号
ビツトを前記加算器の入力側から取込みこれらの
内容と、前記加算器の演算結果の符号ビツトを取
込む手段の出力内容との論理判定を行ない、前記
加算器のオーバーフロー、アンダーフローの判定
出力を得る判定手段と、この判定手段からの前記
オーバーフロー指示と前記アンダーフロー指示に
応じて前記加算器の出力を取込むレジスタに対し
てそれぞれ所定の値をセツトする設定手段とを具
備したことを特徴とする加算器補助回路。
an adder to which first and second addition data are serially supplied; a sign bit of the first and second addition data is taken in from the input side of the adder; these contents and the calculation result of the adder; determining means for performing a logical determination with the output content of the means for taking in the sign bit of the adder to obtain a determination output of overflow or underflow of the adder; An adder auxiliary circuit comprising: setting means for setting predetermined values to respective registers that receive outputs from the adder.
JP4385386U 1986-03-27 1986-03-27 Pending JPS62158558U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4385386U JPS62158558U (en) 1986-03-27 1986-03-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4385386U JPS62158558U (en) 1986-03-27 1986-03-27

Publications (1)

Publication Number Publication Date
JPS62158558U true JPS62158558U (en) 1987-10-08

Family

ID=30861106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4385386U Pending JPS62158558U (en) 1986-03-27 1986-03-27

Country Status (1)

Country Link
JP (1) JPS62158558U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02126295A (en) * 1988-11-07 1990-05-15 Kawai Musical Instr Mfg Co Ltd Musical sound data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02126295A (en) * 1988-11-07 1990-05-15 Kawai Musical Instr Mfg Co Ltd Musical sound data processing system

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