JPS6034643U - Erroneous access prohibition circuit - Google Patents

Erroneous access prohibition circuit

Info

Publication number
JPS6034643U
JPS6034643U JP12342283U JP12342283U JPS6034643U JP S6034643 U JPS6034643 U JP S6034643U JP 12342283 U JP12342283 U JP 12342283U JP 12342283 U JP12342283 U JP 12342283U JP S6034643 U JPS6034643 U JP S6034643U
Authority
JP
Japan
Prior art keywords
mode register
circuit
erroneous access
access prohibition
prohibition circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12342283U
Other languages
Japanese (ja)
Other versions
JPS6331143Y2 (en
Inventor
実 松田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP12342283U priority Critical patent/JPS6034643U/en
Publication of JPS6034643U publication Critical patent/JPS6034643U/en
Application granted granted Critical
Publication of JPS6331143Y2 publication Critical patent/JPS6331143Y2/ja
Granted legal-status Critical Current

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  • Storage Device Security (AREA)
  • Microcomputers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図は本考案の一実施例のブロック図である。 １・・・・・・選択回路、１−１．１−２・・・・・・
ＮＯＲゲート、２・・・・・・タイミング制御回路、２
−１・・・・・・ＯＲゲート、２−２．３・・・・・・
誤アクセス検出ゲート、２−３・・・・・・インバータ
、４・・・・・・モードレジスタ、５・・・・・・内部
バス、６・・・・・・アクセス選択信号、７・・・・・
・リセット信号、８・・・・・・モードレジスタアクセ
ス信号、９・・・・・・誤アクセス検出信号。The figure is a block diagram of an embodiment of the present invention. 1... Selection circuit, 1-1.1-2...
NOR gate, 2... Timing control circuit, 2
-1...OR gate, 2-2.3...
Erroneous access detection gate, 2-3... Inverter, 4... Mode register, 5... Internal bus, 6... Access selection signal, 7... ...
- Reset signal, 8...Mode register access signal, 9...Error access detection signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路の動作を規定するモードレジスタと、アクセス選択
信号により前記モードレジスタへのデータ設定を許可す
るか禁止するかの選択を行なう選択回路と、前記モード
レジスタへの入力タイミングを制御するタイミング制御
回路と、前記選択回路でデータ設定を禁止した後での前
記モードレジスタへの誤アクセスを検出する誤アクセス
検出回路とを備えることを特徴とする誤アクセス禁止同a mode register that defines the operation of the circuit; a selection circuit that selects whether to permit or prohibit data setting to the mode register based on an access selection signal; and a timing control circuit that controls input timing to the mode register. , an erroneous access detection circuit that detects erroneous access to the mode register after data setting is prohibited in the selection circuit;
JP12342283U 1983-08-09 1983-08-09 Erroneous access prohibition circuit Granted JPS6034643U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12342283U JPS6034643U (en) 1983-08-09 1983-08-09 Erroneous access prohibition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12342283U JPS6034643U (en) 1983-08-09 1983-08-09 Erroneous access prohibition circuit

Publications (2)

Publication Number Publication Date
JPS6034643U true JPS6034643U (en) 1985-03-09
JPS6331143Y2 JPS6331143Y2 (en) 1988-08-19

Family

ID=30281738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12342283U Granted JPS6034643U (en) 1983-08-09 1983-08-09 Erroneous access prohibition circuit

Country Status (1)

Country Link
JP (1) JPS6034643U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991130A (en) * 1972-12-29 1974-08-30
JPS5416333U (en) * 1977-07-06 1979-02-02

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS525921A (en) * 1975-07-01 1977-01-18 Sumitomo Cement Co Building method of slate outer wall and fittngs for fixation

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4991130A (en) * 1972-12-29 1974-08-30
JPS5416333U (en) * 1977-07-06 1979-02-02

Also Published As

Publication number Publication date
JPS6331143Y2 (en) 1988-08-19

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