JPS60126849U - Peripheral LSI for microcomputer - Google Patents

Peripheral LSI for microcomputer

Info

Publication number
JPS60126849U
JPS60126849U JP1380584U JP1380584U JPS60126849U JP S60126849 U JPS60126849 U JP S60126849U JP 1380584 U JP1380584 U JP 1380584U JP 1380584 U JP1380584 U JP 1380584U JP S60126849 U JPS60126849 U JP S60126849U
Authority
JP
Japan
Prior art keywords
microcomputer
operation mode
peripheral
peripheral lsi
setting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1380584U
Other languages
Japanese (ja)
Inventor
清浦 澄洋
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1380584U priority Critical patent/JPS60126849U/en
Publication of JPS60126849U publication Critical patent/JPS60126849U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は、それぞれ本考案の実施例による
周辺δ■の要部ブロック図である。 1・・・・・・周辺LSI本体、2・・・・・・状態保
持レジスタ、3・・・・・・状態保持レジスタ内容判別
回路、4・・・・・・内部信号線、5・・・・・・状態
信号出力端子、6・・・・・・データバス、7・・・・
・・内部状態出力制御信号線。
FIGS. 1 and 2 are block diagrams of main parts of the periphery δ■ according to embodiments of the present invention, respectively. 1... Peripheral LSI main body, 2... Status holding register, 3... Status holding register content determination circuit, 4... Internal signal line, 5... ...Status signal output terminal, 6...Data bus, 7...
・Internal status output control signal line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 機能がプログラマブルであり、定められた手順に従って
何段階かの設定を行うことによってその動作モードが決
定されるマイクロコンピュータ用周辺LSIにおいて、
その動作モードの設定段階、設定された動作モードおよ
びその動作モードの変化等を検出し、その状態を外部に
知らせる手段を有することを特徴とするマイクロコンピ
ュータ用周辺比I0
Peripheral LSIs for microcomputers whose functions are programmable and whose operating mode is determined by setting several stages according to a prescribed procedure.
Peripheral ratio I0 for a microcomputer, characterized by having means for detecting the setting stage of the operation mode, the set operation mode, changes in the operation mode, etc., and notifying the outside of the state.
JP1380584U 1984-02-03 1984-02-03 Peripheral LSI for microcomputer Pending JPS60126849U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1380584U JPS60126849U (en) 1984-02-03 1984-02-03 Peripheral LSI for microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1380584U JPS60126849U (en) 1984-02-03 1984-02-03 Peripheral LSI for microcomputer

Publications (1)

Publication Number Publication Date
JPS60126849U true JPS60126849U (en) 1985-08-26

Family

ID=30498147

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1380584U Pending JPS60126849U (en) 1984-02-03 1984-02-03 Peripheral LSI for microcomputer

Country Status (1)

Country Link
JP (1) JPS60126849U (en)

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