JPS61653U - DMA transfer circuit - Google Patents
DMA transfer circuitInfo
- Publication number
- JPS61653U JPS61653U JP8368284U JP8368284U JPS61653U JP S61653 U JPS61653 U JP S61653U JP 8368284 U JP8368284 U JP 8368284U JP 8368284 U JP8368284 U JP 8368284U JP S61653 U JPS61653 U JP S61653U
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- direct memory
- count
- terminal
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例を示すブロック図、第2図は
第1図に示す実施例の動作を示すタイムチャートである
。
1・・・システムバス、2・・・Z8QDMA. 3
・・・Z80CTC,4.7−NANDゲ−}、5,6
−J−Kフリツプフロツプ。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1...System bus, 2...Z8QDMA. 3
...Z80CTC, 4.7-NAND game}, 5,6
-J-K flip-flop.
Claims (1)
状態を挿入するWAIT端子および動作の中断を制御す
るRDY端子を有するダイレクトメモリアクセスコント
ローラと、カウント出力を上記ダイレクトメモリアクセ
スコントローラのWAIT端子へ与えて設定したカウン
ト値をカウントする時間間隔でデータ転送を制御する第
1のプログラマブルカウンタと、この第1のプログラマ
ブルカウンタのカウント出力をゲートを介して与えられ
てカウントしかつカウント出力を上記ダイレクトメモリ
アクセスコントローラのRDY端子へ与えてデータ転送
を中断させる第2のプログラマブルカウンタとを具備す
ることを特徴とするDMAi転送回路。A direct memory access controller that has a WAIT terminal that inserts a wait state into data transfer by direct memory access operation and an RDY terminal that controls interruption of the operation, and a count value that is set by applying a count output to the WAIT terminal of the direct memory access controller. a first programmable counter that controls data transfer at time intervals for counting; a count output of the first programmable counter is applied via a gate to count the count output; and the count output is sent to the RDY terminal of the direct memory access controller; and a second programmable counter that interrupts data transfer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8368284U JPS61653U (en) | 1984-06-06 | 1984-06-06 | DMA transfer circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8368284U JPS61653U (en) | 1984-06-06 | 1984-06-06 | DMA transfer circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61653U true JPS61653U (en) | 1986-01-06 |
JPH0116194Y2 JPH0116194Y2 (en) | 1989-05-12 |
Family
ID=30632529
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8368284U Granted JPS61653U (en) | 1984-06-06 | 1984-06-06 | DMA transfer circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61653U (en) |
-
1984
- 1984-06-06 JP JP8368284U patent/JPS61653U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH0116194Y2 (en) | 1989-05-12 |
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