JPS61653U - DMA transfer circuit - Google Patents

DMA transfer circuit

Info

Publication number
JPS61653U
JPS61653U JP8368284U JP8368284U JPS61653U JP S61653 U JPS61653 U JP S61653U JP 8368284 U JP8368284 U JP 8368284U JP 8368284 U JP8368284 U JP 8368284U JP S61653 U JPS61653 U JP S61653U
Authority
JP
Japan
Prior art keywords
memory access
direct memory
count
terminal
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8368284U
Other languages
Japanese (ja)
Other versions
JPH0116194Y2 (en
Inventor
雄司 藤田
Original Assignee
菊水電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 菊水電子工業株式会社 filed Critical 菊水電子工業株式会社
Priority to JP8368284U priority Critical patent/JPS61653U/en
Publication of JPS61653U publication Critical patent/JPS61653U/en
Application granted granted Critical
Publication of JPH0116194Y2 publication Critical patent/JPH0116194Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロック図、第２図は
第１図に示す実施例の動作を示すタイムチャートである
。 １・・・システムバス、２・・・Ｚ８ＱＤＭＡ． ３
・・・Ｚ８０ＣＴＣ，４．７−ＮＡＮＤゲ−｝、５，６
−Ｊ−Ｋフリツプフロツプ。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1...System bus, 2...Z8QDMA. 3
...Z80CTC, 4.7-NAND game}, 5,6
-J-K flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダイレクトメモリアクセス動作によるデータ転送に待ち
状態を挿入するＷＡＩＴ端子および動作の中断を制御す
るＲＤＹ端子を有するダイレクトメモリアクセスコント
ローラと、カウント出力を上記ダイレクトメモリアクセ
スコントローラのＷＡＩＴ端子へ与えて設定したカウン
ト値をカウントする時間間隔でデータ転送を制御する第
１のプログラマブルカウンタと、この第１のプログラマ
ブルカウンタのカウント出力をゲートを介して与えられ
てカウントしかつカウント出力を上記ダイレクトメモリ
アクセスコントローラのＲＤＹ端子へ与えてデータ転送
を中断させる第２のプログラマブルカウンタとを具備す
ることを特徴とするＤＭＡｉ転送回路。A direct memory access controller that has a WAIT terminal that inserts a wait state into data transfer by direct memory access operation and an RDY terminal that controls interruption of the operation, and a count value that is set by applying a count output to the WAIT terminal of the direct memory access controller. a first programmable counter that controls data transfer at time intervals for counting; a count output of the first programmable counter is applied via a gate to count the count output; and the count output is sent to the RDY terminal of the direct memory access controller; and a second programmable counter that interrupts data transfer.
JP8368284U 1984-06-06 1984-06-06 DMA transfer circuit Granted JPS61653U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8368284U JPS61653U (en) 1984-06-06 1984-06-06 DMA transfer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8368284U JPS61653U (en) 1984-06-06 1984-06-06 DMA transfer circuit

Publications (2)

Publication Number Publication Date
JPS61653U true JPS61653U (en) 1986-01-06
JPH0116194Y2 JPH0116194Y2 (en) 1989-05-12

Family

ID=30632529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8368284U Granted JPS61653U (en) 1984-06-06 1984-06-06 DMA transfer circuit

Country Status (1)

Country Link
JP (1) JPS61653U (en)

Also Published As

Publication number Publication date
JPH0116194Y2 (en) 1989-05-12

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