JPS5984628U - Peripheral control system - Google Patents
Peripheral control systemInfo
- Publication number
- JPS5984628U JPS5984628U JP18078682U JP18078682U JPS5984628U JP S5984628 U JPS5984628 U JP S5984628U JP 18078682 U JP18078682 U JP 18078682U JP 18078682 U JP18078682 U JP 18078682U JP S5984628 U JPS5984628 U JP S5984628U
- Authority
- JP
- Japan
- Prior art keywords
- external buffer
- control system
- data
- buffer device
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のコンピュータによる周辺装置制御システ
ムの概略構成を示すブロック図、第２図は本考案に係る
周辺装置システムの一実施例のブロック図である。
１０・・・ＣＰＵ、１２・・・ＣＰＵバス、１４・・・
ラインプリンタコントローラ、１４′・・・紙テープリ
ーグパンチコントローラ、１６・・・ラインプリンタ、
１６′・・・紙テープ、１８・・・外部バッファ装置＼
２０・・・ＤＭＡデバイス、２２・・・外部バス。FIG. 1 is a block diagram showing a schematic configuration of a conventional computer-based peripheral device control system, and FIG. 2 is a block diagram of an embodiment of the peripheral device system according to the present invention. 10...CPU, 12...CPU bus, 14...
Line printer controller, 14'... paper tape league punch controller, 16... line printer,
16'...Paper tape, 18...External buffer device\
20...DMA device, 22...external bus.
Claims (1)
制御する周辺装置制御システムにおいて、前記ＣＰＵバ
スにＤＭＡデバイスと外部バッファ装置を接続すると共
に、前記外部バッファ装置に外部バスを介して前記周辺
装置を接続してなり、前記ＤＭＡデバイスにより前記外
部バッファ装置へ各周辺装置に対応した入力データをＤ
ＭＡ転送し、該外部バッファ装置への入出力データの転
送完了時点で、データ以外あ各周辺装置についての転送
処理の可否やデータ量等を前記ＣＰＵに該外部バッファ
装置から割込データとして転送することを特徴とする周
辺装置制御システム。In a peripheral device control system that controls input/output of peripheral devices via a CPU bus under the supervision of a CPU, a DMA device and an external buffer device are connected to the CPU bus, and a DMA device and an external buffer device are connected to the external buffer device via an external bus. devices are connected, and input data corresponding to each peripheral device is transferred to the external buffer device by the DMA device.
MA transfer is performed, and when the transfer of input/output data to the external buffer device is completed, information other than the data, such as whether transfer processing can be performed and the amount of data for each peripheral device, is transferred from the external buffer device to the CPU as interrupt data. A peripheral device control system characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18078682U JPS5984628U (en) | 1982-11-29 | 1982-11-29 | Peripheral control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18078682U JPS5984628U (en) | 1982-11-29 | 1982-11-29 | Peripheral control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5984628U true JPS5984628U (en) | 1984-06-07 |
Family
ID=30391904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18078682U Pending JPS5984628U (en) | 1982-11-29 | 1982-11-29 | Peripheral control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5984628U (en) |
-
1982
- 1982-11-29 JP JP18078682U patent/JPS5984628U/en active Pending
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